DisplayPort VIP Output Board Evaluation Board User Guide FPGA-EB-02015-1.0 March 2018 DisplayPort VIP Output Board Evaluation Board User Guide Contents Acronyms in This Document .................................................................................................................................................3 1. Introduction ..................................................................................................................................................................4 1.1. Further Information ................................................................................................................................................ 5 2. Functional Description ..................................................................................................................................................6 2.1. Switches .................................................................................................................................................................. 6 2.2. DisplayPort Interface .............................................................................................................................................. 6 2.3. LVDS Translator ...................................................................................................................................................... 6 2.4. Clock Interface ........................................................................................................................................................ 6 3. High-Speed Headers .....................................................................................................................................................7 4. Power Supply ................................................................................................................................................................9 5. User LEDs and Headers ...............................................................................................................................................10 6. Ordering Information ..................................................................................................................................................11 References ..........................................................................................................................................................................12 Technical Support Assistance .............................................................................................................................................12 Appendix A. DisplayPort VIP Output Board Schematics .....................................................................................................13 Appendix B. DisplayPort VIP Output Board Bill of Materials ..............................................................................................16 Revision History ...................................................................................................................................................................19 Figures Figure 1.1. Top View of DisplayPort VIP Output Board.........................................................................................................4 Figure 1.2. Bottom View of DisplayPort VIP Output Board ..................................................................................................5 Figure 2.1 Functional Block Diagram ....................................................................................................................................6 Figure 4.1 Power Supply .......................................................................................................................................................9 Figure A.1. Block Diagram ...................................................................................................................................................13 Figure A.2. DP Redriver and Connector I/F .........................................................................................................................14 Figure A.3. Power, Debug LED, Header I/F .........................................................................................................................15 Tables Table 3.1. Connector J1 ........................................................................................................................................................7 Table 3.2. Connector J2 ........................................................................................................................................................8 Table 5.1 User LEDs.............................................................................................................................................................10 Table 6.1. Reference Part Number .....................................................................................................................................11 (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide Acronyms in This Document A list of acronyms used in this document. Acronym DP I2C LDO LED LVDS mDP VIP Definition DisplayPort Inter-Integrated Circuit Low Dropout Light-emitting Diode Low-Voltage Differential Signaling Mini DisplayPort Video Interface Platform (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 3 DisplayPort VIP Output Board Evaluation Board User Guide 1. Introduction This document describes the Lattice Semiconductor DisplayPort(R) VIP Output Board. This board is designed to work with the Lattice Video Interface Platform (VIP) board interconnect system. This user guide includes descriptions of board components, schematics, and bill of materials. Key features of the DisplayPort VIP Output Board include: Integrated Texas Instruments SN75DP130 DisplayPort 1:1 Redriver Mini DisplayPort (mDP) connector Two 60-pin Rugged High-Speed Headers Figure 1.1 shows the top view of the DisplayPort VIP Output Board and its key components. Figure 1.2 shows the bottom view of the board. User LEDs 3.3 V Power to mDP Connector (Not populated) User Header SN65MLVD200 System Reset Mini DisplayPort Connector 135 MHz Clock SN75DP130 Figure 1.1. Top View of DisplayPort VIP Output Board (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide Downstream Connector (J2) Downstream Connector (J1) Figure 1.2. Bottom View of DisplayPort VIP Output Board 1.1. Further Information The following references provide detailed information on the DisplayPort VIP Output Board: Appendix A. DisplayPort VIP Output Board Schematics Appendix B. DisplayPort VIP Output Board Bill of Materials For more information on boards and kits available for the VIP (Video Interface Platform) system visit www.latticesemi.com/boards For details on the Texas Instruments SN75DP130, visit the Texas Instruments website at www.ti.com (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 5 DisplayPort VIP Output Board Evaluation Board User Guide 2. Functional Description The DisplayPort VIP Output board receives up to 4-lanes of DisplayPort from the upstream processor board through connector J1. The DisplayPort Main Link, Control and Aux Channel are sent through the TI DisplayPort re-driver, which regenerates the DisplayPort high-speed digital link to the mini DisplayPort connector. DisplayPort Main Link (4 lanes) DisplayPort Main Link (4 lanes) HPD/CAD/Control J1 Aux Channel SN75DP130 U1 HPD/CAD/Control Aux Channel mDP Connector CN1 Figure 2.1 Functional Block Diagram 2.1. Switches The push button switch, SW1, controls the reset signal RESET. Pressing SW1 provides logic 0 to the SN75DP130 RSTN pin. RESET is connected to GSRN on connecter J1, allowing SW1 to control the reset signal for other connected boards. 2.2. DisplayPort Interface The mini DisplayPort connector, CN1, connects the DisplayPort VIP Output Board to a DisplayPort sink. If PWR Out is required on Pin 20, the user must populate the 3.3 V Low Dropout (LDO) regulator, U4, and short jumper J4. 2.3. LVDS Translator The SN65MLV200 LVDS Driver/Receiver, U2, can be used to translate the LVDS AUX Channel to single ended I/O. This can be used if the upstream processor board is unable to receive LVDS. The single ended I/O are routed to connector J2. 2.4. Clock Interface The 135 MHz LVDS clock, U3, can be used as a reference clock for the upstream processor board. This clock is routed to connector J1. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide 3. High-Speed Headers The two 60-pin high-speed headers, connectors J1 and J2, are used to connect to an upstream host processor board. Table 3.1. Connector J1 J1 Connector Pin 1 2 3 4 5 6 7 8 9 11 13 14 19 20 26 28 30 32 34 36 38 40 41 42 43 44 46 48 50 52 54 55 56 58 60 10, 12, 15, 16, 17, 18, 21, 22, 23, 24, 25, 27, 29, 31, 33, 35, 37, 39, 45, 47, 49, 51, 53, 57, 59 Signal Name GND 12V CLK135_P 12V CLK135_N 12V GND 12V AUX_P AUX_N GND GND GND GND GND RESET HPD_SRC CAD_SRC GND TXP0_D0CH0 TXN0_D0CH0 GND SCL_CTL TXP0_D0CH1 SDA_CTL TXN0_D0CH1 GND TXP0_D1CH0 TXN0_D1CH0 GND TXP0_D1CH1 GND TXN0_D1CH1 GND TP14 Not Connected SN75DP130 pin -- -- -- -- -- -- -- -- AUX_SRCp AUX_SRCn -- -- -- -- -- RSTN HPD_SRC CAD_SRC -- IN0p IN0n -- SCL_CTL IN1p SDA_CTL IN1n -- IN2p IN2n -- IN3p -- IN3n -- -- -- Description -- -- 135 MHz LVDS Clock -- 135 MHz LVDS Clock -- -- -- DisplayPort Auxiliary Data Channel DisplayPort Auxiliary Data Channel -- -- -- -- -- Global System Reset Hot Plug Detect DP Cable Adapter Detect -- DisplayPort Main Link Lane 0 DisplayPort Main Link Lane 0 -- I2C Interface to SN75DP130 DisplayPort Main Link Lane 1 I2C Interface to SN75DP130 DisplayPort Main Link Lane 1 -- DisplayPort Main Link Lane 2 DisplayPort Main Link Lane 2 -- DisplayPort Main Link Lane 3 -- DisplayPort Main Link Lane 3 -- -- -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 7 DisplayPort VIP Output Board Evaluation Board User Guide Table 3.2. Connector J2 J1 Connector Pin 1 2 3 4 7 8 9 10 11 12 13 14 20 21 30 32 39 40 44 46 48 50 52 53 55 56 57 58 59 60 5, 6, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 31, 33, 34, 35, 36, 37, 38, 41, 42, 43, 45, 47, 49, 51, 54 Signal Name 3.3V 3.3V 3.3V 3.3V AUX_EN LED1 AUX_OUT LED2 AUX_IN LED3 EN LED4 GND GND SDA_DDC SCL_DDC GND GND HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 GND GND GND 2.5V 2.5V 2.5V 2.5V Not Connected SN75DP130 pin -- -- -- -- -- -- -- -- -- -- EN -- -- -- SDA_DDC SCL_DDC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Description -- -- -- -- Aux Channel Translator Enable User LED Aux Channel single ended Out User LED Aux Channel single ended In User LED SN75DP130 Enable User LED -- -- I2C Display Data Channel I2C Display Data Channel -- -- User I/O Header J3 User I/O Header J3 User I/O Header J3 User I/O Header J3 User I/O Header J3 -- -- -- -- -- -- -- -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide 4. Power Supply Board power is supplied through connectors J1 and J2. Figure 4.1 shows the power distribution scheme. To provide power to the mini DisplayPort connector, install a 5.0 V to 3.3 V LDO at U4 and add shunt to jumper J4. 2.5 V from J2 Status LED D5 3.3 V from J2 Status LED D7 12 V from J1 Status LED D6 LDO* U4 3.3 V, 500 mA J4 mDP Connector CN1 * Not Installed Figure 4.1 Power Supply (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 9 DisplayPort VIP Output Board Evaluation Board User Guide 5. User LEDs and Headers Four discrete LEDs (light-emitting diodes) are available to the user. These are driven by the upstream processor board through connector J2. Table 5.1 User LEDs Signal LED1 LED2 LED3 LED4 LED # D1 D2 D3 D4 Connector J2 Pin 8 10 12 14 Color Green Green Green Green An 8-pin 100-mil header, J3, is available to the user. There are five user connections routed to the upstream connector J2. Table 5.2 User Header Signal 3V3 HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 RESET GND Header J3 Pin 1 2 3 4 5 6 7 8 Connector J2 Pin -- 44 46 48 50 52 -- -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide 6. Ordering Information Please visit www.latticesemi.com/boards for the latest ordering information. Table 6.1. Reference Part Number Description DisplayPort VIP Output Board Ordering Part Number DP-VIP-O-EVN (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 11 DisplayPort VIP Output Board Evaluation Board User Guide References For more information, refer to Lattice Embedded Vision Development Kit User Guide (FPGA-UG-02015) ECP5 VIP Processing Board (FPGA-EB-02001) Technical Support Assistance Submit a technical support case through www.latticesemi.com/techsupport. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide Appendix A. DisplayPort VIP Output Board Schematics 5 4 3 2 1 DisplayPort VIP Output Board D D 5V,3V3,2V5 OnBoard LDO (pg4) I2C C GPIO I/F DP AUX I/F (pg3&4) Downstream Connector 1&2 C SN75DP130 (pg3) LED & Header I/F (pg4) X4 DP Data Control GPIO X4 DP Data Mini DP Connector B B (pg3) A A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com Title Title & Index Size B Date: 5 4 3 Project DisplayPort VIP Output Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 2 of 4 A 1 Figure A.1. Block Diagram (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 13 DisplayPort VIP Output Board Evaluation Board User Guide 5 4 3 2 1 3V3_TX 1 6 12 25 32 36 3V3 R1 4.7k R4 4.7k SDA_DDC SCL_DDC SDA_DDC {4} SCL_DDC {4} TXP0_D0CH0 TXN0_D0CH0 C1 TXP0_D0CH1 TXN0_D0CH1 C10 TXP0_D1CH0 TXN0_D1CH0 C11 100nF TXP0_D1CH1 TXN0_D1CH1 C13 100nF C3 100nF 38 39 C4 100nF 41 42 C6 100nF 44 45 100nF 47 48 100nF 100nF SDA_CTL SCL_CTL C18 3V3 C15 SDA_DDC 0 SCL_DDC 0 R6 R8 34 33 CAD_SRC 0 HPD_SRC 0 R10 R12 8 9 30 29 0.1uF AUX_P R18 51E R17 2.49K 7 15 21 46 43 40 37 C C20 R22 1.5K 10uF C21 R23 51E 0.1uF OUT0p OUT0n IN1p IN1n OUT1p OUT1n IN2p IN2n OUT2p OUT2n IN3p IN3n SDA_DDC SCL_DDC CAD_SRC HPD_SRC AUX_SRCp AUX_SRCn NC1 NC2 NC3 NC4 NC5 NC6 NC7 OUT3p OUT3n RSTn EN SCL_CTL SDA_CTL CAD_SINK HPD_SINK AUX_SINKp AUX_SINKn 23 22 C2 20 19 C8 17 16 C12 100nF 14 13 C14 100nF 0 C7 100nF 3 5 C5 100nF 9 11 C9 100nF 15 17 C16 100nF 10 12 {3,4} C17 1uF RST_N 100nF 100nF R39 RESET 35 26 0 R5 4 5 0 0 R7 R9 SCL_CTL SDA_CTL 10 11 28 27 0 0 0 0 R11 R13 R15 R19 CAD_SINK HPD_SINK EN 16 18 {4} HPD_SINK R40 R41 2 20 DP_3V3 CAD_SINK 4 6 R20 100K100K 3V3 13 14 19 7 8 1 R21 3V3_TX ADDR_EQ 100K C19 3 1uF 1M SN75DP130SS C25 CN1 IN0p IN0n E-PAD(GND) R3 4.7k GND GND GND R2 4.7k VDDD_DREG 2 24 18 31 D VCC VCC VCC VCC VCC VCC U1 C22 C23 C24 100nF 100nF 1uF ML_LANE0P ML_LANE0N D ML_LANE1P ML_LANE1N ML_LANE2P ML_LANE2N ML_LANE3P ML_LANE3N AUX_CHP AUX_CHN HPD DPPOWER CONFIG1 CONFIG2 GND1 GND2 GND3 GND4 GND5 GND6 C Mini-DP 0.1uF AUX_N 3V3 U2 SCL_CTL SDA_CTL A 2V5 0 0 DNI A AUX_IN RESET HPD_SRC CAD_SRC 6 R28 4.7k OUT_P EN OUT_N AUX_P 6 R 2 0.1uF B 1 VDD AUX_N 7 NC GND 4 CLK135_P 5 CLK135_N B 3 DSC1103CE2-135.0000 7 {4} 1 U3 R26 R27 C27 RE# AUX_P AUX_N AUX_OUT 3V3 D 2 B {4} 4 5 GND CLK135_P CLK135_N 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 {4} DE 3 12V J1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 VCC 8 AUX_EN 0.1uF E-PAD C26 SN65MLVD200 {3,4} TXP0_D0CH0 TXN0_D0CH0 3V3 TXP0_D0CH1 TXN0_D0CH1 TXP0_D1CH0 TXN0_D1CH0 TXP0_D1CH1 TXN0_D1CH1 1 3V3_TX L4 2 1 60ohms 2.3A C28 C29 C30 C31 C32 C33 C34 C35 10uF 1uF 100nF 100nF 100nF 100nF 100nF 100nF A Lattice Semiconductor Applications Email: techsupport@Latticesemi.com TP14 Title DP Redriver & Connector I/F PLACE DE-CAPS CLOSE TO THEIR POWER PINS ERM5-030-05.0-L-DV-K-TR Size B Date: 5 4 3 Project DisplayPort VIP Output Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 3 of 4 A 1 Figure A.2. DP Redriver and Connector I/F (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide 5 4 3 2 1 D D NOTE : PLACE SWITCH IN THE TOP SIDE 3V3 REG_3V3 DP3V3 DP_3V3 12V U4 LT1086CM-3.3 700mA traces 3 10uF Vin Vout GND TAB 2 1 0.1uF 1 C37 4 10uF R29 2 2 1 FUSE 0.1uF C36 1 EXTERNAL RESET J4 U16 700mA traces L2 2 1 60ohms 500mA 2 SW1 SYS_RST Jumper 4.7k C39 C38 DNI 2 4 D8 1 3 RESET RESET {3} C40 0.1uF D1213A-01WS-7 C C 3V3 R33 R34 330E 330E 330E D3 Green 3V3 D4 Green LED2 LED3 SDA_DDC SCL_DDC {3} {3} J3 1 2 3 4 5 6 7 8 HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 RESET 2 D2 Green 2 D1 Green 2 LED1 2 LED1 LED2 LED3 LED4 1 R32 330E 1 R31 B LED4 8 HEADER HEADER1 HEADER2 HEADER3 HEADER4 HEADER5 12V 3V3 12V R37 R36 R35 1K 330E 1 EXT_2V5 2V5 1K D5 Green L8 ERM5-030-05.0-L-DV-K-TR 2 1 60ohms 2.3A 1 TP13 D6 Green D7 Green Q1 MMBT2222A 2 2 A 2V5 32 EXT_2V5 3V3 1 A R38 10K Lattice Semiconductor Applications Email: techsupport@Latticesemi.com 2 B 3V3 1 AUX_EN AUX_OUT AUX_IN EN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 1 {3} {3} {3} {3} 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 1 L6 2 1 60ohms 2.3A J2 EXT_3V3 3V3 3V3 1 EXT_3V3 Title Power,Debug LED,Header I/F Size B Date: 5 4 3 Project DisplayPort VIP Output Board Friday, 11-Nov-16 2 Sheet Schematic Rev 0.1 Board Rev 4 of 4 A 1 Figure A.3. Power, Debug LED, Header I/F (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 15 DisplayPort VIP Output Board Evaluation Board User Guide Appendix B. DisplayPort VIP Output Board Bill of Materials Item Reference Qty Value Comments Part Number Manufacturer Description 1 CN1 1 Mini-DP -- 2129320-3 TE Connectivity MINI DISPLAYPORT REVERSE OFFSET 2 C1,C2,C3,C4,C5,C6,C7,C8, C9,C10,C11,C12,C13,C14, C15,C16 16 100 nF -- 885012205018 Wurth CAP CER 0.1UF 10V X7R 0402 3 C17,C19,C24,C29 4 1 uF -- GRM155R61A105KE15 D Murata CAP CER 1uf 10V 10% X5R 0402 4 C18,C21,C25,C26,C27 5 0.1 uF -- GRM155R61A104KA01 D Murata CAP CER 0.1UF 10V X5R 0402 5 C20,C28 2 10 uF -- GRM21BR61A106KE19L Murata CAP CER 10UF 10V X5R 0805 6 C22,C23,C30,C31,C32,C33, C34,C35 8 100 nF -- GRM155R61A104KA01 D Murata CAP CER 0.1UF 10V X5R 0402 7 C36,C38 2 10 uF -- C1608X5R1E106M080A C TDK Corporation CAP CER 10UF 25V X5R 0603 8 C37,C39 2 0.1 uF -- CL05A104KA5NNNC Samsung CAP CER 0.1UF 25V X5R 0402 9 C40 1 0.1 uF -- 885012205037 Wurth CAP CER 0.1UF 16V X7R 0402 10 D1,D2,D3,D4,D5,D6,D7 7 Green -- LTST-C190KGKT LITE-On INC LED SUPER GREEN CLEAR 0603 SMD 11 D8 1 D1213A-01WS-7 -- D1213A-01WS-7 Diodes Incorporated TVS DIODE 3.3VWM 10VC SOD323 12 J1,J2 2 ERM5-030-05.0-LDV-K-TR -- ERM5-030-050-L-DV-KTR Samtec Inc Conn High Speed Edge Rate Terminal Strip HDR 60 POS 0.5mm Solder ST SMD T/R - 13 J3 1 8 HEADER -- -- -- General purpose 100 Mils header 14 J4 1 Jumper -- -- -- General purpose 100 mils 1x2 Header 15 L2 1 60 500 mA -- MMZ1608Y600BTA00 TDK FERRITE BEAD 60 OHM 0603 1LN (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide Item Reference Qty Value Comments Part Number Manufacturer Description 16 L4,L6,L8 3 60 2.3 A -- MPZ1608Y600BTA00 TDK FERRITE BEAD 60 OHM 0603 1LN 17 Q1 1 MMBT2222A -- MMBT2222A,215 NXP Semiconductor TRANS NPN 40V 0.6A SOT23 18 R1,R2,R3,R4,R28,R29 6 4.7 k -- CRCW06034K70FKEA Vishay RES SMD 4.7K OHM 1% 1/10W 0603 19 R5,R6,R7,R8,R9,R10,R11, R12,R13,R15,R19,R27,R39 13 0 -- RC0603JR-070RL Yageo RES SMD 0.0OHM JUMPER 1/10W 0603 20 R26 1 0 DNL RC0603JR-070RL Yageo RES SMD 0.0OHM JUMPER 1/10W 0603 21 R17 1 2.49 K -- ERA-2AEB2491X Panasonic RES SMD 2.49KOHM 0.1% 1/16W 0402 22 R18,R23 2 51E -- ERJ-2GEJ510X Panasonic RES SMD 51 OHM 5% 1/10W 0402 23 R20,R40,R41 3 100 K -- ERA-2AEB104X Panasonic RES SMD 100K OHM 0.1% 1/16W 0402 24 R21 1 1M -- ERJ-2GEJ105X Panasonic RES SMD 1M OHM 5% 1/10W 0402 25 R22 1 1.5 K -- ERJ-2RKF1501X Panasonic RES SMD 1.5K OHM 1% 1/10W 0402 26 R31,R32,R33,R34,R36 5 330E -- CRCW0402330RFKED Vishay Dale RES SMD 330 OHM 1% 1/16W 0402 27 R35 1 1K -- RC0603FR-071KL Yageo RES SMD 1K OHM 1% 1/10W 0603 28 R37 1 1K -- RMCF0402JT1K00 Stackpole Electronics Inc RES SMD 1K OHM 5% 1/16W 0402 29 R38 1 10 K -- ERJ-3EKF1002V Panasonic RES SMD 10K OHM 1% 1/10W 0603 30 SW1 1 SYS_RST -- 434153017835 Wurth SWITCH TACTILE SPST-NO 0.05A 12V 31 TP13,TP14 2 TEST POINT -- 22-28-4020 Molex Test Point 0.1" 32 U1 1 SN75DP130SS -- SN75DP130SSRGZR Texas Instruments IC DISPLYPRT 1:1 REDRIVR 48VQFN 33 U2 1 SN65MLVD200 -- SN65MLVD200AD Texas Instruments IC LVDS LINE DVR/RCVR 8-SOIC (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 17 DisplayPort VIP Output Board Evaluation Board User Guide Item Reference Qty Value Comments Part Number Manufacturer Description 34 U3 1 DSC1103CE2135.0000 -- DSC1103CE2-135.0000 Microchip Technology Inc Standard Clock Oscillators -20C - 70C 25 ppm 135.0000MHz 35 U4 1 LT1086CM-3.3 DNI LT1086CM-3.3#TRPBF Linear Tech IC REG LDO 3.3V 1.5A D2PAK 36 U16 1 FUSE -- 0154004.DRT Littelfuse Inc. FUSE BRD MNT 4A 125VAC/VDC 2SMD 37 DISPLAYPORT-VIP-OUTPUT BOARD REV1 PCB 1 -- -- 305-PD-16-0XXX PACTRON -- (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 FPGA-EB-02015-1.0 DisplayPort VIP Output Board Evaluation Board User Guide Revision History Date Version March 2018 1.0 Change Summary Initial release. (c) 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB-02015-1.0 19 7th Floor, 111 SW 5th Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com