DisplayPort VIP Output Board
Evaluation Board User Guide
FPGA-EB-02015-1.0
March 2018
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02015-1.0
Contents
Acronyms in This Document ................................................................................................................................................. 3
1. Introduction .................................................................................................................................................................. 4
1.1. Further Information ................................................................................................................................................ 5
2. Functional Description .................................................................................................................................................. 6
2.1. Switches .................................................................................................................................................................. 6
2.2. DisplayPort Interface .............................................................................................................................................. 6
2.3. LVDS Translator ...................................................................................................................................................... 6
2.4. Clock Interface ........................................................................................................................................................ 6
3. High-Speed Headers ..................................................................................................................................................... 7
4. Power Supply ................................................................................................................................................................ 9
5. User LEDs and Headers ............................................................................................................................................... 10
6. Ordering Information .................................................................................................................................................. 11
References .......................................................................................................................................................................... 12
Technical Support Assistance ............................................................................................................................................. 12
Appendix A. DisplayPort VIP Output Board Schematics ..................................................................................................... 13
Appendix B. DisplayPort VIP Output Board Bill of Materials .............................................................................................. 16
Revision History ................................................................................................................................................................... 19
Figures
Figure 1.1. Top View of DisplayPort VIP Output Board......................................................................................................... 4
Figure 1.2. Bottom View of DisplayPort VIP Output Board .................................................................................................. 5
Figure 2.1 Functional Block Diagram .................................................................................................................................... 6
Figure 4.1 Power Supply ....................................................................................................................................................... 9
Figure A.1. Block Diagram ................................................................................................................................................... 13
Figure A.2. DP Redriver and Connector I/F ......................................................................................................................... 14
Figure A.3. Power, Debug LED, Header I/F ......................................................................................................................... 15
Tables
Table 3.1. Connector J1 ........................................................................................................................................................ 7
Table 3.2. Connector J2 ........................................................................................................................................................ 8
Table 5.1 User LEDs............................................................................................................................................................. 10
Table 6.1. Reference Part Number ..................................................................................................................................... 11
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 3
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
DP
DisplayPort
I2C
Inter-Integrated Circuit
LDO
Low Dropout
LED
Light-emitting Diode
LVDS
Low-Voltage Differential Signaling
mDP
Mini DisplayPort
VIP
Video Interface Platform
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02015-1.0
1. Introduction
This document describes the Lattice Semiconductor DisplayPort® VIP Output Board. This board is designed to work with
the Lattice Video Interface Platform (VIP) board interconnect system.
This user guide includes descriptions of board components, schematics, and bill of materials.
Key features of the DisplayPort VIP Output Board include:
Integrated Texas Instruments SN75DP130 DisplayPort 1:1 Redriver
Mini DisplayPort (mDP) connector
Two 60-pin Rugged High-Speed Headers
Figure 1.1 shows the top view of the DisplayPort VIP Output Board and its key components. Figure 1.2 shows the
bottom view of the board.
SN75DP130
Mini DisplayPort
Connector
SN65MLVD200
User LEDs
135 MHz Clock
3.3 V Power to mDP
Connector
(Not populated)
System Reset
User Header
Figure 1.1. Top View of DisplayPort VIP Output Board
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 5
Downstream Connector (J2)
Downstream Connector (J1)
Figure 1.2. Bottom View of DisplayPort VIP Output Board
1.1. Further Information
The following references provide detailed information on the DisplayPort VIP Output Board:
Appendix A. DisplayPort VIP Output Board Schematics
Appendix B. DisplayPort VIP Output Board Bill of Materials
For more information on boards and kits available for the VIP (Video Interface Platform) system visit
www.latticesemi.com/boards
For details on the Texas Instruments SN75DP130, visit the Texas Instruments website at www.ti.com
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02015-1.0
2. Functional Description
The DisplayPort VIP Output board receives up to 4-lanes of DisplayPort from the upstream processor board through
connector J1. The DisplayPort Main Link, Control and Aux Channel are sent through the TI DisplayPort re-driver, which
regenerates the DisplayPort high-speed digital link to the mini DisplayPort connector.
SN75DP130
U1
mDP
Connector
CN1
J1
DisplayPort Main Link
(4 lanes)
Aux Channel
HPD/CAD/Control
DisplayPort Main Link
(4 lanes)
Aux Channel
HPD/CAD/Control
Figure 2.1 Functional Block Diagram
2.1. Switches
The push button switch, SW1, controls the reset signal RESET. Pressing SW1 provides logic 0 to the SN75DP130 RSTN
pin. RESET is connected to GSRN on connecter J1, allowing SW1 to control the reset signal for other connected boards.
2.2. DisplayPort Interface
The mini DisplayPort connector, CN1, connects the DisplayPort VIP Output Board to a DisplayPort sink. If PWR Out is
required on Pin 20, the user must populate the 3.3 V Low Dropout (LDO) regulator, U4, and short jumper J4.
2.3. LVDS Translator
The SN65MLV200 LVDS Driver/Receiver, U2, can be used to translate the LVDS AUX Channel to single ended I/O. This
can be used if the upstream processor board is unable to receive LVDS. The single ended I/O are routed to connector
J2.
2.4. Clock Interface
The 135 MHz LVDS clock, U3, can be used as a reference clock for the upstream processor board. This clock is routed to
connector J1.
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 7
3. High-Speed Headers
The two 60-pin high-speed headers, connectors J1 and J2, are used to connect to an upstream host processor board.
Table 3.1. Connector J1
J1 Connector Pin
Signal Name
Description
1
GND
—
2
12V
—
3
CLK135_P
135 MHz LVDS Clock
4
12V
—
5
CLK135_N
135 MHz LVDS Clock
6
12V
—
7
GND
—
8
12V
—
9
AUX_P
DisplayPort Auxiliary Data Channel
11
AUX_N
DisplayPort Auxiliary Data Channel
13
GND
—
14
GND
—
19
GND
—
20
GND
—
26
GND
—
28
RESET
Global System Reset
30
HPD_SRC
Hot Plug Detect
32
CAD_SRC
DP Cable Adapter Detect
34
GND
—
36
TXP0_D0CH0
DisplayPort Main Link Lane 0
38
TXN0_D0CH0
DisplayPort Main Link Lane 0
40
GND
—
41
SCL_CTL
I2C Interface to SN75DP130
42
TXP0_D0CH1
DisplayPort Main Link Lane 1
43
SDA_CTL
I2C Interface to SN75DP130
44
TXN0_D0CH1
DisplayPort Main Link Lane 1
46
GND
—
48
TXP0_D1CH0
DisplayPort Main Link Lane 2
50
TXN0_D1CH0
DisplayPort Main Link Lane 2
52
GND
—
54
TXP0_D1CH1
DisplayPort Main Link Lane 3
55
GND
—
56
TXN0_D1CH1
DisplayPort Main Link Lane 3
58
GND
—
60
TP14
—
10, 12, 15, 16, 17, 18, 21, 22,
23, 24, 25, 27, 29, 31, 33, 35,
37, 39, 45, 47, 49, 51, 53, 57,
59
Not Connected
—
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02015-1.0
Table 3.2. Connector J2
J1 Connector Pin
Signal Name
SN75DP130 pin
Description
1
3.3V
—
—
2
3.3V
—
—
3
3.3V
—
—
4
3.3V
—
—
7
AUX_EN
—
Aux Channel Translator Enable
8
LED1
—
User LED
9
AUX_OUT
—
Aux Channel single ended Out
10
LED2
—
User LED
11
AUX_IN
—
Aux Channel single ended In
12
LED3
—
User LED
13
EN
EN
SN75DP130 Enable
14
LED4
—
User LED
20
GND
—
—
21
GND
—
—
30
SDA_DDC
SDA_DDC
I2C Display Data Channel
32
SCL_DDC
SCL_DDC
I2C Display Data Channel
39
GND
—
—
40
GND
—
—
44
HEADER1
—
User I/O Header J3
46
HEADER2
—
User I/O Header J3
48
HEADER3
—
User I/O Header J3
50
HEADER4
—
User I/O Header J3
52
HEADER5
—
User I/O Header J3
53
GND
—
—
55
GND
—
—
56
GND
—
—
57
2.5V
—
—
58
2.5V
—
—
59
2.5V
—
—
60
2.5V
—
—
5, 6, 15, 16, 17, 18, 19, 22, 23,
24, 25, 26, 27, 28, 29, 31, 33,
34, 35, 36, 37, 38, 41, 42, 43,
45, 47, 49, 51, 54
Not Connected
—
—
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 9
4. Power Supply
Board power is supplied through connectors J1 and J2. Figure 4.1 shows the power distribution scheme. To provide
power to the mini DisplayPort connector, install a 5.0 V to 3.3 V LDO at U4 and add shunt to jumper J4.
12 V from J1
3.3 V from J2
2.5 V from J2
Status
LED D7
Status
LED D5
Status
LED D6
LDO*
U4
mDP
Connector
CN1
3.3 V, 500 mA
* Not Installed
J4
Figure 4.1 Power Supply
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02015-1.0
5. User LEDs and Headers
Four discrete LEDs (light-emitting diodes) are available to the user. These are driven by the upstream processor board
through connector J2.
Table 5.1 User LEDs
Signal
LED #
Connector J2 Pin
Color
LED1
D1
8
Green
LED2
D2
10
Green
LED3
D3
12
Green
LED4
D4
14
Green
An 8-pin 100-mil header, J3, is available to the user. There are five user connections routed to the upstream connector
J2.
Table 5.2 User Header
Signal
Header J3 Pin
Connector J2 Pin
3V3
1
—
HEADER1
2
44
HEADER2
3
46
HEADER3
4
48
HEADER4
5
50
HEADER5
6
52
RESET
7
—
GND
8
—
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 11
6. Ordering Information
Please visit www.latticesemi.com/boards for the latest ordering information.
Table 6.1. Reference Part Number
Description
Ordering Part Number
DisplayPort VIP Output Board
DP-VIP-O-EVN
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02015-1.0
References
For more information, refer to
Lattice Embedded Vision Development Kit User Guide (FPGA-UG-02015)
ECP5 VIP Processing Board (FPGA-EB-02001)
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 13
Appendix A. DisplayPort VIP Output Board Schematics
Figure A.1. Block Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DisplayPort VIP Output Board
LED & Header I/F
SN75DP130 GPIO I/F
5V,3V3,2V5
Downstream Connector 1&2
I2C
X4 DP Data
DP AUX I/F
Control GPIO
OnBoard LDO
(pg4)
(pg4)
(pg3&4)
Mini DP Connector
X4 DP Data
(pg3)
(pg3)
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
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Friday, 11-Nov-16
B0.1
42
Title & Index
DisplayPort VIP Output Board A
Date:
Size Schematic Rev
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Title
Lattice Semiconductor Applications
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Board Rev
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B0.1
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Title & Index
DisplayPort VIP Output Board A
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
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B0.1
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Title & Index
DisplayPort VIP Output Board A
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02015-1.0
Figure A.2. DP Redriver and Connector I/F
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLACE DE-CAPS CLOSE TO THEIR POWER PINS
3V3_TX
DP_3V3
2V53V3
3V3
3V3_TX
3V3
3V3
3V3
12V
3V3_TX
3V3
AUX_IN{4}
SDA_DDC {4}
SCL_DDC {4}
AUX_OUT{4}
EN {4}
AUX_EN {4}
RESET {3,4}
RESET {3,4}
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Friday, 11-Nov-16
B0.1
43
DP Redriver & Connector I/F
DisplayPort VIP Output Board A
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
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Board Rev
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Friday, 11-Nov-16
B0.1
43
DP Redriver & Connector I/F
DisplayPort VIP Output Board A
Date:
Size Schematic Rev
ofSheet
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Lattice Semiconductor Applications
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Board Rev
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DP Redriver & Connector I/F
DisplayPort VIP Output Board A
C33
100nF
C10 100nF
R2
4.7k
C12 100nFC11 100nF
C22
100nF
R4
4.7k
C27
0.1uF
R3
4.7k
R130
C13 100nF
R40
100K
R60 R70
R17
2.49K
C31
100nF
E-PAD(GND)
U1
SN75DP130SS
VCC 1
VDDD_DREG 2
ADDR_EQ 3
SCL_CTL 4
SDA_CTL 5
VCC 6
NC1
7
CAD_SRC
8
HPD_SRC
9
VCC 12
NC2
15
GND
18
NC3
21
GND
24
VCC 25
EN 26
AUX_SRCn
29 AUX_SRCp
30
GND
31 VCC 32
SCL_DDC
33 SDA_DDC
34
RSTn 35
VCC 36
NC7
37
IN0p
38
IN0n
39
NC6
40
IN1p
41
IN1n
42
NC5
43
IN2p
44
IN2n
45
NC4
46
IN3p
47
IN3n
48
OUT0p 23
OUT0n 22
OUT1p 20
OUT1n 19
OUT2p 17
OUT2n 16
OUT3p 14
OUT3n 13
CAD_SINK 10
HPD_SINK 11
AUX_SINKp 28
AUX_SINKn 27
R120
R50
C29
1uF
R28 4.7k
R270
C16 100nF
U2
SN65MLVD200
4D
1R7
B
6
A
3
DE
8
VCC
5GND
RE#
2
C28
10uF
U3
DSC1103CE2-135.0000
EN
1
NC
2GND 3
OUT_P 4
OUT_N 5
VDD
6
E-PAD
7
R18
51E
CN1
Mini-DP
DPPOWER
20
GND3
19
AUX_CHN
18
ML_LANE1P
9
AUX_CHP
16
ML_LANE1N
11
GND2
14 GND1
13
ML_LANE0P
3
ML_LANE2P
15
ML_LANE0N
5
ML_LANE2N
17
GND5
8GND4
7
CONFIG2
6
ML_LANE3P
10
CONFIG1
4
ML_LANE3N
12
HPD
2
GND6
1
C19
1uF
J1
ERM5-030-05.0-L-DV-K-TR
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
C7 100nF
R190
C35
100nF
C8 100nF
C18 0.1uF
C25 0.1uF
L4
60ohms 2.3A 12
C26
0.1uF
C3 100nF
R260 DNI
C2 100nF
C24
1uF
C34
100nF
C4 100nF
C17 1uF
R150
C9 100nFC6 100nF
R1
4.7k
C23
100nF
TP14
1
C21
0.1uF
R110
R80 R90
C30
100nF
C15 100nF C14 100nF
R100
C32
100nF
R390
R23
51E
R21
1M
R41
100K
C20
10uF
C5 100nF
C1 100nF
R20
100K
R22
1.5K
TXP0_D0CH0
TXN0_D0CH0
TXP0_D0CH1
TXN0_D0CH1
TXP0_D1CH0
TXN0_D1CH0
TXP0_D1CH1
TXN0_D1CH1
HPD_SINK
RST_N
SCL_CTL
SDA_CTL
CAD_SINK
HPD_SINK
CLK135_N
CLK135_P
AUX_P
AUX_N
AUX_P
AUX_N
SCL_CTL
SDA_CTL
SDA_DDC
SCL_DDC
SDA_DDC
SCL_DDC
CAD_SRC
HPD_SRC CAD_SINK
TXP0_D0CH0
TXN0_D0CH0
TXP0_D0CH1
TXN0_D0CH1
TXP0_D1CH0
TXN0_D1CH0
TXP0_D1CH1
TXN0_D1CH1
SCL_CTL
SDA_CTL
CLK135_N
CLK135_P
AUX_N
AUX_P
HPD_SRC
CAD_SRC
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 15
Figure A.3. Power, Debug LED, Header I/F
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOTE : PLACE SWITCH IN THE TOP SIDE
EXTERNAL RESET
700mA traces 700mA traces
3V3
3V33V33V33V3
12V 3V3 12V
2V5
3V3
12V
REG_3V3 DP3V3
EXT_2V5
EXT_3V3
EXT_3V3
EXT_2V5 2V5
3V3
DP_3V3
RESET {3}
AUX_IN{3}
AUX_EN{3} AUX_OUT{3}
EN{3}
SDA_DDC {3}
SCL_DDC {3}
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
Project
Friday, 11-Nov-16
B0.1
44
Power,Debug LED,Header I/F
DisplayPort VIP Output Board A
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: techsupport@Latticesemi.com
Board Rev
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Friday, 11-Nov-16
B0.1
44
Power,Debug LED,Header I/F
DisplayPort VIP Output Board A
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
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44
Power,Debug LED,Header I/F
DisplayPort VIP Output Board A
L6
60ohms 2.3A 12
J4
Jumper
1 2
SW1
SYS_RST
12 34
R32
330E
D8
D1213A-01WS-7
C40
0.1uF
D4
Green
12
R31
330E
L2
60ohms 500mA
12
C39
0.1uF
C37
0.1uF
D6
Green
12
D3
Green
12
TP13
1
Q1
MMBT2222A
32
1
J2
ERM5-030-05.0-L-DV-K-TR
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59 1K
R37
L8
60ohms 2.3A 12
D2
Green
12
U16
FUSE
1
122
R35
1K
R29
4.7k
R34
330E
D1
Green
12
C38
10uF
R36
330E
D5
Green
12
D7
Green
12
J3
8 HEADER
1
2
3
4
5
6
7
8
R33
330E
C36
10uF
R38 10K
U4 LT1086CM-3.3
DNI
Vin
3
GND
1TAB 4
Vout 2
RESET
LED1
LED2
LED3
LED4
HEADER1
HEADER2
HEADER3
HEADER4
HEADER5
RESET
LED1
LED2
LED3
LED4
HEADER1
HEADER3
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DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02015-1.0
Appendix B. DisplayPort VIP Output Board Bill of Materials
Item
Reference
Qty
Value
Comments
Part Number
Manufacturer
Description
1
CN1
1
Mini-DP
—
2129320-3
TE Connectivity
MINI DISPLAYPORT REVERSE OFFSET
2
C1,C2,C3,C4,C5,C6,C7,C8,
C9,C10,C11,C12,C13,C14,
C15,C16
16
100 nF
—
885012205018
Wurth
CAP CER 0.1UF 10V X7R 0402
3
C17,C19,C24,C29
4
1 uF
—
GRM155R61A105KE15
D
Murata
CAP CER 1uf 10V 10% X5R 0402
4
C18,C21,C25,C26,C27
5
0.1 uF
—
GRM155R61A104KA01
D
Murata
CAP CER 0.1UF 10V X5R 0402
5
C20,C28
2
10 uF
—
GRM21BR61A106KE19L
Murata
CAP CER 10UF 10V X5R 0805
6
C22,C23,C30,C31,C32,C33,
C34,C35
8
100 nF
—
GRM155R61A104KA01
D
Murata
CAP CER 0.1UF 10V X5R 0402
7
C36,C38
2
10 uF
—
C1608X5R1E106M080A
C
TDK Corporation
CAP CER 10UF 25V X5R 0603
8
C37,C39
2
0.1 uF
—
CL05A104KA5NNNC
Samsung
CAP CER 0.1UF 25V X5R 0402
9
C40
1
0.1 uF
—
885012205037
Wurth
CAP CER 0.1UF 16V X7R 0402
10
D1,D2,D3,D4,D5,D6,D7
7
Green
—
LTST-C190KGKT
LITE-On INC
LED SUPER GREEN CLEAR 0603 SMD
11
D8
1
D1213A-01WS-7
—
D1213A-01WS-7
Diodes
Incorporated
TVS DIODE 3.3VWM 10VC SOD323
12
J1,J2
2
ERM5-030-05.0-L-
DV-K-TR
—
ERM5-030-050-L-DV-K-
TR
Samtec Inc
Conn High Speed Edge Rate Terminal
Strip HDR 60 POS 0.5mm Solder ST SMD
T/R -
13
J3
1
8 HEADER
—
—
—
General purpose 100 Mils header
14
J4
1
Jumper
—
—
—
General purpose 100 mils 1x2 Header
15
L2
1
60 Ω 500 mA
—
MMZ1608Y600BTA00
TDK
FERRITE BEAD 60 OHM 0603 1LN
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 17
Item
Reference
Qty
Value
Comments
Part Number
Manufacturer
Description
16
L4,L6,L8
3
60 Ω 2.3 A
—
MPZ1608Y600BTA00
TDK
FERRITE BEAD 60 OHM 0603 1LN
17
Q1
1
MMBT2222A
—
MMBT2222A,215
NXP
Semiconductor
TRANS NPN 40V 0.6A SOT23
18
R1,R2,R3,R4,R28,R29
6
4.7 k
—
CRCW06034K70FKEA
Vishay
RES SMD 4.7K OHM 1% 1/10W 0603
19
R5,R6,R7,R8,R9,R10,R11,
R12,R13,R15,R19,R27,R39
13
0
—
RC0603JR-070RL
Yageo
RES SMD 0.0OHM JUMPER 1/10W 0603
20
R26
1
0
DNL
RC0603JR-070RL
Yageo
RES SMD 0.0OHM JUMPER 1/10W 0603
21
R17
1
2.49 K
—
ERA-2AEB2491X
Panasonic
RES SMD 2.49KOHM 0.1% 1/16W 0402
22
R18,R23
2
51E
—
ERJ-2GEJ510X
Panasonic
RES SMD 51 OHM 5% 1/10W 0402
23
R20,R40,R41
3
100 K
—
ERA-2AEB104X
Panasonic
RES SMD 100K OHM 0.1% 1/16W 0402
24
R21
1
1 M
—
ERJ-2GEJ105X
Panasonic
RES SMD 1M OHM 5% 1/10W 0402
25
R22
1
1.5 K
—
ERJ-2RKF1501X
Panasonic
RES SMD 1.5K OHM 1% 1/10W 0402
26
R31,R32,R33,R34,R36
5
330E
—
CRCW0402330RFKED
Vishay Dale
RES SMD 330 OHM 1% 1/16W 0402
27
R35
1
1 K
—
RC0603FR-071KL
Yageo
RES SMD 1K OHM 1% 1/10W 0603
28
R37
1
1 K
—
RMCF0402JT1K00
Stackpole
Electronics Inc
RES SMD 1K OHM 5% 1/16W 0402
29
R38
1
10 K
—
ERJ-3EKF1002V
Panasonic
RES SMD 10K OHM 1% 1/10W 0603
30
SW1
1
SYS_RST
—
434153017835
Wurth
SWITCH TACTILE SPST-NO 0.05A 12V
31
TP13,TP14
2
TEST POINT
—
22-28-4020
Molex
Test Point 0.1"
32
U1
1
SN75DP130SS
—
SN75DP130SSRGZR
Texas Instruments
IC DISPLYPRT 1:1 REDRIVR 48VQFN
33
U2
1
SN65MLVD200
—
SN65MLVD200AD
Texas Instruments
IC LVDS LINE DVR/RCVR 8-SOIC
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02015-1.0
Item
Reference
Qty
Value
Comments
Part Number
Manufacturer
Description
34
U3
1
DSC1103CE2-
135.0000
—
DSC1103CE2-135.0000
Microchip
Technology Inc
Standard Clock Oscillators -20C - 70C 25
ppm 135.0000MHz
35
U4
1
LT1086CM-3.3
DNI
LT1086CM-3.3#TRPBF
Linear Tech
IC REG LDO 3.3V 1.5A D2PAK
36
U16
1
FUSE
—
0154004.DRT
Littelfuse Inc.
FUSE BRD MNT 4A 125VAC/VDC 2SMD
37
DISPLAYPORT-VIP-OUTPUT
BOARD REV1 PCB
1
—
—
305-PD-16-0XXX
PACTRON
—
DisplayPort VIP Output Board
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02015-1.0 19
Revision History
Date
Version
Change Summary
March 2018
1.0
Initial release.
7th Floor, 111 SW 5th Avenue
Portland, OR 97204, USA
T 503.268.8000
www.latticesemi.com