PTN3393 2-lane DisplayPort to VGA adapter test IC Rev. 2 -- 27 July 2012 Objective product brief 1. General description The PTN3393 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort source to a VGA sink. The PTN3393 integrates a DisplayPort receiver and a high-speed triple video digital-to-analog converter that supports display resolutions from VGA to WUXGA. The PTN3393 supports either one or two DisplayPort v1.1a lanes operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3393 supports `Flash-over-AUX' capability enabling simple firmware upgradability in the field. The PTN3393 supports I2C-bus over AUX per DisplayPort v1.1a specification, and bridges the VESA DDC channel to the DisplayPort Interface. The PTN3393 is designed for single supply and minimizes application costs. It can be powered directly from the DisplayPort source side 3.3 V supply without a need for additional core voltage regulator. The VGA output is powered down when there is no valid DisplayPort source data being transmitted. The PTN3393 also aids in monitor detection by performing load sensing and reporting sink connection status to the source. 2. Functional diagram PTN3393 DIFF CDR, RCV S2P 10b/8b lane 1 DE-SCRAM Vbias ISOCHRONOUS LINK TIME CONV. VIDEO DAC SUBSYSTEM R[7:0] DAC G[7:0] MAIN STREAM B[7:0] TIMING RECOVERY DPCD REGISTERS DAC DAC MONITOR PRESENCE DETECT INTERFACE DE-SKEWING DIFF CDR, RCV S2P 10b/8b lane 0 RX PHY DIGITAL DE-SCRAM RX PHY ANALOG SUBSYSTEM R VGA OUTPUT G B H, V sync HSYNC VSYNC CONTROL FLASH MCU Vbias RCV AUX MANCHESTER CODEC AUX COMMAND LEVEL MODULE I2C-BUS MASTER SCL SDA DRV RX ACLI Vbias RX DIGITAL SUBSYSTEM 002aah229 Fig 1. Functional diagram of PTN3393 PTN3393 NXP Semiconductors 2-lane DisplayPort to VGA adapter test IC 3. Pinning information 31 RED 32 n.c. 33 OSC_IN 34 OSC_OUT 35 LDOCAP_DIG 36 VDDD33_CORE 37 S0 38 S1 40 S3 terminal 1 index area 39 S2 3.1 Pinning VDDA22_AUX 1 30 RSET LDOCPA_AUX 2 29 n.c. AUX_P 3 28 GRN AUX_N 4 RRX 5 ML0_P 6 ML0_N 7 24 VSYNC n.c. 8 23 n.c. ML1_P 9 22 SDA 27 VDDA33_DAC 26 BLU PTN3393BS 25 HSYNC SCL 20 TDI 19 TRST 18 TMS 17 TDO 16 TCK 15 VDDA33_DP 14 HPD 13 CLK_O 12 21 VDDD33_IO RESET 11 ML1_N 10 002aah226 Transparent top view Fig 2. Pin configuration for HVQFN40 3.2 Pin description Table 1. Pin description Symbol Pin Type Description VDDD33_CORE 36 power Digital core 3.3 V supply voltage VDDA33_AUX 1 power Analog AUX, bias and PLL 3.3 V supply voltage VDDA33_DP 14 power Analog 3.3 V supply for DisplayPort receiver module VDDD33_IO 21 power I/O 3.3 V supply voltage VDDA33_DAC 27 power Analog 3.3 V supply for DAC LDOCAP_AUX 2 power 1.8 V AUX supply decoupling LDOCAP_DIG 35 power 1.8 V digital core supply decoupling ML0_P 6 self-biasing differential input DisplayPort main lane signal lane 0, positive ML0_N 7 self-biasing differential input DisplayPort main lane signal lane 0, negative ML1_P 9 self-biasing differential input DisplayPort main lane signal lane 1, positive ML1_N 10 self-biasing differential input DisplayPort main lane signal lane 1, negative AUX_P 3 self-biasing differential DisplayPort auxiliary channel signal, positive input/output AUX_N 4 self-biasing differential DisplayPort auxiliary channel signal, negative input/output Power DisplayPort PTN3393 Objective product brief All information provided in this document is subject to legal disclaimers. Rev. 2 -- 27 July 2012 (c) NXP B.V. 2012. All rights reserved. 2 of 5 PTN3393 NXP Semiconductors 2-lane DisplayPort to VGA adapter test IC Table 1. Pin description ...continued Symbol Pin Type Description HPD 13 3.3 V TTL single-ended output Hot Plug Detect RGB DAC outputs BLU 26 analog output `blue' current analog output GRN 28 analog output `green' current analog output RED 31 analog output `red' current analog output RSET 30 analog input/output DAC full-scale current control resistor. Pull down to ground by an external 1.2 k 1 % resistor. SCL 20 single-ended 5 V open-drain DDC I/O 5 V sink-side DDC clock I/O. Pulled up by external resistor to 5 V. SDA 22 single-ended 5 V open-drain DDC I/O 5 V sink-side DDC data I/O. Pulled up by external resistor to 5 V. DDC Monitor-side sync HSYNC 25 single-ended 3.3 V TTL output horizontal sync signal to monitor VSYNC 24 single-ended 3.3 V TTL output vertical sync signal to monitor TCK 15 input JTAG clock input TDO 16 output JTAG data output TMS 17 input JTAG mode select input TRST 18 input JTAG reset (active LOW) input TDI 19 input JTAG data input 37 input Open (internal pull-down) = logic 0 Implement VGA-side monitor detect according to VESA DisplayPort Standard v1.1a, sections 7 and 8. JTAG Miscellaneous S0 HIGH (external pull-up) = logic 1 Set HPD HIGH upon VGA monitor detection; set HPD LOW upon VGA monitor detachment. S1 38 input reserved; leave open-circuit (default internal pull-down) S2 39 input Open (internal pull-down) = logic 0 to set default I2C-bus speed to 50 kbit/s. HIGH (external pull-up) = logic 1, to set default I2C-bus speed to 10 kbit/s. This pin may be left open-circuit (internal pull-down) or tied to VDD according to the desired default I2C-bus speed. See more explanation about S2 pin setting and DPCD register 00109h. S3 40 input reserved; leave open-circuit (default internal pull-down) RESET 11 input Hardware reset input (active LOW); internal pull-up. A capacitor must be connected between this pin and ground. A 1 F capacitor is recommended. CLK_O 12 output DisplayPort receiver test clock output OSC_IN 33 input crystal oscillator input PTN3393 Objective product brief All information provided in this document is subject to legal disclaimers. Rev. 2 -- 27 July 2012 (c) NXP B.V. 2012. All rights reserved. 3 of 5 PTN3393 NXP Semiconductors 2-lane DisplayPort to VGA adapter test IC Table 1. Pin description ...continued Symbol Pin Type Description OSC_OUT 34 output crystal oscillator output RRX 5 input Receiver termination resistance control. A 12 k resistor must be connected between this pin and LDOCAP_AUX (pin 2). n.c. 8, 23, 29, 32 not connected 4. Display resolution Table 2 lists some example display resolutions and clock rates that PTN3393 supports. Table 2. Display type Display resolution and pixel clock rate Active video Horizontal Total frame Vertical Horizontal Vertical Bits per pixel Frame rate (Hz) Pixel clock (MHz) Data rate (Gbit/s) VGA 640 480 800 525 24 59.94 25.175 0.8 SVGA 800 600 1056 628 24 60.32 40.002 1.2 XGA 1024 768 1344 806 24 60 64.996 1.9 XGA+ 1152 864 1520 806 24 60 81.806 2.45 WXGA 1280 768 1664 897 24 60 79.672 2.39 WXGA+ 1400 900 1848 934 24 60 103.562 3.11 XGA+ 1152 864 1520 806 24 60 81.806 2.45 1366 768 1792 798 24 60 85.801 2.57 SXGA 1280 1024 1688 1066 24 60.02 108.000 3.2 SXGA 1280 1024 1728 1072 24 85 157.455 4.72 SXGA+ 1400 1050 1864 1089 24 60 121.794 3.65 1600 900 2112 934 24 60 118.356 3.55 WSXGA+ 1680 1050 2240 1089 24 60 146.362 4.39 UXGA 1600 1200 2160 1250 24 60 162.000 3.9 UXGA 1600 1200 1760 1243 24 75 164.076 4.92 UXGA 1600 1200 2160 1250 18 85 229.500 5.16 FHD 1920 1080 2200 1125 24 60 148.500 4.46 WUXGA 1920 1200 2592 1245 18 59.885 193.251 4.35 WUXGA 1920 1200 2080 1235 24 59.95 154.000 4.62 QXGA 2048 1536 2144 1555 24 49.266 164.249 4.9 QWXGA 2048 1152 2720 1188 24 49.979 161.500 4.84 QWXGA 2048 1152 2208 1185 24 59.909 156.751 4.7 The available bandwidth over a 2-lane HBR DisplayPort 1.1a link limits pixel clock rate support to: * 240 MHz at 6 bpc * 180 MHz at 8 bpc PTN3393 Objective product brief All information provided in this document is subject to legal disclaimers. Rev. 2 -- 27 July 2012 (c) NXP B.V. 2012. All rights reserved. 4 of 5 PTN3393 NXP Semiconductors 2-lane DisplayPort to VGA adapter test IC 5. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-1 terminal 1 index area A E A1 c detail X C e1 e 1/2 e v M C A B w M C b 11 20 y y1 C L 21 10 e e2 Eh 1/2 1 e 30 terminal 1 index area 40 31 Dh X 0 2.5 scale DIMENSIONS (mm are the original dimensions) A(1) UNIT max. mm 1 A1 b 0.05 0.00 0.30 0.18 5 mm c D(1) Dh E(1) Eh 0.2 6.1 5.9 4.25 3.95 6.1 5.9 4.25 3.95 e e1 4.5 0.5 e2 L v w y y1 4.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Fig 3. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT618-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Package outline SOT618-1 (HVQFN40) (c) NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 July 2012 Document identifier: PTN3393 PTN3393 Objective product brief All information provided in this document is subject to legal disclaimers. Rev. 2 -- 27 July 2012 (c) NXP B.V. 2012. All rights reserved. 5 of 5 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: PTN3393BSY PTN3393BS/F1Y