SPT9713
12-BIT, 100 MWPS TTL D/A CONVER TER
TECHNICAL DATA
FEBRUARY 15, 2001
APPLICATIONS
• Fast frequency hopping spread spectrum radios
• Direct sequence spread spectrum radios
• Microwave and satellite modems
• Test & measurement instr umentation
FEATURES
• 12-Bit, 100 MWPS digital-to-analog converter
• TTL compatibility
• Low power : 640 mW
• 1/2 LSB DNL
• 40 MHz multiplying bandwidth
• Industrial temperature range
• Superior performance over AD9713
– Improved settling time of 13 ns
– Improved glitch energy 15 pV-s
– Master-slave latches
GENERAL DESCRIPTION
The SPT9713 is a 12-bit, 100 MWPS digital-to-analog
conver ter designed for direct digital synthesis, high reso-
lution imaging, and arbitrary waveform generation applica-
tions.
This de vice is pin-for-pin compatib le with the AD9713 with
significantly improved performance. The only difference
between the SPT9713 and the AD9713 is that the Latch
Enable (LE, pin 26) for the SPT9713 is rising-edge trig-
gered (see figure 1), whereas the Latch Enable (LE, pin
26) for the AD9713 functions in the transparent mode.
The SPT9713 is a TTL-compatible device. It features a
f ast settling time of 13 ns and lo w glitch impulse energy of
15 pV- s, which results in excellent spur ious-free dynamic
range characteristics.
The SPT9713 is available in a 28-lead PLCC package in
the industrial temperature range (–40 to +85 °C).
BLOCK DIAGRAM
(MSB)
Latch Enable
Digital
Inputs
D1
through
D12
Ref In
IOut
IOut
Decoders
and
Drivers
Latches
(LSB)
RSet
Control Amp In
Control
Amp Out
Internal
Voltage
Reference
Ref Out
Switch
Network
Control
Amp
+
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SPT9713
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
Supply Voltages
Positive Supply Voltage (VCC)................................+7 V
Negative Supply Voltage (VEE) .............................. –7 V
A/D Ground Voltage Differential ........................... 0.5 V
Input Voltages
Digital Input Voltage
(D1–D12, Latch Enable)...............................0 V to VCC
Control Amp Input Voltage Range ...............0 V to –4 V
Reference Input Voltage Range (VREF) ........ 0 V to VEE
Output Currents
Internal Reference Output Current.................... 500 µA
Control Amplifier Output Current.....................±2.5 mA
Temperature
Operating Temperature .......................... –40 to +85 °C
Junction Temperature...................................... +150 °C
Lead, Soldering (10 seconds) ......................... +300 °C
Storage ................................................ –65 to +150 °C
ELECTRICAL SPECIFICATIONS
TA = TMIN – TMAX, VCC = +5.0 V, VEE = –5.2 V, RSet = 7.5 kΩ, Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified.
TEST TEST SPT9713A SPT9713B
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
DC Performance
Resolution 12 12 Bits
Differential Linearity I ±0.5 ±0.75 ±1.0 ±1.25 LSB
Differential Linearity Max at Full Temp. VI ±1.5 ±2.0 LSB
Integral Linearity Best Fit I ±0.75 ±1.0 ±1.0 ±1.5 LSB
Integral Linearity Max at Full Temp. VI ±1.75 ±2.0 LSB
Output Capacitance +25 °C V 10 10 pF
Gain Error1+25 °C I 1.0 5. 0 1.0 5.0 % FS
Full Temp. VI 8.0 8.0 % FS
Gain Error Tempco Full Temp. V 150 150 PPM/°C
Zero-Scale Offset Error +25 °C I 0.5 2.5 0.5 2.5 µA
Full Temp. VI 5.0 5. 0 µA
Offset Drift Coefficient Full Temp. V 0.01 0.01 µA/°C
Output Compliance Voltage +25 °C IV –1.2 +2.0 –1.2 +2.0 V
Equivalent Output Resistance +25 °C IV 0.8 1.0 1.2 0.8 1.0 1.2 kΩ
Dynamic Performance
Conversion Rate +25 °C IV 100 100 MWPS
Settling Time tST2+25 °C V 13 13 n s
Output Propagation Delay tD3+25 °C V 2 2 ns
Glitch Energy4+25 °C V 1 5 15 pV-s
Full Scale Output Current5+25 °C V 20.48 20.48 mA
Spurious-Free Dynamic Range6+25 °C
1.23 MHz; 10 MWPS 2 MHz Span V 7 0 70 dBc
5.055 MHz; 20 MWPS 2 MHz Span V 6 8 68 dBc
10.1 MHz; 50 MWPS 2 MHz Span V 6 8 68 dBc
16 MHz; 40 MWPS 10 MHz Span V 6 8 68 d Bc
Rise Time / Fall Time RL = 50 ΩV2 2ns
1Gain is measured as a ratio of the full-scale current to ISet. The r atio is nominally 128.
2Measured as voltage at mid-scale transition to ±0.024%; RL=50 Ω.
3Measured from the rising edge of Latch Enable to where the output signal has left a 1 LSB error band.
4Glitch is measured as the largest single transient.
5Calculated using IFS = 128 x (Control Amp In / RSet)
6SFDR is defined as the difference in signal energy betw een the fundamental and worst case spurious frequencies in the output spectrum window ,
which is centered at the fundamental frequency and covers the indicated span.
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SPT9713
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any b lank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL TEST PROCEDURE
I 100% production tested at the specified temperature.
I I 100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
II I QA sample tested only at the specified temperatures.
IV Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V Parameter is a typical value for information pur poses only.
VI 100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
ELECTRICAL SPECIFICATIONS
TA = TMIN – TMAX, VCC = +5.0 V, VEE = –5.2 V, RSET = 7.5 kΩ, Control Amp In = Ref Out, VOUT = 0 V, unless otherwise specified.
TEST TEST SPT9713A SPT9713B
PARAMETERS CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS
Power Supply Requirements
Positive Supply Voltage IV 4.75 5.0 +5.25 4.75 5.0 +5.25 V
Negative Supply Voltage IV –5.4 6 –5.2 –4.94 –5.46 –5.2 –4.94 V
Positive Supply Current (+5.0 V) +25 °C I 8 14 8 14 mA
Full Temp. VI 16 16 mA
Negative Supply Current (–5.2 V) +25 °C I 115 140 115 140 mA
Full Temp VI 148 148 mA
Nominal Power Dissipation V 6 40 640 m W
Power Supply Rejection Ratio ±5% of VEE and VCC I 30 100 30 100 µA/V
External Ref, +25 °C
Voltag e Input and Control
Reference Input Impedance +25 °C V 3 3 kΩ
Ref. Multiplying Bandwidth +25 °C V 40 40 M Hz
Internal Reference Voltage VI –1.15 –1.20 –1.25 –1.15 –1.20 –1.25 V
Internal Reference Voltage Drift Full V 50 50 ppm/°C
Amplifier Input Impedance +25 °C V 3 3 MΩ
Amplifier Input Bandwidth +25 °C V 1 1 MHz
Digital Inputs
Logic 1 Voltage Full Temp. VI 2.0 2.0 V
Logic 0 Voltage Full Temp. VI 0.8 0. 8 V
Logic 1 Current Full Temp. V I 20 20 µA
Logic 0 Current Full Temp. V I 600 600 µA
Input Capacitance +25 °C V 3 3 pF
Input Setup Time – tS+25 °C IV 3 2 3 2 ns
Input Setup Time – tSFull Temp. IV 3.5 3. 5 ns
Input Hold Time – tH+25 °C IV 0.5 0 0. 5 0 n s
Input Hold Time – tHFull Temp. I V 0. 5 0.5 ns
Latch Pulse Width – tPWL, tPWH +25 °C IV 5. 0 4.0 5.0 4. 0 ns
42/15/01
SPT9713
THEORY OF OPERATION
The SPT9713 uses a segmented architecture incorporat-
ing most significant bit (MSB) decoding. The four MSBs
(D1–D4) are decoded to thermometer code lines to dr ive
15 discrete current sinks. For the eight least significant
bits (LSBs), D5 and D6 are binary weighted and D7–D12
are applied to the R-2R network. The 12-bit decoded data
is input to inter nal master/slave latches. The latched data
is input to the switching networ k and is presented on the
output pins as complementary current outputs.
TYPICAL INTERFACE CIRCUIT
The SPT9713 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
SPT9713 in normal circuit operation. The following sec-
tions provide descriptions of the pin functions and outline
critical performance criteria to consider f or achie ving opti-
mal device performance.
POWER SUPPLIES AND GROUNDING
The SPT9713 requires the use of +5 V and –5.2 V sup-
plies. All supplies should be treated as analog supply
sources. This means the ground returns of the device
should be connected to the analog ground plane. All sup-
ply pins should be bypassed with .01 µF and 10 µF
decoupling capacitors as close to the device as possible.
The two grounds available on the SPT9713 are DGND
and AGND. These grounds are not tied together internal to
the device. The use of ground planes is recommended to
achie ve the best perf ormance of the SPT9713. All ground,
reference and analog output pins should be tied directly to
the DAC ground plane. The DAC and system ground
planes should be separate from each other and only con-
nected at a single point through a ferrite bead to reduce
ground noise pic kup.
DIGITAL INPUTS AND TIMING
The SPT9713 uses TTL logic drivers for each data input
D1–D12 and Latch Enable. It also employs master/slave
latches to simplify digital interface timing requirements
and reduce glitch energy by synchronizing the current
s witches. This is an impro v ement over the AD9713, which
typically requires external latches for digital input synchro-
nization.
Referring to figure 1, data is latched into the DAC on the
rising edge of the latch enable clock with the associated
setup and hold times. The output transition occurs after a
typical 2 ns propagation delay and settles to within ±1 LSB
in typically 13 ns. Because of the SPT9713’s rising-edge
triggering, no timing changes are required when replacing
an AD9713 operating in the transparent mode.
VOLTA GE REFERENCE
When using the internal reference, Ref Out should be con-
nected to Control Amp In and decoupled with a 0.1 µF
capacitor . Control Amp Out should be connected to Ref In
and decoupled to the analog supply. (See figure 2.)
Full-scale output current is determined by Control Amp In
and RSet using the following formula:
IOut (FS) = (Control Amp In / RSet) x 128
(Current Out is a constant 128 factor of the
reference current)
The internal reference is typically –1.20 V with a tolerance
of ±0.05 V and a typical drift of 50 ppm/°C. If greater accu-
racy or temperature stability is required, an e xternal refer-
ence can be utilized.
OUTPUTS
The output of the SPT9713 is comprised of complemen-
tar y current sinks, IOut and IOut. The output current levels
at either IOut or IOut are based upon the digital input code.
The sum of the two is always equal to the full-scale output
current minus one LSB.
By terminating the output current through a resistive load
to ground, an associated voltage develops. The effective
resistive load (REff) is the output resistance of the device
(ROut) in parallel with the resistive load (RL). The voltage
which develops can be determined using the following
formulas:
Control Amp Out = –1.2 V, and R Set = 7.5 kΩ
IOut (FS) = (–1.2 V / 7.5 kΩ) x 128 = –20.48 mA
RL = 51 Ω
ROut = 1.0 kΩ
REff = 51 Ω || 1.0 kΩ = 48.52 Ω
VOut = REff x IOut (FS) = 48.52 Ω x –20.48 mA
= –0.994 V
The resistive load of the SPT9713 can be modified to in-
corporate a wide variety of signal lev els. Howe v er , optimal
device performance is achieved when the outputs are
equivalently loaded.
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SPT9713
Figure 1 – Timing Diagram
Latch
Enable
t
PWL
t
H
t
S
t
PWH
OUT+
OUT
1/2 LSB
t
ST
1 LSB
t
D
Data Inputs
15,2512,21
0.1 µF
0.1 µF
0.001 µF
0.001 µF
+5 V
23
0.1 µF
0.01 µF
AV
EE
R
L
R
L
14
16
I
Out
I
Out
R
Set
24
R
Set
19
20
Control
Amp In
Ref Out
Control
Amp Out
18
17
20 W
Ref In
D1 (MSB)
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12 (LSB)
LE
28
1
2
3
4
5
6
7
8
9
10
11
26
DGND AGND Ref GND
System
GND
TTL Logic Drivers
0.1 µF
5.2 V
V
Out
Digital Inputs
Clock
Input
SPT9713
27 13 22
DV
EE
DV
CC
10 µF
10 µF
0.1 µF
Figure 2 – Typical Interface Circuit
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SPT9713
PACKAGE OUTLINE
28-Lead PLCC
A
B
Pin 1
C
D
E
F
G
H
TOP
VIEW
Pin 1
BOTTOM
VIEW
I
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A 0.452 0.456 11.48 11.58
B 0.485 0.495 12.32 12.57
C 30° 30°
D 0.170 0.179 4.32 4.55
E 0.020 0.025 0.51 0.64
F 0.031 0.035 0.79 0.89
G 0.013 0.021 0.33 0.53
H 0.048 0.052 1.22 1.32
I 0.410 0.430 10.41 10.92
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SPT9713
ORDERING INFORMATION
PART NUMBER DNL/INL TEMPERATURE RANGE PACKAGE
SPT9713AIP ±0.75/±1.0 –40 to +85 °C 28L PLCC
SPT9713BIP ±1.25/±1.5 –40 to +85 °C 28L PLCC
PIN ASSIGNMENTS PIN FUNCTIONS
Name Function
Out+ Analog Current Output
Out– Complementary Analog Current Output
D1–D12 Digital Input Bits (D12 is the LSB)
Latch Enable Latch Control Line
Ref In Voltage Reference Input
Ref Out Internal Voltage Reference Output
Normally Connected to Control Amp In
Ref GND Ground Return For Inter nal Voltage
Reference and Amplifier
Control Amp In Normally Connected to Ref Out If Not
Connected to External Reference
Control Amp Out Output of Inter nal Control Amplifier
Normally Connected to Ref In
RSet1Connection for Exter nal Resistance
Reference When Using Internal Amplifier
Nominally 7.5 kΩ
Analog Return Analog Return Ground
Analog VEE Analog Negative Supply (–5.2 V)
Digital VEE Digital Negative Supply (–5.2 V)
Digital VCC Digital Positive Supply (+5.2 V)
DGND Digital Ground Return
1Full-Scale Current Out = 128 (Control Amp In / RSet)
25
24
23
22
21
20
19
5
6
7
8
9
10
11
18
17
16
15
14
13
12
26
27
28
1
2
3
4
Analog V
EE
R
Set
Digital V
CC
Ref GND
Digital V
EE
Ref Out
Control Amp In
D6
D7
D8
D9
D10
D11
(LSB) D12
Latch Enable
DGND
(MSB) D1
D2
D3
D4
D5
Control Amp Out
Ref In
Analog V
EE
I
Out
Analog Return
Digital V
EE
I
Out
PLCC
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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
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intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
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IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR
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