Philips
Semiconductors
PCA9518
Expandable 5-channel I2C hub
Product data sheet
Supersedes data of 2004 Jun 24 2004 Sep 29
INTEGRATED CIRCUITS
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2
2004 Sep 29
DESCRIPTION
The PCA9518 is a BiCMOS integrated circuit intended for
application in I2C and SMBus systems.
While retaining all the operating modes and features of the I2C
system, it permits extension of the I2C-bus by buffering both the
data (SDA) and the clock (SCL) lines, thus enabling virtually
unlimited buses of 400 pF.
The I2C-bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9518 enables the system
designer to divide the bus into an unlimited number of segments off
of a hub where any segment to segment transition sees only one
repeater delay and is multiple master capable on each segment.
Using multiple PCA9518 parts, any width hub (in multiples of five)1
can be implemented using the expansion pins.
A PCA9518 cluster cannot be put in series with a PCA9515/16
or with another PCA9518 cluster. Multiple PCA9518 devices can
be grouped with other PCA9518 devices into any size cluster thanks
to the EXPxxxx pins that allow the I2C signals to be sent/received
from/to one PCA9518 to/from another PCA9518 within the cluster.
Since there is no direction pin, slightly different “legal” low voltage
levels are used to avoid lock up conditions between the input and
the output of individual repeaters in the cluster. A “regular low”
applied at the input of any of the PCA9518 devices will then be
propagated as a “buffered low” with a slightly higher value to all
enabled outputs in the PCA9518 cluster. When this “buffered low” is
applied to a PCA9515 and PCA9516 or separate PCA9518 cluster
(not connected via the EXPxxx pins) in series, the second PCA9515
and PCA9516 or PCA9518 cluster will not recognize it as a “regular
low” and will not propagate it as a “buffered low ” again. The
PCA9510/9511/9513/9514 and PCA9512 cannot be used in series
with the PCA9515 and PCA9516 or PCA9518 but can be used in
series with themselves since they use shifting instead of static
offsets to avoid lock up conditions.
FEATURES
Expandable 5 channel, bi-directional buffer
I2C-bus and SMBus compatible
Active-HIGH individual repeater enable inputs
Open-drain input/outputs
Lock-up free operation
Supports arbitration and clock stretching across the repeater
Accommodates standard mode and fast mode I2C devices and
multiple masters
Powered-of f high-impedance I2C pins
Operating supply voltage range of 3.0 V to 3.6 V
5 V tolerant I2C and enable pins
0 kHz to 400 kHz clock frequency2
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101.
Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA.
Package offerings: SO and TSSOP
PIN CONFIGURATION
10
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
20EXPSCL1
EXPSCL2
SCL0
SDA0
SCL1
SDA1
EN1
SCL2
SDA2
GND
VCC
EN4
SDA4
SCL4
EN3
SDA3
SCL3
EXPSDA2
EN2
EXPSDA1
SU01595
Figure 1. Pin configuration
PIN DESCRIPTION
PIN SYMBOL FUNCTION
1 EXPSCL1 Expandable serial clock pin 1
2 EXPSCL2 Expandable serial clock pin 2
3 SCL0 Serial clock bus 0
4 SDA0 Serial data bus 0
5 SCL1 Serial clock bus 1
6 SDA1 Serial data bus 1
7 EN1 Active-HIGH Bus 1 enable Input
8 SCL2 Serial clock bus 2
9 SDA2 Serial data bus 2
10 GND Supply ground
11 EN2 Active-HIGH Bus 2 enable Input
12 SCL3 Serial clock bus 3
13 SDA3 Serial data bus 3
14 EN3 Active-HIGH Bus 3 enable Input
15 SCL4 Serial clock bus 4
16 SDA4 Serial data bus 4
17 EN4 Active-HIGH Bus 4 enable Input
18 EXPSDA1 Expandable serial data pin 1
19 EXPSDA2 Expandable serial data pin 2
20 VCC Supply power
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
20-pin plastic SO –40 °C to +85 °C PCA9518D PCA9518D SOT163-1
20-pin plastic TSSOP –40 °C to +85 °C PCA9518PW PCA9518 SOT360-1
Standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
1. Only four ports per device are available if individual Enable is required.
2. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 3
Hub
Logic
VCC
SCL4
SCL0
SU01596
Buffer
SCL1 Buffer
SCL2 Buffer
EN1
Buffer
SCL3
Buffer
Hub
Logic
SDA4
SDA0 Buffer
SDA1 Buffer
SDA2 Buffer
Buffer
SDA3
Buffer
PCA9518
EN2
EN4
EN3
EXPSDA2
EXPSDA1
EXPSCL1
EXPSCL2
GND
Figure 2. Block Diagram: PCA9518
A more detailed view of Figure 2 buffer is shown in Figure 3.
SW00712
Data
Enable
To output
Inz
Inc
Figure 3. Buffer detail
The output pull-down voltage of each internal buffer is set for
approximately 0.5 V, while the input threshold of each internal buffer
is set about 0.07 V lower, when the output is internally driven LOW.
This prevents a lock-up condition from occurring.
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 4
FUNCTIONAL DESCRIPTION
The PCA9518 BiCMOS integrated circuit is a five way hub repeater,
which enables I2C and similar bus systems to be expanded in
increments of five with only one repeater delay and no functional
degradation of system performance.
The PCA9518 BiCMOS integrated circuit contains five
multi-directional, open drain buf fers specifically designed to support
the standard low-level-contention arbitration of the I2C-bus. Except
during arbitration or clock stretching, the PCA9518 acts like a pair of
non-inverting, open drain buffers, one for SDA and one for SCL.
Enable
The enable pins EN1 through EN4 are active-HIGH and have
internal pull-up resistors. Each enable pin ENn controls its
associated SDAn and SCLn ports. When LOW, the ENn pin blocks
the inputs from SDAn and SCLn, as well as disabling the output
drivers on the SDAn and SCLn pins. The enable pins should only
change state when both the global bus and the local port are in an
idle state to prevent system failures.
The active-HIGH enable pins allow the use of open drain drivers
which can be wire-ORed to create a distributed enable where either
centralized control signal (master) or spoke signal (submaster) can
enable the channel when it is idle.
Expansion
The PCA9518 includes 4 open drain I/O pins used for expansion.
Two expansion pins, EXPSDA1 and EXPSDA2 are used to
communicate the internal state of the serial data within each hub to
the other hubs. The EXPSDA1 pins of all hubs are connected
together to form an open-drain bus. Similarly, all EXPSDA2 pins,
EXPSCL1 pins, and all EXPSCL2 pins are connected together
forming a 4-wire bus between hubs.
When it is necessary to be able to deselect every port, each
expansion device only contributes 4 ports which can be enabled or
disables because the fifth does not have an enable pin.
Pull-up resistors are required on the EXPXXXX3 pins even if only
one PCA9518 is used.
I2C Systems
As with the standard I2C system, pull-up resistors are required to
provide the logic HIGH levels on the Buffered bus. (Standard
open-collector or open-drain configuration of the I2C-bus). The size
of these pull-up resistors depends on the system, but each side of
the repeater must have a pull-up resistor. This part is designed to
work with standard mode (0 to 100 kHz) and fast mode (0 to
400 kHz) I2C devices in addition to SMBus devices. Standard mode
I2C devices only specify 3 mA output drive, this limits the termination
current to 3 mA in a generic I2C system where standard mode
devices and multiple masters are possible. Please see Application
Note AN255
“I
2
C & SMBus Repeaters, Hubs and Expanders”
for
additional information on sizing resistors.
APPLICATION INFORMATION
A typical application is shown in Figure 4. In this example, the
system master is running on a 3.3 V I2C-bus while the slaves are
connected to a 3.3 V or 5 V bus. All buses run at 100 kHz unless
slave 3, 4 and 5 are isolated from the bus. Then the master bus and
slave 1, 2 and 6 can run at 400 kHz.
Any segment of the hub can talk to any other segment of the hub.
Bus masters and slaves can be located on any segment with 400 pF
load allowed on each segment.
The PCA9518 is 5 V tolerant so it does not require any additional
circuitry to translate between the different bus voltages.
When one port of the PCA9518 is pulled LOW by a device on the
I2C-bus, a CMOS hysteresis type input detects the falling edge and
drives the EXPXXX1 line LOW, when the EXPXXX1 voltage is less
than1/2VCC, the other ports are pulled down to the VOL of the
PCA9518 which is typically 0.5 V.
In order to illustrate what would be seen in a typical application, refer
to Figure 5. If the bus master in Figure 4 were to write to the slave
through the PCA9518, we would see the waveform shown in Figure
5. This looks like a normal I2C transmission except for the small foot
preceding each clock LOW to HIGH transition and proceeding each
data LOW to HIGH transition for the master. The foot height is the
difference between the LOW level driven by the master and the
higher voltage LOW level driven by the PCA9518 repeater. Its width
corresponds to an effective clock stretching coming from the
PCA9518 which delays the rising edge of the clock. That same
magnitude of delay is seen on the rising edge of the data. The foot
on the rising edge of the data is extended through the 9th clock
pulse as the PCA9518 repeats the acknowledge from the slave to
the master. The clock of the slave looks normal except the VOL is
the 0.5 V level generated by the PCA9518. The SDA at the slave
has a particularly interesting shape during the 9th clock cycle where
the slave pulls the line below the value driven by the PCA9518
during the acknowledge and then returns to the PCA9518 level
creating a foot before it completes the LOW to HIGH transition. SDA
lines other than the one with the master and the one with the slave
have a uniform LOW level driven by the PCA9518 repeater.
The other four waveforms are the expansion bus signals and are
included primarily for timing reference points. All timing on the
expansion bus is with respect to 0.5 VCC. EXPSDA1 is the
expansion bus that is driven LOW whenever any SDA pin falls
below 0.3 VCC. EXPSDA2 is the expansion bus that is driven LOW
whenever any pin is 0.4 V. EXPSCL1 is the expansion bus that is
driven LOW whenever any SCL pin falls below 0.3 VCC. EXPSCL2
is the expansion bus that is driven LOW whenever any SCL pin is
0.4 V. The EXPSDA2 returns HIGH after the SDA pin that was the
last one being held below 0.4 V by an external driver starts to rise.
The last SDA to rise above 0.4 V is held down by the PCA 9518 to
0.5 V until after the delay of the circuit which determines that it was
the last to rise, then it is allowed to rise above the 0.5 V level driven
by the PCA9518. Considering the bus 0 SDA to be the last one to go
above 0.4 V, then the EXPSDA1 returns to HIGH after the
EXPSDA2 is HIGH and either the bus 0 SDA rise time is 1 µs or,
when the bus 0 SDA reaches 0.7 VCC, whichever occurs first. After
both EXPSDA2 and EXPSDA1 are HIGH the rest of the SDA lines
are allowed to rise. The same description applies for the EXPSCL1,
EXPSCL2, and SCL pins.
3. XXXX is SDA1, SDA2, SCL1, or SCL2
XXX is SDA or SCL
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 5
SW00974
BUS
MASTER
SUBSYSTEM 1
SDA SDA0
SDA
SCL SCL0
SCL
EN1
3.3 V 5 V
SDA1
SCL1
EN2
EN3
EN4
SDA
SCL
3.3 V
SDA2
SCL2
SDA
SCL
5 V
SDA3
SCL3
SDA
SCL
3.3 V
SDA4
SCL4
SDA0
SCL0
EN1
SDA1
SCL1
EN2
EN3
EN4
SDA2
SCL2
SDA3
SCL3
SDA4
SCL4
EXPSDA1 EXPSDA1
EXPSDA2 EXPSDA2
EXPSCL1
EXPSCL1
EXPSCL2 EXPSCL2
SUBSYSTEM 2
SUBSYSTEM 3
SUBSYSTEM 4
SUBSYSTEM 5
SDA
SCL
5 V
SDA
SCL
3.3 V
SUBSYSTEM 6
DISABLED
NOT CONNECTED
100 kHz
400 kHz
400 kHz
400 kHz
100 kHz
100 kHz
400 kHz
GND GND
VDD VDD
PCA9518
DEVICE 2 PCA9518
DEVICE 1
3.3 V or 5 V
3.3 V or 5 V
NOTE:
1. Only two of the five channels on the PCA9518 Device 2 are being used. EN3 and EN4 are connected to GND to disable channels 3 and 4
and/or SDA3/SCL3 and SDA4/SCL4 are pulled up to VCC. SDA0 and SCL0 can be used as a normal I2C port, but if unused then it must be
pulled-up to VCC since there is no enable pin.
Figure 4. Typical application: Multiple expandable 5-channel I2C hubs
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 6
tst
9TH CLOCK CYCLE 9TH CLOCK CYCLE
VOL OF MASTER VOL OF PCA9518
VOL OF PCA9518
VOL OF SLAVE
tPLH
tPHL
tf1
tf2
tr1
tEr1
tr2
SCL OF MASTER
SDA OF MASTER
EXPSDA1
EXPSDA2
EXPSCL1
EXPSCL2
SCL OF SLAVE
SDA OF SLAVE
BUS n
WITH n > 1
BUS 0
EXPANSION
BUS
BUS 1
SW01090
Figure 5. Bus waveforms
It is important to note that any arbitration or clock stretching events on Bus 1 require that the VOL of the devices on Bus 1 be 70 mV below the
VOL of the PCA9518 (see VOL – Vilc in the DC Characteristics section) to be recognized by the PCA9518 and then transmitted to Bus 0.
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 7
ABSOLUTE MAXIMUM RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134).
Voltages with respect to pin GND.
LIMITS
SYMBOL PARAMETER MIN. MAX. UNIT
VCC to GND Supply voltage range VCC –0.5 +7 V
Vbus Voltage range I2C-bus, SCL or SDA –0.5 +7 V
IDC current (any pin) 50 mA
Ptot Power dissipation 300 mW
Tstg Storage temperature range –55 +125 °C
Tamb Operating ambient temperature range –40 +85 °C
DC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 3.6 V ; GND = 0 V; Tamb = –40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN. TYP. MAX.
UNIT
Supplies
VCC DC supply voltage 3.0 3.3 3.6 V
ICCH Quiescent supply current,
both channels HIGH VCC = 3.6 V ;
SDAn = SCLn = VCC 7.5 10 mA
ICCL Quiescent supply current,
both channels LOW VCC = 3.6 V ;
one SDA and one SCL = GND,
other SDA and SCL open
9 11 mA
ICCLc Quiescent supply current in contention VCC = 3.6 V ;
SDAn = SCLn = GND 9 11 mA
Input SCL; input/output SDA
VIH HIGH-level input voltage, SCL, SDA 0.7 VCC 5.5 V
VIL LOW-level input voltage, SCL, SDA
(Note 1) –0.5 0.3 VCC V
VILc LOW-level input voltage contention,
SCL, SDA (Note 1) –0.5 0.4 V
VIK Input clamp voltage II = –18 mA –1.2 V
IIInput leakage current VI = 3.6 V ±1µA
IIL Input current LOW, SDA, SCL VI = 0.2 V, SDA, SCL 5 µA
VOL LOW level output, SCL, SDA IOL = 02 or 6 mA 0.47 0.52 0.6 V
VOL–VILc LOW level input voltage below
output LOW level voltage Guaranteed by design 70 mV
CIInput capacitance VI = 3 V or 0 V 6 8 pF
Enable 1–4
VIL LOW level input voltage –0.5 0.8 V
VIH HIGH level input voltage 2.0 5.5 V
IIL Input current LOW VI = 0.2 V, EN1–EN4 10 30 µA
ILI Input leakage current –1 1 µA
CIInput capacitance VI = 3.0 V or 0 V 3 7 pF
Expansion Pins
VIH HIGH level input voltage, EXP* 0.55
VCC 5.5 V
VIL LOW level input voltage, EXP* –0.5 0.45 VCC V
IIL Input current LOW, EXP* VI = 0.2 V, EXP* 5 µA
VOL LOW level output, EXP* IOL = 12 mA 0.5 V
CIInput capacitance VI = 3.0 V or 0 V 6 8 pF
NOTE:
1. VIL specification is for the first LOW level seen by the SDAx/SCLx lines. VILc is for the second and subsequent LOW levels seen by the
SDAx/SCLx lines.
2. Test performed with IOL = 10 µA.
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 8
AC ELECTRICAL CHARACTERISTICS1
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS3
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
tPHLs Propagation delay
SDA to SDAn or SCL to SCLn Waveform 1; Note 2 105 202 389 ns
tPLHs Propagation delay
SDA to SDAn or SCL to SCLn Waveform 1; Note 3 110 259 265 ns
tPHLE1s Propagation delay
EXPSDA1 to SDA or EXPSCL1 to SCL W aveform 1 109 193 327 ns
tPLHE1s Propagation delay
EXPSDA1 to SDA or EXPSCL1 to SCL W aveform 1 130 153 179 ns
tPLHE2s Propagation delay
EXPSDA2 to SDA or EXPSCL2 to SCL W aveform 1 160 234 279 ns
tTHLs T ransition time, SDA/SCL W aveform 1 58 110 187 ns
tTLHs T ransition time, SDA/SCL W aveform 1 0.85 RC ns
tSET Enable to Start condition 300 ns
tHOLD Enable after Stop condition 300 ns
NOTES:
1. The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are only
sensitive to load capacitance. The rise times are RC time constant controlled and therefor a specific numerical value can only be given for
fixed RC time constants.
2. The SDA HIGH to LOW propagation delay, tPLHs, includes the fall time from VCC to 0.5 VCC of the EXPSDA1 or EXPSCL1 pins and the SDA
or SCL fall time from the quiescent HIGH (usually VCC) to below 0.3 VCC. The SDA and SCL outputs have edge rate control circuits included
which make the fall time almost independent of load capacitance.
3. The SDA or SCL LOW to HIGH propagation delay includes the rise time constant from the quiescent LOW to 0.5 VCC for the EXPSDA1 or
EXPSCL2, the rise time constant for the quiescent LOW to 0.5 VCC for the EXPSDA1 or EXPSCL1, and the rise time constant from the
quiescent external driven LOW to 0.7 VCC for the SDA or SCL output. All of these rise times are RC time constants determined by the
external R and total C for the various nodes.
AC WAVEFORMS
SW01089
0.7 VCC
0.4 V
tTLHs
tTHLs
tPHLs
tTHLs
tPHLs
EFFECTIVE
STRETCH
tPLHs
tPLHE1s
tPLHE2s tPLHs
0.3 VCC
0.4 V
0.3 VCC
0.7 VCC
0.5 VCC 0.5 VCC
0.5 VCC 0.5 VCC
0.7 VCC 0.7 VCC
0.3 VCC
0.3 VCC
0.52 V
INPUT
SDA
OR SCL
EXPSDA1
OR
EXPSCL1
EXPSDA2
OR
EXPSCL2
OUTPUT
SDA
OR SCL
W aveform 1.
TEST CIRCUIT
DEFINITIONS
RL = Load resistor; 1.1 k for I2C and 500 for EXP.
CL = Load capacitance includes jig and probe capacitance;
100 pF for I2C and 100 pF for EXP
RT = Termination resistance should be equal to ZOUT of
pulse generators.
PULSE
GENERATOR
VIN D.U.T. VOUT
CL
VCC
RL
Test circuit for open-drain outputs
RT
SW01088
VCC
Figure 6. Test circuit
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 9
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 10
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 11
REVISION HISTORY
Rev Date Description
_4 20040929 Product data sheet (9397 750 14109). Supersedes data of 2004 Jun 24 (9397 750 13253).
Modifications:
“Description” section on page 2, last sentence: change from “The PCA9511/9513/9514 and the PCA9512
cannot be used in series ...” to “The PCA9510/9511/9513/9514 and PCA9512 cannot be used in series ...”
Figure 4 on page 5 modified.
Note 1 on page 5 re-written.
_3 20040624 Product data sheet (9397 750 13253). Supersedes data of 10 November 2003 (9397 750 12295).
_2 20031110 Product data (9397 750 12295); ECN 853-2364 30410 dated 03 October 2003.
Supersedes data of 20 August 2002 (9397 750 10258).
_1 20020820 Product data (9397 750 10258); ECN: 853–2364 28791 (2002 Aug 20)
Philips Semiconductors Product data sheet
PCA9518Expandable 5-channel I2C hub
2004 Sep 29 12
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2004
All rights reserved. Published in the U.S.A.
Date of release: 09-04
Document number: 9397 750 14109


Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III