CLC1001
Ultra-Low Noise Amplifier
© 2007-2014 Exar Corporation 1 / 18 exar.com/CLC1001
Rev 1H
FEATURES
0.6nV/√Hz input voltage noise
1mV maximum input offset voltage
2.1GHz gain bandwidth product
Minimum stable gain of 10
410V/μs slew rate
130mA output current
-40°C to +125°C operating temperature
range
Fully specied at 5 and ±5V supplies
CLC1001: ROHS compliant TSOT-6,
SOIC-8 package options
APPLICATIONS
Transimpedance ampliers
Pre-amplier
Low noise signal processing
Medical instrumentation
Probe equipment
Test equipment
Ultrasound channel amplier
General Description
The CLC1001 is a high-performance, voltage feedback amplier with
ultra-low input voltage noise, 0.6nV/√Hz. The CLC1001 provides 2.1GHz
gain bandwidth product and 410V/μs slew rate making it well suited for
high-speed data acquisition systems requiring high levels of sensitivity
and signal integrity. This high-performance amplier also offers low input
offset voltage.
The CLC1001 is designed to operate from 4V to 12V supplies. It
consumes only 12.5mA of supply current per channel and offers a power
saving disable pin that disables the amplier and decreases the supply
current to below 225μA. The CLC1001 amplier operates over the
extended temperature range of -40°C to +125°C.
If a lower minimum stable gain is required, the CLC1002 offers a minimum
stable gain of 5.
Typical Application
Photo
Diode
VOUT
R1
R2
Rf
R3
+Vs
-
+
Single Supply Photodiode Amplier
Input Voltage Noise vs Competition
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0.1 110
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
Competition
CLC1002CLC1001
Ordering Information - back page
© 2007-2014 Exar Corporation 2 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Absolute Maximum Ratings
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
VS ................................................................................. 0V to +14V
VIN ............................................................ -VS - 0.5V to +VS +0.5V
Operating Conditions
Supply Voltage Range .......................................................4 to 12V
Operating Temperature Range ...............................-40°C to 125°C
Junction Temperature ...........................................................150°C
Storage Temperature Range ...................................-65°C to 150°C
Lead Temperature (Soldering, 10s) ......................................260°C
Package Thermal Resistance
θJA (TSOT-6) .....................................................................192°C/W
θJA (SOIC-8) .....................................................................150°C/W
Package thermal resistance (θJA), JEDEC standard, multi-layer
test boards, still air.
ESD Protection
CLC1001 (HBM) .......................................................................2kV
ESD Rating for HBM (Human Body Model).
© 2007-2014 Exar Corporation 3 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Electrical Characteristics at +5V
TA = 25°C, VS = +5V, Rf = 200Ω, RL = 500Ω to VS/2; G = 10; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product G = +40, VOUT = 0.2Vpp 2000 MHz
BWSS -3dB Bandwidth G = +10, VOUT = 0.2Vpp 265 MHz
f0.1dBSS 0.1dB Gain Flatness Small Signal G = +10, VOUT = 0.2Vpp 37 MHz
BWLS Large Signal Bandwidth G = +10, VOUT = 2Vpp 105 MHz
f0.1dBLS 0.1dB Gain Flatness Large Signal G = +10, VOUT = 2Vpp 36 MHz
Time Domain
tR, tFRise and Fall Time VOUT = 1V step; (10% to 90%) 2.4 ns
tSSettling Time to 0.1% VOUT = 1V step 11 ns
OS Overshoot VOUT = 1V step 6 %
SR Slew Rate 4V step 360 V/μs
Distortion/Noise Response
HD2 2nd Harmonic Distortion 10MHz, VOUT = 1Vpp 80 dBc
HD3 3rd Harmonic Distortion 10MHz, VOUT = 1Vpp 83 dBc
THD Total Harmonic Distortion 10MHz, VOUT = 1Vpp 79 dB
enInput Voltage Noise >100kHz 0.6 nV/√Hz
inInput Current Noise >100kHz 4.2 pA/√Hz
DC Performance
VIO Input Offset Voltage 0.1 mV
dVIO Average Drift 2.7 μV/°C
IBInput Bias Current 28 μA
dIBAverage Drift 45 nA/°C
IOS Input Offset Current 0.5 μA
PSRR Power Supply Rejection Ratio DC 83 dB
AOL Open Loop Gain VOUT = VS / 2 82 dB
ISSupply Current per channel 12 mA
Disable Characteristics
tON Turn On Time 1V step, 1% settling 100 ns
tOFF Turn Off Time 900 ns
OFFISO Off Isolation 2Vpp , 5MHz 80 dB
OFFCOUT Off Output Capacitance 5.7 pF
VOFF Power Down Voltage
Disabled if DIS pin is grounded or pulled below VOFF
Disabled if DIS < 1.5 V
VON Enable Voltage
Enabled if DIS pin is oating or pulled above VON
Enabled if DIS > 3 V
ISD Disable Supply Current No Load, DIS pin tied to ground 130 μA
Input Characteristics
RIN Input Resistance Non-inverting 2.6 MΩ
CIN Input Capacitance 1. 6 pF
CMIR Common Mode Input Range 0.8 to 5.1 V
CMRR Common Mode Rejection Ratio DC, VCM = 1.5V to 4V 85 dB
Output Characteristics
VOUT Output Swing RL = 500Ω 0.93 to 4 V
RL = 2kΩ 0.9 to 4.1 V
IOUT Output Current ±130 mA
ISC Short Circuit Current VOUT = VS / 2 ±150 mA
© 2007-2014 Exar Corporation 4 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Electrical Characteristics at ±5V
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω to GND; G = 10; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product G = +40, VOUT = 0.2Vpp 2100 MHz
BWSS -3dB Bandwidth G = +10, VOUT = 0.2Vpp 284 MHz
f0.1dBSS 0.1dB Gain Flatness Small Signal G = +10, VOUT = 0.2Vpp 42 MHz
BWLS Large Signal Bandwidth G = +10, VOUT = 2Vpp 117 MHz
f0.1dBLS 0.1dB Gain Flatness Large Signal G = +10, VOUT = 2Vpp 47 MHz
Time Domain
tR, tFRise and Fall Time VOUT = 1V step; (10% to 90%) 2.2 ns
tSSettling Time to 0.1% VOUT = 1V step 11 ns
OS Overshoot VOUT = 1V step 3 %
SR Slew Rate 4V step 410 V/μs
Distortion/Noise Response
HD2 2nd Harmonic Distortion 10MHz, VOUT = 2Vpp 81 dBc
HD3 3rd Harmonic Distortion 10MHz, VOUT = 2Vpp 75 dBc
THD Total Harmonic Distortion 10MHz, VOUT = 2Vpp 74 dB
enInput Voltage Noise >100kHz 0.6 nV/√Hz
inInput Current Noise >100kHz 4.2 pA/√Hz
DC Performance
VIO Input Offset Voltage -1 0.35 1 mV
dVIO Average Drift 4.4 μV/°C
IBInput Bias Current -60 30 60 μA
dIBAverage Drift 44 nA/°C
IOS Input Offset Current 0.8 6 μA
PSRR Power Supply Rejection Ratio DC 78 83 dB
AOL Open Loop Gain VOUT = VS / 2 74 83 dB
ISSupply Current per channel 12.5 16 mA
Disable Characteristics
tON Turn On Time 1V step, 1% settling 125 ns
tOFF Turn Off Time 840 ns
OFFISO Off Isolation 2Vpp , 5MHz 80 dB
OFFCOUT Off Output Capacitance 5.6 pF
VOFF Power Down Voltage
Disabled if DIS pin is grounded or pulled below VOFF
Disabled if DIS < 1.3 V
VON Enable Voltage
Enabled if DIS pin is oating or pulled above VON
Enabled if DIS > 3 V
ISD Disable Supply Current No Load, DIS pin tied to ground 180 225 μA
Input Characteristics
RIN Input Resistance Non-inverting 4 MΩ
CIN Input Capacitance 1. 5 pF
CMIR Common Mode Input Range -4.3 to 5.1 V
CMRR Common Mode Rejection Ratio DC, VCM = -3.5V to 4V 75 90 dB
Output Characteristics
VOUT Output Swing RL = 500Ω -3.8 ±4 3.8 V
RL = 2kΩ ±4 V
IOUT Output Current ±130 mA
ISC Short Circuit Current VOUT = VS / 2 ±160 mA
© 2007-2014 Exar Corporation 5 / 18 exar.com/CLC1001
Rev 1H
CLC1001
SOIC-8
Pin No. Pin Name Description
1 NC No Connect
2 -IN Negative input
3 +IN Positive input
4 -VSNegative supply
5 NC No Connect
6 OUT Output
7 +VSPositive supply
8 DIS
Disable. Enabled if pin is left oating or pulled
above VON, disabled if pin is grounded or
pulled below VOFF.
SOIC-8
-
+
1
2
3
4
NC
-IN
+IN
-Vs
DIS
+Vs
OUT
NC
8
7
6
5
CLC1001 Pin Assignments
TSOT-6
Pin No. Pin Name Description
1 OUT Output
2 -VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 DIS
Disable. Enabled if pin is left oating or pulled
above VON, disabled if pin is grounded or
pulled below VOFF.
6 +VSPositive supply
CLC1001 Pin Congurations
TSOT-6
-
+
2
3
6
4
+IN
+Vs
5DIS
-IN
1
-Vs
OUT
© 2007-2014 Exar Corporation 6 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
Frequency Response vs. VOUT -3dB Bandwidth vs. Output Voltage
Frequency Response vs. CL Frequency Response vs. RL
Non-Inverting Frequency Response Inverting Frequency Response
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = +10
G = +20
G = +40
VOUT = 0.2Vpp
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = -10
G = -20
G = -40
VOUT = 0.2Vpp
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
VOUT = 0.2Vpp
CL= 100pF
Rs= 13Ω
CL= 47pF
Rs= 20Ω
CL= 22pF
Rs= 33Ω
CL= 10pF
Rs= 43Ω
CL= 470pF
Rs= 4.3Ω
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
Rl = 1K
Rl = 2K
Rl = 5K
VOUT = 0.2Vpp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
VOUT = 2Vpp
VOUT = 3Vpp
VOUT = 4Vpp
0
50
100
150
200
250
300
0.0 1.0 2.0 3.0 4.0
-3dB Bandwidth (MHz)
VOUT (VPP)
© 2007-2014 Exar Corporation 7 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
Frequency Response vs. VOUT at VS = 5V -3dB Bandwidth vs. Output Voltage at VS = 5V
Frequency Response vs. CL at VS = 5V Frequency Response vs. RL at VS = 5V
Non-Inverting Frequency Response at VS = 5V Inverting Frequency Response at VS = 5V
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = +10
G = +20
G = +40
VOUT = 0.2Vpp
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
G = -10
G = -20
G = -40
VOUT = 0.2Vpp
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
VOUT = 0.2Vpp
CL= 100pF
Rs= 15Ω
CL= 47pF
Rs= 22Ω
CL= 22pF
Rs= 36Ω
CL= 10pF
Rs= 50Ω
CL= 470pF
Rs= 5Ω
-9
-6
-3
0
3
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
Rl = 1K
Rl = 2K
Rl = 5K
VOUT = 0.2Vpp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100 1000
Normalized Gain (dB)
Frequency (MHz)
VOUT = 1Vpp
VOUT = 1.5Vpp
VOUT = 2Vpp
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0
-3dB Bandwidth (MHz)
VOUT (VPP)
© 2007-2014 Exar Corporation 8 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
ROUT vs. Frequency
Input Voltage Noise (>10kHz) Input Voltage Noise at VS = 5V (>10kHz)
Input Voltage Noise Input Voltage Noise at VS = 5V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
0.0001 0.001 0.01 0.1 110
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
0.0001 0.001 0.01 0.1 110
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
10
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.01 0.1 110
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
10
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.01 0.1 110
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
10
0.01
0.1
1
10
100
0.001 0.01 0.1 110 100 1000
ROUT (Ω)
Frequency (MHz)
© 2007-2014 Exar Corporation 9 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
2nd Harmonic Distortion vs. Gain 3rd Harmonic Distortion vs. Gain
2nd Harmonic Distortion vs. VOUT 3rd Harmonic Distortion vs. VOUT
2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL
-115
-105
-95
-85
-75
-65
510 15 20
Distortion (dBc)
Frequency (MHz)
RL= 500Ω
VOUT = 1Vpp
RL= 1kΩ
-115
-105
-95
-85
-75
-65
510 15 20
Distortion (dBc)
Frequency (MHz)
VOUT = 1Vpp
RL= 500Ω
VOUT = 1Vpp
RL= 1kΩ
-105
-100
-95
-90
-85
-80
-75
-70
-65
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (Vpp)
10MHz
5MHz
20MHz
RL = 500Ω
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (Vpp)
10MHz
5MHz
20MHz
RL = 500Ω
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
510 15 20
Distortion (dBc)
Frequency (MHz)
AV+20
AV+10
AV+40
RL= 500Ω
VOUT = 1VPP
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
510 15 20
Distortion (dBc)
Frequency (MHz)
AV+20
AV+10
AV+40
RL= 500Ω
VOUT = 1VPP
© 2007-2014 Exar Corporation 10 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
2nd Harmonic Distortion vs. Gain at VS = 5V 3rd Harmonic Distortion vs. Gain at VS = 5V
2nd Harmonic Distortion vs. VOUT at VS = 5V 3rd Harmonic Distortion vs. VOUT at VS = 5V
2nd Harmonic Distortion vs. RL at VS = 5V 3rd Harmonic Distortion vs. RL at VS = 5V
-115
-105
-95
-85
-75
-65
510 15 20
Distortion (dBc)
Frequency (MHz)
VOUT = 1Vpp
RL= 500Ω
VOUT = 1Vpp
RL= 1kΩ
-115
-105
-95
-85
-75
-65
510 15 20
Distortion (dBc)
Frequency (MHz)
VOUT = 1Vpp
RL= 500Ω
VOUT = 1Vpp
RL= 1kΩ
-95
-90
-85
-80
-75
-70
-65
-60
-55
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (Vpp)
10MHz
5MHz
20MHz
RL = 500Ω
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (Vpp)
10MHz 5MHz
20MHz
RL = 500Ω
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
510 15 20
Distortion (dBc)
Frequency (MHz)
AV+20
AV+10
AV+40
RL= 500Ω
VOUT = 1VPP
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
510 15 20
Distortion (dBc)
Frequency (MHz)
AV+20
AV+10
AV+40
RL= 500Ω
VOUT = 1VPP
© 2007-2014 Exar Corporation 11 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
Enable Response Disable Response
Large Signal Pulse Response Large Signal Pulse Response at VS = 5V
Small Signal Pulse Response Small Signal Pulse Response at VS = 5V
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
050 100 150 200
Voltage (V)
Time (ns)
2.35
2.4
2.45
2.5
2.55
2.6
2.65
050 100 150 200
Voltage (V)
Time (ns)
-3
-2
-1
0
1
2
3
050 100 150 200
Voltage (V)
Time (ns)
1
1.5
2
2.5
3
3.5
4
050 100 150 200
Voltage (V)
Time (ns)
-0.5
0
0.5
1
1.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
-50 050 100 150 200
Output Voltage (V)
Enable Voltage (V)
Time (ns)
Output
Enable
-0.5
0
0.5
1
1.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
-100 0100 200 300 400 500 600 700 800 900
Output Voltage (V)
Disable Voltage (V)
Time (ns)
Output
Disable
© 2007-2014 Exar Corporation 12 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 200Ω, RL = 500Ω, G = +10; unless otherwise noted.
CMRR vs. Frequency PSRR vs. Frequency
Off Isolation Off Isolation at VS = 5V
Enable Response at VS = 5V Disable Response at VS = 5V
-0.5
0
0.5
1
1.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
-50 050 100 150 200
Output Voltage (V)
Enable Voltage (V)
Time (ns)
Output
Enable
-0.5
0
0.5
1
1.5
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
-100 0100 200 300 400 500 600 700 800 900
Output Voltage (V)
Disable Voltage (V)
Time (ns)
Output
Disable
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
110 100
Off Isolation (dB)
Frequency (MHz)
VOUT = 2Vpp
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
110 100
Off Isolation (dB)
Frequency (MHz)
VOUT = 2Vpp
0
20
40
60
80
100
0.001 0.01 0.1 110 100 1000
CMRR (dB)
Frequency (MHz)
0
20
40
60
80
100
0.001 0.01 0.1 110 100
PSRR (dB)
Frequency (MHz)
© 2007-2014 Exar Corporation 13 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Application Information
Basic Information
Figures 1 and 2 illustrate typical circuit congurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+
-
Rf
0.1μF
6.8μF
Output
G = 1 + (Rf/Rg)
Input
+Vs
-Vs
Rg
0.1μF
6.8μF
RL
Figure 1: Typical Non-Inverting Gain Circuit
+
-
Rf
0.1μF
6.8μF
Output
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Rg
R1
Figure 2: Typical Inverting Gain Circuit
Achieving Low Noise in an Application
Making full use of the low noise of the CLC1001 requires
careful consideration of resistor values. The feedback and
gain set resistors (Rf and Rg) and the non-inverting source
impedance (Rsource) all contribute noise to the circuit and
can easily dominate the overall noise if their values are
too high. The datasheet is specied with an Rg of 22.1Ω,
at which point the noise from Rf and Rg is about equal to
the noise from the CLC1001. Lower value resistors could be
used at the expense of more distortion. Figure 3 shows total
input voltage noise (amp+resistors) versus Rf and Rg. As
the value of Rf increases, the total input referred noise also
increases.
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
100 1000
Input Referred Noise (nV/rtHz)
Rf (Ohms)
G = +11
G = +21
G = +41
Figure 3: Input Referred Voltage Noise vs. Rf and Rg
The noise caused by a resistor is modeled with either a
voltage source in series with the resistance:
4kTR
Or a current source in parallel with it:
iR
R=4kT
Op amp noise is modeled with three noise sources, en, in,
in and ii. These three sources are analogous to the DC input
voltage and current errors Vos, Ibn and Ibi.
The noise models must be analyzed in-circuit to determine
the effect on the op amp output noise.
Since noise is statistical in nature rather than a continuous
signal, the set of noise sources in circuit add in an RMS
(root mean square) fashion rather than in a linear fashion.
For uncorrelated noise sources, this means you add the
squares of the noise voltages. A typical non-inverting
application (see gure 1) results in the following noise at the
output of the op amp:
e
o
2
=e
n
2
1+R
f
R
g
2
+ in
2
R
s
2
1+R
f
R
g
2
+ i
i
2
R
f
2
op amp noise terms e
n
, i
n
and i
i
op amp noise terms en, in and ii
+ e
Rs
2
1 +R
f
R
g
2
+ e
Rg
2
R
f
R
g
2
+ e
Rf
2
external resistor noise terms for RS, Rg and Rf
© 2007-2014 Exar Corporation 14 / 18 exar.com/CLC1001
Rev 1H
CLC1001
High source impedances are sometimes unavoidable, but
they increase noise from the source impedance and also
make the circuit more sensitive to the op amp current noise.
Analyze all noise sources in the circuit, not just the op amp
itself, to achieve low noise in your application.
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 500Ω load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature is
not exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value ThetaJA
(θJA) is used along with the total die power dissipation.
TJunction = TAmbient + (θJA × PD)
Where TAmbient is the temperature of the working
environment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by the
supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equation.
Psupply = Vsupply × IRMSsupply
Vsupply = VS+ - VS-
Power delivered to a purely resistive load is:
Pload = ((Vload)RMS2)/Rloadeff
The effective load resistor (Rloadeff) will need to include the
effect of the feedback network. For instance,
Rloadeff in Figure 3 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - Pload
Quiescent power can be derived from the specied IS values
along with known supply voltage, Vsupply. Load power can
be calculated as above with the desired signal amplitudes
using:
(Vload)RMS = Vpeak / √2
( Iload)RMS = ( Vload)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDynamic = (VS+ - Vload)RMS × ( Iload)RMS
Assuming the load is referenced in the middle of the power
rails or Vsupply/2.
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the packages
available.
0
0.5
1
1.5
2
-40 -20 020 40 60 80 100 120
Maximum Power Dissipation (W)
Ambient Temperature (°C)
TSOT-6
SOIC-8
Figure 4. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
possible unstable behavior. Use a series resistance, RS,
between the amplier and the load to help improve stability
and settling performance. Refer to Figure 5.
+
-
Rf
Input
Output
Rg
Rs
CLRL
Figure 5. Addition of RS for Driving Capacitive Loads
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in approximately
<1dB peaking in the frequency response. The Frequency
Response vs. CL plots, on page 6 and 7, illustrate the
response of the CLC1001.
© 2007-2014 Exar Corporation 15 / 18 exar.com/CLC1001
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CLC1001
CL (pF) RS (Ω) -3dB BW (MHz)
10 43 266
22 33 228
47 20 192
100 13 155
470 4.3 84
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
Overdrive Recovery
For an amplier, an overdrive condition is dened as the
point when either one of the inputs or the output exceed
their specied voltage range. Overdrive recovery is the time
needed for the amplier to return to its normal or linear
operating point. The recovery time varies based on whether
the input or output is overdriven and by how much the
ranges are exceeded. The CLC1001 will typically recover in
less than 25ns from an overdrive condition. Figure 6 shows
the CLC1001 in an overdriven condition.
-6
-4
-2
0
2
4
6
0100 200 300 400 500 600 700 800 900 1,000
Voltage (V)
Time (ns)
Vs= +/-5V_RL=2K_AV=+5
INPUT
OUTPUT
Figure 6: Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board # Products
CEB002 CLC1001 in TSOT
CEB003 CLC1001 in SOIC
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 7-11 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
Figure 7. CEB002 & CEB003 Schematic
© 2007-2014 Exar Corporation 16 / 18 exar.com/CLC1001
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CLC1001
Figure 8. CEB002 Top View
Figure 9. CEB002 Bottom View
Figure 10. CEB003 Top View
Figure 11. CEB003 Bottom View
© 2007-2014 Exar Corporation 17 / 18 exar.com/CLC1001
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CLC1001
Mechanical Dimensions
TSOT-6 Package
SOIC-8 Package
For Further Assistance:
Email: CustomerSupport@exar.com or HPATechSupport@exar.com
Exar Technical Documentation: http://www.exar.com/techdoc/
Exar Corporation Headquarters and Sales Offices
48760 Kato Road Tel.: +1 (510) 668-7000
Fremont, CA 94538 - USA Fax: +1 (510) 668-7001
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation
assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free
of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specic application. While the information
in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected
to cause failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR
Corporation is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
© 2007-2014 Exar Corporation 18 / 18 exar.com/CLC1001
Rev 1H
CLC1001
Ordering Information
Part Number Package Green Operating Temperature Range Packaging Quantity
CLC1001 Ordering Information
CLC1001IST6X TSOT-6 Ye s -40°C to +125°C 2.5k Tape & Reel
CLC1001IST6MTR TSOT-6 Ye s -40°C to +125°C 250 Tape & Reel
CLC1001IST6EVB Evaluation Board N/A N/A N/A
CLC1001ISO8X SOIC-8 Ye s -40°C to +125°C 2.5k Tape & Reel
CLC1001ISO8MTR SOIC-8 Ye s -40°C to +125°C 250 Tape & Reel
CLC1001ISO8EVB Evaluation Board N/A N/A N/A
Moisture sensitivity level for all parts is MSL-1.
Revision History
Revision Date Description
1H (ECN 1441-02) September
2014
Reformat into Exar data sheet template. Updated ordering information table to include MTR and EVB
part numbers. Increased “I” temperature range from +85 to +125°C. Removed “A” temp grade parts,
since “I” is now equivalent. Updated thermal resistance numbers and package outline drawings.
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Exar:
CLC1001ISO8X CLC1001IST6X CLC1001IST6EVB CLC1001AST6EVB CLC1001ISO8MTR CLC1001ASO8EVB
CLC1001IST6MTR CLC1001ISO8EVB