250 V / 500 V High V oltage 3-phase Motor Driver ICs
SX6800xMH Series Data Sheet
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© SANKEN ELECTRIC CO., LTD. 2013
Description
The SX6800xMH series are high voltage 3-phase
motor driver ICs in which transistors, a pre-driver IC
(MIC), and bootstrap circuits (diodes and resistors) are
highly int egrat ed.
These products can optimally control the inverter
systems of small- to medium-capacity motors that
require universal input standards.
Features
Built-in Bootstrap Diodes with Current Limiting
Resistors (60 Ω)
CMOS-compatible Input (3.3 V or 5 V)
Bare Lead Frame: Pb-free (RoHS Compliant)
Fault Signal Outp ut at Protection Activation (FO Pin)
High-side Shutdown Signal Input (SD Pin)
Protec tions Include:
Overcurrent Limit (OCL): Auto-restart
Overcurrent Protection (OCP): Auto-restart
Unde rvolt age Lockout for Power Supp ly
High-side (UVLO_VB): Auto-restart
Low-side (UVLO_VCC): Auto-restart
Thermal Shutdown (TSD): Auto-restart
Typical Application
SD
VCC1VB31
VB1
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB1
V2
LS
V
VB2
VB32
C
FO
5 V
R
FO
R
S
R
O
C
O
VCC
Con troller
C
BOOT1
C
BOOT3
C
BOOT2
M
C
DC
C
S
V
DC
MIC
16
15
14
12
11
10
8
7
6
5
4
327
21
24
23
22
25
20
19
18
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
Fault
GND
9
1
2
VBB2
26
REG 13
17
A/D
REG
Package
SOP27
Not to scale
Selection Guide
VDSS IO Part Number
250 V 2.0 A SX68001MH
500 V 1.5 A SX68002MH
2.5 A SX68003MH
Applications
Fan Motor for Air Conditioner
Fan Motor for Air Purifier and Electric Fan
27
18
17
1
SX6800xMH Series
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Contents
Description ------------------------------------------------------------------------------------------------------ 1
Contents --------------------------------------------------------------------------------------------------------- 2
1. Absolute Maximum Ratings ----------------------------------------------------------------------------- 4
2. Reco mmended Opera ting Conditions ----------------------------------------------------------------- 5
3. Electrical Characteristics -------------------------------------------------------------------------------- 6
3.1 Characteristics of Control Parts ------------------------------------------------------------------ 6
3.2 Bootstrap Diode Characteristics ----------------------------------------------------------------- 7
3.3 Thermal Resistance Characteristics ------------------------------------------------------------- 7
3.4 Transistor Characteristics ------------------------------------------------------------------------- 8
3.4.1 SX68001MH ------------------------------------------------------------------------------------ 9
3.4.2 SX68002MH ------------------------------------------------------------------------------------ 9
3.4.3 SX68003MH ---------------------------------------------------------------------------------- 10
4. Mechanical Characteristics --------------------------------------------------------------------------- 10
5. Truth Ta ble ----------------------------------------------------------------------------------------------- 11
6. Block Diagram ------------------------------------------------------------------------------------------- 12
7. Pin Configuration Definitions ------------------------------------------------------------------------- 13
8. Typical Application ------------------------------------------------------------------------------------- 14
9. Physical Dimensions ------------------------------------------------------------------------------------ 15
10. Marking Diagram --------------------------------------------------------------------------------------- 16
11. Funct ional Descr iptions -------------------------------------------------------------------------------- 17
11.1 Turning On and Off the IC ---------------------------------------------------------------------- 17
11.2 Pin Descriptions ----------------------------------------------------------------------------------- 17
11.2.1 U, V, V1, V2, W1, and W2 ----------------------------------------------------------------- 17
11.2.2 VB1, VB2, VB31, a nd VB 32 --------------------------------------------------------------- 17
11.2.3 VCC1 and VCC2 ---------------------------------------------------------------------------- 18
11.2.4 COM1 and COM2--------------------------------------------------------------------------- 18
11.2.5 REG -------------------------------------------------------------------------------------------- 19
11.2.6 HIN1, HIN2 , and H IN 3; LIN1, LIN2, and LIN3 -------------------------------------- 19
11.2.7 VBB1 and VBB2 ----------------------------------------------------------------------------- 19
11.2.8 LS ----------------------------------------------------------------------------------------------- 20
11.2.9 OCL -------------------------------------------------------------------------------------------- 20
11.2.10 SD----------------------------------------------------------------------------------------------- 20
11.2.11 FO ---------------------------------------------------------------------------------------------- 20
11.3 Protections ------------------------------------------------------------------------------------------ 20
11.3.1 Fault Signal Output ------------------------------------------------------------------------- 21
11.3.2 Shutdown Signal Input --------------------------------------------------------------------- 21
11.3.3 Undervoltage Lockout for Power Supply (UVLO) ----------------------------------- 21
11.3.4 Overcurrent Limit (OCL) ----------------------------------------------------------------- 22
11.3.5 Overcurrent Protection (OCP) ----------------------------------------------------------- 23
11.3.6 Thermal S hutdown (TSD) ----------------------------------------------------------------- 23
12. Design Notes ---------------------------------------------------------------------------------------------- 24
12.1 PCB Pattern La yout ------------------------------------------------------------------------------ 24
12.2 Considerations in IC Characteristics Measure ment --------------------------------------- 24
13. Calculating Power Losses and Estimating Junction Temperature ---------------------------- 25
13.1 Power MOSFET ----------------------------------------------------------------------------------- 25
13.1.1 Power MOSFET Steady-state Loss, PRON----------------------------------------------- 25
13.1.2 Power MO S FET Switching Loss, PSW --------------------------------------------------- 26
13.1.3 Body D iode Steady-state Loss, PSD ------------------------------------------------------- 26
13.1.4 Estimating Junction Temper ature of Pow er MOSFET ------------------------------ 26
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14. Performance Curves ------------------------------------------------------------------------------------ 27
14.1 Transient Thermal Resistance Curves -------------------------------------------------------- 27
14.2 Performance Curves of Control Parts --------------------------------------------------------- 28
14.3 Performance Curves of Output Parts --------------------------------------------------------- 34
14.3.1 Output Transistor Perf o rmance Curves ------------------------------------------------ 34
14.3.2 Switching Losses ----------------------------------------------------------------------------- 35
14.4 Allowable Effective Current Curves ----------------------------------------------------------- 37
14.4.1 SX68001MH ---------------------------------------------------------------------------------- 37
14.4.2 SX68002MH ---------------------------------------------------------------------------------- 38
14.4.3 SX68003MH ---------------------------------------------------------------------------------- 39
15. Pattern Layout Example ------------------------------------------------------------------------------- 40
16. Typical Motor Dr iver Application ------------------------------------------------------------------- 42
Important Notes ---------------------------------------------------------------------------------------------- 43
SX6800xMH Series
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1. Absolute Maximum Ratings
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, COM1 = COM2 = COM.
Parameter Symbol Conditions Rating Unit Remarks
Main Supply Vo lta ge (DC) VDC VBBx–LS 200 V SX68001MH
400
SX68002MH
SX68003MH
Main Supply Vo lta ge
(Surge) VDC(SURGE) VBBx–LS 250 V SX68001MH
500
SX68002MH
SX68003MH
Power MOSFET
Breakdown Voltage VDSS
CC
D
250
V
SX68001MH
CC
D
500 SX68002MH
CC
D
500 SX68003MH
Logic Supply Voltage
VCC
20
V
VBS
VB2V, VB2V1;
20
Output C urrent (DC) (1) IO TC = 25 °C
2
A
SX68001MH
1.5 SX68002MH
2.5 SX68003MH
Output C urrent (Pul s e) IOP TC = 25 °C, PW 100 μs
3
A
SX68001MH
2.25 SX68002MH
3.75 SX68003MH
Regul ator Output C urrent IREG 35 mA
Input Voltage VIN HINx, LINx, FO, SD 0.5 to 7 V
Allowable Power
Dissipation
PD TC = 25 °C 3 W
Operating Case
Temperature
(2)
TC(OP) 20 to 100 °C
Junct ion Te mperature(3) TJ 150 °C
Storage Temperature TSTG 40 to 150 °C
(1) Should be derated depending on an actual case temperature. See Section 14.4.
(2) Refers to a case temperature measured during IC operation.
(3) Refers to the junction temperature of each chip built in t he I C, including the controller IC (M IC), transistors, and fast
recovery diodes.
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2. Recommended Operating Conditions
Unless specifically noted, COM1 = COM2 = COM.
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Main Supply Vo lta ge VDC VBBx–LS 140 200 V SX68001MH
VBBx–LS 300 400
SX68002MH
SX68003MH
Logic Supply Voltage
VCC
VCC1–COM1,
VCC2–COM2
13.5 16.5 V
VBS
VB1–U;
VB2–V, VB2V1;
VB31W1, VB32W1
13.5 16.5 V
Input Volta ge
(HINx, LINx, SD, FO)
VIN 0 5.5 V
Minimum Input Pul s e
Width
tIN(MIN)ON 0.5 μs
tIN(MIN)OFF 0.5 μs
Dead Time of Input Signal tDEAD 1.5 μs
FO P in Pull -up Resist or RFO 3.3 10
FO P in Pull -up Vo ltage VFO 3.0 5.5 V
FO Pin Noise Filter
Capacitor
CFO 0.001 0.01 μF
Bootstrap Capacitor CBOOT 1 μF
Shunt Resistor RS
IP 3 A 0.37
Ω
SX68001MH
IP 2.25 A 0.5 SX68002MH
IP 3.75 A 0.3 SX68003MH
RC Filter Resisto r RO 100 Ω
RC Filter Capacitor CO 1000 10000 pF
PWM Carrier Frequency fC 20 kHz
Operating Case
Temperature
TC(OP) 100 °C
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3. Electrical Characteristics
Current polarities are defined as follows: current going into the IC (sinking) is positive current (+); current coming
out of the IC (sourcing) is negative current (−).
Unless specifically noted, TA = 25 °C, VCC = 15 V, COM1 = COM2 = COM.
3.1 Characteristics of Control Parts
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Power Supply Ope r ation
Logic Operation Start
Voltage
VCC(ON)
VCC1–COM1,
VCC2–COM2
10.5 11.5 12.5 V
VBS(ON)
VB1U;
VB2V, VB2V1;
VB31W1, VB32W1
9.5 10.5 11.5 V
Logic Operation Stop
Voltage
VCC(OFF)
VCC1–COM1,
VCC2–COM2
10.0 11.0 12.0 V
VBS(OFF)
VB1U;
VB2V, VB2V1;
VB31W1, VB32W1
9.0 10.0 11.0 V
Logic S upp l y Cur r ent
ICC IREG = 0 A 4.6 8.5 mA
IBS
HINx = 5 V; VBx pin
current in 1-phase
operation
140 400 μA
Input Sig nal
High Level Inp ut
Thresho l d Vo ltage
(HINx, LINx, SD)
VIH O utput ON 2.0 2.5 V
Low Level Input
Thresho l d Vo ltage
(HINx, LINx, SD)
VIL Output OFF 1.0 1.5 V
FO P in High Level Input
Thresho l d Vo ltage
VIH(FO) Output O N 2.0 2.5 V
FO P in Low Level Input
Thresho l d Vo ltage
VIL(FO) Output O FF 1.0 1.5 V
High Level Inp ut Current
(HINx, LINx)
IIH VIN = 5 V 230 500 μA
Low Level Input Current
(HINx, LINx)
IIL VIN = 0 V 2 μA
Fault Signal Output
FO Pin Voltage at Fault
Signal Output
VFOL VFO = 5 V, RFO = 10 0 0.5 V
FO Pin Voltage in Normal
Operation
VFOH VFO = 5 V, RFO = 10 4.8 V
Protection
OCL Pin Outp ut Vo ltage
(L)
VOCL(L) 0 0.5 V
OCL Pin Output Voltage
(H)
VOCL(H) 4.5 5.5 V
Current Limit Reference
Voltage
VLIM 0.6175 0.6500 0.6825 V
OCP Thr eshold Vo l tage VTRIP 0.9 1.0 1.1 V
OCP Hold Time tP 20 25 μs
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Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
OCP Blanking Time tBK(OCP) 2 3.5 μs
Current Limit Blanking
Time
tBK(OCL) 2 3.5 μs
TS D Ope rating
Temperature
TDH
I
REG
= 0 mA; without
heatsink
135 150 165 °C
TSD Releasing
Temperature
TDL
I
REG
= 0 mA; without
heatsink
105 120 135 °C
Regulator Output Voltage VREG IREG = 0 mA to 35 mA 6.75 7.5 8.25 V
3.2 Bootstrap Diode Characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Bootstrap Diode Leakage
Current ILBD
VR = 250 V 10
μA
SX68001MH
VR = 500 V 10 SX68002MH
VR = 500 V 10 SX68003MH
Bootstrap Diode Forward
Voltage
VFB IFB = 0.15 A 1.0 1.3 V
Bootstrap Diode Series
Resistor
RBOOT 48 60 72 Ω
3.3 Thermal Resistance Characteristics
Parameter Symbol Conditions Min. Typ. Max. Unit Remarks
Junction-to-Case Thermal
Resistance
(1)
RJ-C
All power MOSFETs
operating
10 °C/W
Junction-to-Ambient
Thermal Resistance
RJ-A
All power MOSFETs
operating
35 °C/W
(1) Refers to a case temperature at the measurement point de scribed in Figure 3-1. Mounted on a CEM-3 glass (1.6 mm
in thickness, 35 μm in copper foil thickness), and measured under natural air cooling without silicone potting.
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Measurement point
4 mm
17
1
18
27
7.66 mm
Figure 3-1. Case Temperature Measurement Point
3.4 Transistor Characteristics
Figure 3-2 p rovides the definitions of switc hin g characteristics describe d in this and the following sections.
HINx/
LINx
ID / IC
10%
0
VDS /
VCE
td(on)
0
0
90%
tr
ton
trr
td(off)tf
toff
Figure 3-2. Switching Characteristics De finitions
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3.4.1 SX68001MH
Parameter Symbol Conditions Min. Typ. Max. Unit
Drain-to-Sourc e Lea kage Curr ent IDSS VDS = 250 V, VIN = 0 V 100 µA
Drain-to-Source On-resistance RDS(ON) ID = 1.0 A, VIN = 5 V 1.25 1.5 Ω
Source-to-Drain Diode Forward
Voltage
VSD ISD =1.0 A, VIN = 0 V 1.1 1.5 V
High-side Switching
Source-to-Drai n Diode Reverse
Recovery Time
trr VDC = 150 V,
VCC = 15 V,
ID = 1.0 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive l oad
75 ns
Turn-on Del ay Time td(on) 800 ns
Rise Time tr 45 ns
Turn-off Delay Time td(off) 720 ns
Fall Time tf 40 ns
Low-side Switc hi ng
Source-to-Drai n Diode Reverse
Recovery Time
trr VDC = 150 V,
VCC = 15 V,
ID = 1.0 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive l oad
70 ns
Turn-on Delay Time td(on) 750 ns
Rise Time tr 50 ns
Turn-off Delay Time td(off) 660 ns
Fall Time tf 20 ns
3.4.2 SX68002MH
Parameter Symbol Conditions Min. Typ. Max. Unit
Drain-to-Sourc e Lea kage Curr ent IDSS VDS = 500 V, VIN = 0 V 100 µA
Drain-to-Source On-resistance RDS(ON) ID = 0.75 A, VIN = 5 V 3.2 4.0 Ω
Source-to-Drain Diode Forward
Voltage
VSD ISD = 0.75 A, VIN = 0 V 1.0 1.5 V
High-side Switching
Source-to-Drai n Diode Reverse
Recovery Time
trr VDC = 300 V,
VCC = 15 V,
ID = 0.75 A,
VIN = 05 V or 50 V,
TJ = 25 °C,
inductive l oad
120 ns
Turn-on Dela y Time td(on) 810 ns
Rise Time tr 60 ns
Turn-off Delay Time td(off) 815 ns
Fall Time tf 40 ns
Low-side Switc hi ng
Source-to-Drai n Diode Reverse
Recovery Time
trr VDC = 300 V,
VCC = 15 V,
ID = 0.75 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive l oad
110 ns
Turn-on Del ay Time td(on) 760 ns
Rise Time tr 60 ns
Turn-off Delay Time td(off) 750 ns
Fall Time tf 30 ns
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3.4.3 SX68003MH
Parameter Symbol Conditions Min. Typ. Max. Unit
Drain-to-Source Leakage Current IDSS VDS = 500 V, VIN = 0 V 100 µA
Drain-to-Source On-resistance RDS(ON) ID = 1.25 A, VIN = 5 V 2.0 2.4 Ω
Source-to-Drain Diode Forward
Voltage
VSD ISD =1.25 A, VIN = 0 V 1.0 1.5 V
High-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr VDC = 300 V,
VCC = 15 V,
ID = 1.5 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive l oad
135 ns
Turn-on Del ay Time td(on) 940 ns
Rise Time tr 100 ns
Turn-off Delay Time td(off) 975 ns
Fall Time tf 45 ns
Low-side Switching
Source-to-Drain Diode Reverse
Recovery Time
trr VDC = 300 V,
VCC = 15 V,
ID = 1.5 A,
VIN = 0→5 V or 5→0 V,
TJ = 25 °C,
inductive l oad
135 ns
Turn-on Del ay Time td(on) 900 ns
Rise Time tr 105 ns
Turn-off Delay Time td(off) 905 ns
Fall Time tf 35 ns
4. Mechanical Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Unit
Remarks
Package Weight 1.4 g
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5. Truth Table
Table 5-1 is a truth table that pr ovides the logic level d e fi nitions of operation modes.
In the case where HINx and LINx signals in each phase are high at the same time, both the high- and low-side
transistors become on (simultaneous on-state). Therefore, HINx and LINx signals, the input signals for the HINx and
LIN x pins, require dea d time setting so tha t such a simulta neous on-state event can be avoided.
After the IC recovers from a UVLO_VCC condition, the low-side transistors resume switching in accordance with
the input logic levels of the LINx signals (level-triggered), whereas the high-side transistors resume switching at the
next rising edge of an HINx signal (edge-triggered).
After the IC recovers from a UVLO_VB condition, the high-side transis tors resume switching at the next ri sing ed ge
of an HIN x signal (edge-triggered).
Table 5-1. Truth Table for Operation Modes
Mode
HINx
LINx
High-side Tra nsi st or
Low-side Transistor
Normal Operation
L
L
OFF
OFF
H
L
ON
OFF
L
H
OFF
ON
H
H
ON
ON
Shutdown Signal Input
FO = “L”
L L OFF OFF
H
L
ON
OFF
L
H
OFF
OFF
H
H
ON
OFF
Undervoltage Lockout for High-
side Power Supply (UVLO_VB)
L
L
OFF
OFF
H
L
OFF
OFF
L
H
OFF
ON
H
H
OFF
ON
Unde rvolt age Lockout for Low-
side Power Supply (UVLO_VCC)
L
L
OFF
OFF
H
L
OFF
OFF
L H OFF OFF
H
H
OFF
OFF
Overcurrent Protection (OCP)
L
L
OFF
OFF
H
L
ON
OFF
L
H
OFF
OFF
H
H
ON
OFF
Overcurrent Limit (OCL)
(OCL = SD)
L
L
OFF
OFF
H
L
OFF
OFF
L
H
OFF
ON
H
H
OFF
ON
Thermal S hutdown (TSD)
L L OFF OFF
H
L
ON
OFF
L
H
OFF
OFF
H H ON OFF
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6. Block Diagram
SD
VCC1
VB32
VB1
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB1
V2
Low
Side
Driver
Input
Logic
VB31
LS
UVLO UVLO UVLOUVLO
OCP and OCL
Input Logic
(OCP reset )
UVLO
16
15
14
12
11
10
9
8
7
6
5
4
3
25
21
24
23
22
20
19
18
17
VB2
V
1
2
High Side
Level Shift Dr iver
27
VBB2
26
REG 13
Thermal
Shutdown
REG
OCP
Figure 6-1. SX6800xMH Block Diagram
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7. Pin Configuration Definitions
Top view
Pin Number
Pin Name
Description
1
VB2
V-phas e high-side floating supply voltage input
2
V
V-phase bootstrap capacitor connection
3
VCC1
High-side logic supply voltage input
4
COM1
High-side logic gr ound
5
HIN3
Logic input for W-phase high-side gate driver
6
HIN2
Logic input for V-p has e hig h -side gate driver
7
HIN1
Logic input for U-p has e hig h -side gate driver
8
SD
High-side shutdown si gnal input
9
OCL
Overcurrent limit signal input
10
LIN3
Logic input for W-phase l ow-side gate driver
11
LIN2
Logic input for V-phase low-side gate driver
12
LIN1
Logic input for U-phase low-side gate driver
13
REG
Regulator output
14
COM2
Low-side logic ground
15
VCC2
Low-side l ogic supply voltage inp ut
16
FO
Fault signal output and shutdown signal input
17
LS
Power MOSFET source
18
W2
W-phase output (connected to W1 externally)
19
V2
V-phase output (connected to V1 externally)
20
U
U-phase output
21
VB1
U-phas e high-side floating supply voltage input
22
VBB1
Positive DC bus supply voltage (connected to VBB2 externally)
23
V1
V-phase output (connected to V2 e xterna lly)
24
W1
W-phase output (connected to W2 externally)
25
VB31
W-phase hig h -side floating supply voltage input
26
VBB2
Positive DC bus supply voltage (connected to VBB1 externally)
27
VB32
W-phase hig h -side floating supply voltage input
27
1
17
18
1
17
27
18
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8. Typical Application
CR filters and Zener diodes should be added to your application as needed. This is to protect each pin against surge
voltages causing malfunctions, and to avoid the IC being used under the conditions exceeding the absolute maximum
ratings where critical damage is inevitable. Then, check all the pins thoroughly under actual operating conditions to
ensure that your a pplication w orks flawlessly.
SD
VCC1
VB31
VB1
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN1
HIN2
HIN3
OCL
W1
V1
VBB1
V2
V
VB2
VB32
CFO
5 V
RFO
VCC
Controller         
CBOOT1
CBOOT3
CBOOT2
M
CDC
CS
VDC
MIC
16
15
14
12
11
10
8
7
6
5
4
3
1
2
27
22
25
20
19
HIN 1
HIN 2
HIN 3
LIN1
LIN2
LIN3
Fault
GND
9
A/D
REG 13
VBB2
26
GND
A/D
17
LS
RS
RO
CO
REG
21
24
18
23
Figure 8-1. SX6800xMH Typical Application
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9. Physical Dimensions
SOP27 Package
14.1 ±0.3
11.4 ±0.2
1.05 ±0.2
22 ±0.2
0.4
+0.15
-0.05
0.25
+0.15
-0.05
2.1 ±0.2
A
18
27
117
P=1.2 ±0.2
0.8 ±0.2 0~0.2
(R-end)
0.7 ±0.3
(Excludes mold flash)
(Includesmold flash)
0to8°
(From backside to root of pin)
NOTES:
- Dimensions i n millimeters
- Bare lead frame: Pb-free (RoHS compliant)
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Land Pattern Example
1.75
13.32
1.75
16.82
0.8
1.6 0.4
1.6 0.4
0
0.6
1.8
3
4.2
5.4
6.6
9
10.2
0.6
1.8
3
4.2
5.4
6.6
7.8
9
10.2
10.2
7.8
5.4
4.2
1.8
0.6
4.2
5.4
7.8
10.2
Pin 27
Pin 18
Pin 1
Pin 17
10. Marking Diagram
117
Par t Number
L ot Number :
Y is the last d igit of the y ea r o f manufacture (0 to 9)
M is t he month of the year (1 to 9, O, N, or D)
DD is the da y of the month (01 to 31)
X is the contr ol number
S M 6 8 0 0 x M H
1827
Y M D D X
Unit: mm
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11. Functional Descriptions
Unless specifically noted, this section uses the
following defi nitions:
All the characteristic values given in this section are
typical values.
For pin and peripheral component descriptions, this
section employs a notation system that denotes a pin
name with the arbitrary letter “x”, depending on
context. Thus, “the VCCx pin” is used when referring
to either or both of the VCC1 and VCC2 pins.
The COM1 pin is always connected to the COM2 pin.
11.1 Turning On and Off the IC
The procedures listed below provide recommended
startup and shutdown sequences. To turn on the IC
properly, do not apply any voltage on the VBBx, HINx,
and LI Nx pins until the VC Cx pi n volta ge has r eached a
stable state (VCC(ON) 12.5 V).
It is required to fully charge bootstrap capacitors,
CBOOTx, at startup (see Section 11.2.2).
To turn off the IC, set the HINx and LINx pins to
logic low (or “L”), and then decrease the VCCx pin
voltage.
11.2 Pin Descriptions
11.2.1 U, V, V1, V2, W1, and W2
These pins are the outputs of the three phases, and
serve as the connection terminals to the 3-phase motor.
The V1 and W1 pins must be connected to the V2 and
W2 pins on a PCB, respectively.
The U, V (V1), and W1 pins are the grounds for the
VB1, VB2, and VB31 pins.
The U, V, and W1 pins are connected to the negative
nodes of bootstrap capacitors, CBOOTx. The V pin is
internall y co nnected to the V1 pin.
Since high voltages are applied to these output pins
(U, V, V1, V2, W1, and W2), it is required to take
measures for insulating as follows:
Keep enough distance between the output pins and
low-voltage traces.
Coat the output p ins with insulating resin.
11.2.2 VB1, VB2, VB31, and VB32
These pins are connected to bootstrap capacitors for
the high-side floating supply.
In actual applica tions, use either of the VB31 or VB32
pin because they are internally connected.
Voltages across the VBx and these output pins shoul d
be maintained within the recommended range (i.e., the
Logic Supply Voltage, VBS) given in Section 2.
A bootstrap capacitor, CBOOTx, should be connected i n
each of the traces between the VB1 and U pins, the VB2
and V pins, the VB31 (VB32) and W1 pins.
For proper st artup, turn on the low-side transistor first,
then fully charge the bootstrap capacitor, CBOOTx.
For the capacitance of the bootstrap capacitors,
CBOOTx, choose the values that satisfy Equations (1) and
(2). Note that capacitance tolerance and DC bias
characteristics must be taken into account when you
choose appropriate values for CBOOTx.
C(F)>800 × t()
(1)
1 FC 220 F
(2)
In Eq uat io n (1), let tL(OFF) be th e max i mu m o ff -ti me o f
the low-side transistor (i.e., the non-charging time of
CBOOTx), me asured in seconds.
Even while the high-side transistor is off, voltage
across the bootstrap capacitor keeps decreasing due to
power dissipation in the IC. When the VBx pin voltage
decreases to VBS(OFF) or less, the high-side undervoltage
lockout (UVLO_VB) starts operating (see Section
11.3.3.1). Therefore, actual board checking should be
done thoroughly to validate that voltage across t he VBx
pin maintain s over 11.0 V (VBS > VBS(OFF)) dur i n g a low-
frequency operation such as a startup period.
As Figure 11-1 shows, a bootstrap diode, DBOOTx, and
a current-limiting resistor, RBOOTx, are internally placed
in series between the VCC1 and VBx pins. Time
constant for the charging time of CBOOTx, τ, can be
computed by Equation (3):
= C × R ,
(3)
where CBOOTx is the optimized capacitance of the
bootstrap capacitor, and RBOOTx is the resistance of the
current-limiting resistor (60 Ω ± 20%).
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VCC1
VB1
VB31
W2
U
COM2
VCC2
COM1
W1
V1
VBB1
V
VB2
V
CC
C
BOOT1
C
BOOT3
C
BOOT2
M
MIC
15
14
4
3
25
24
23
22
22
20
18
1
2
HO1
HO2
HO3
D
BOOT1
D
BOOT2
D
BOOT3
R
BOOT1
R
BOOT2
R
BOOT3
V
DC
VBB2
26
Figure 11-1. Bootstrap Circuit
Figure 11-2 shows an i nternal level-shiftin g circuit. A
high-side output signal, HOx, is generated according to
an input signal on the HINx pin. When an input signal
on the HINx pin transits from low to high (rising edge),
a “Se t” signa l is gene rated. When the HINx i nput si gnal
transits from high to low (falling edge), a “Reset” signal
is generated. These two signals are then transmitted to
the hi gh -side b y the level-shift i ng circui t and are input to
the SR flip-flop circuit. Finally, the SR flip-flop circuit
feed s an o ut put s ignal , Q (i.e., HOx) .
Figure 11-3 is a timing diagram describing how noise
or other detr imental effects will i mprop erly influence t he
level-shifting process. When a noise-induced rapid
volta ge dr op bet ween the V Bx a nd out put p ins (U , V/V 1
or W1; hereafter “VBxHSx”) occurs after the Set signal
generation, the next Reset signal cannot be sent to the
SR flip-flop circ uit. And the st ate of an HOx signal sta ys
logic high (or “H”) because the SR flip-flop does not
respond. With the HOx state being held high (i.e., the
high-side transistor is in an on-state), the next LINx
signal turns on the low-side transistor and causes a
simultaneously-on condition, which may result in
critical da mage to the IC. T o pro tect the VB x pin against
such a noise effect, add a bootstrap capacitor, CBOOTx, in
each phase. CBOOTx must be placed near the IC, and be
connected between the VBx and HSx pins with a
minimal length of traces. To use an electrolytic capacitor,
add a 0.01 μF to 0.1 μF bypass capacitor, CPx, in paralle l
near these pins used for the same phase.
HINx Input
logic Pulse
generator
COM1
Set
Reset
HOx
VBx
HSx
S
R
Q
U1
4
Figure 11-2. Internal Level-shi ft ing C ircuit
HINx
Set
Reset
VBxHSx
Q
0
V
BS(OFF)
0
0
0
0
V
BS(ON)
Stays logic high
Figure 11-3. Waveforms at VBx-HSx Vo lta ge Drop
11.2.3 VCC1 and VCC2
These are the power supply pins for the built-in
control IC. The VCC1 and VCC2 pins must be
externally connected on a PCB because they are not
internally connected. To pr e vent ma l fu nct io n ind uce d by
supply ripples or other factors, put a 0.01 μF to 0.1 μF
ceramic capacitor, CVCC, near these pins. To prevent
damage caused by surge voltages, put an 18 V to 20 V
Zener diode , DZ, between the VCCx and C OMx pins.
Voltages to be applied between the VCCx and COMx
pins should be regulated within the recommended
operational range of VCC, given in Sect io n 2.
VCC1
COM2
VCC2
COM1
VCC MIC
15
14
4
3
CVCC
DZ
Figure 11-4. VCCx Pin Perip heral C i rcuit
11.2.4 COM1 and COM2
These are the logic ground pins for the built-in c o ntr ol
IC. The COM1 and COM2 pins should be connected
externally on a PCB because they are not internally
connected. Varying electric p ote ntial of the lo gic ground
can be a cause of improper operations. Therefore,
connect the logic ground as close and short as possible
to shunt resistors, RS, at a single-point ground (or star
ground) which is separated from the power ground (see
Figure 11-5).
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COM1
VBB1
LS
COM2
V
DC
R
S
C
DC
C
S
17
22
4
14
Cr eate a singl e-point
ground (a star ground)
near R
S
, but ke e p i t
separ ated f ro m the
p owe r gr ou nd.
Connect COM 1 a n d COM 2
on a PCB.
U1
L ogic ground
VBB2
26
Figure 11-5. Connections to Lo gi c Ground
11.2.5 REG
This is the 7.5 V regulator output pin, which can be
used for a power supply of an external logic IC (e.g.,
hall-effect IC). The pin has a maximum o ut put cur rent of
35 mA. T o stabilize the REG pin output, c onnect t he pin
to a capacitor of about 0.1 μF.
11.2.6 HIN1, HIN2, and HIN3;
LIN1, LIN2, and LIN3
These are the input pins of the internal motor drivers
for each phase. The HINx pin acts as a high-side
controller ; the LINx pin acts as a low-side contro lle r.
Figure 11-6 shows an internal circuit diagram of the
HINx or LINx pin. This is a CMOS Schmitt trigger
circuit with a built-in 20 pull-down resistor, and its
input logic is active high.
Input signals a pplied across the HINxC OMx and t he
LINxCOM x p ins in ea ch p ha s e should b e s et wit hi n th e
ranges provided in Table 11-1, below. Note that dead
time setting must be done for HINx and LINx signals
because the IC does not have a dead time generator.
The higher PWM carrier frequency rises, the more
switching loss increases. Hence, the PWM carrier
frequency must be set so that operational case
temperatures and junction temperatures have sufficient
margins against the absolute maximum ranges, specified
in Section 1.
If the signals from the microcontroller become
unstable, the IC may result in malfunctions. To avoid
this event, the outputs from the microcontroller output
line should not be high impedance. Also, if the traces
from the microcontroller to the HINx or LINx pin (or
both) are too long, the traces ma y be interfered by noise.
Therefore, it is recommended to add an additional filter
or a pull-down resistor near the HINx or LINx pin as
needed (see Figure 11-7).
Here are filter circuit constants for reference:
RIN1x: 33 Ω to 100 Ω
RIN2x: 1 to 10
CINx: 100 pF to 1000 pF
Care should be taken when adding RIN1x and RIN2x to
the traces. When they are connected each other, the
input voltage of the HINx and LINx pins becomes
slightly lower than the output voltage of the
microcontroller.
Table 11-1. Input Signals for HINx and LINx Pins
Parameter High Level Sig nal Low Level Signal
Input
Voltage
3 V < VIN < 5.5 V 0 V < VIN < 0.5 V
Input Pulse
Width
≥0.5 μs ≥0.5 μs
PWM
Carrier
Frequency
20 kHz
Dead Time ≥1.5 μs
HINx
(LINx)
COM1
(COM2)
5 V
2 kΩ
20 kΩ
U1
2 kΩ
Figure 11-6. Internal Circuit Diagram of HINx or
LINx Pin
R
IN1x
R
IN2x
C
INx
U1
Input
signal
Controller
HINx/
LINx
SX6800xMH
Figure 11-7. Filter Circuit for HINx or LINx Pin
11.2.7 VBB1 and VBB2
These are the input pins for the main supply voltage,
i.e., the positive DC bus. All of the power MOSFET
drains of the high-side are connected to these pins.
Voltages between the VBBx and COM2 pins should be
set within the recommended range of the main supply
voltage, V DC, given in Sectio n 2.
The VBB1 and VBB2 pins should be connected
externally on a PCB. To suppress surge voltages, put a
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0.01 μF to 0.1 μF bypass capacitor, CS, near the VBBx
pin and an electrolytic capacitor, CDC, with a minimal
length of PCB traces to the VB Bx pin.
11.2.8 LS
This pin is internally connected to the power
MOSFET source in each phase and the overcurrent
protection (OCP) circuit. For current detection, the LS
pin should be connected externally on a PCB via a shunt
resistor, RS, to the C OMx pin.
For more details on the OCP, see Section 11.3.5.
When connecting a shunt resistor, place it as near as
possible to the IC with a minimum length of tra c es to the
LS and COMx pins. Otherwise, malfunction may occur
because a longer circuit trace increases its inductance
and thus increases its susceptibility to improper
operations. In applications where long PCB traces are
required, add a fast recovery diode, DRS, between the LS
and COMx pins in order to prevent the IC from
malfunctioning.
COM1
VBB1
LS
COM2
V
DC
R
S
C
DC
C
S
17
22
4
14
P ut a shunt r es istor near
the IC with a minimum
length to the LS pin.
Add a fas t re covery
diode to a long tr a c e.
D
RS
U1 VBB2
26
Figure 11-8. Connectio ns to LS Pin
11.2.9 OCL
The OCL pin serves as the output of the overcurrent
protections which monitor the currents going through
the output transistors. In normal operation, the OCL pin
logic level is low. If the OCL pin is connected to the SD
pin so that the SD pin will respond to an OCL output
signal, the high-side transistors can be turned off when
the protections (OCP and OCL) are activated.
11.2.10 SD
When a 5 V o r 3 .3 V signal i s inp ut to the SD pi n, t he
high-side transi stor s turn o ff ind epend ently of any HINx
signals. This is because the SD pin does not respond to a
pulse shorter than an internal filter of 3.3 μs (typ.).
The SDOCL pin connection, as described in Section
11.2.9, allows the IC to turn o ff the hig h-side transi stors
at OCL or OCP activation. Also, inputting the inverted
signal of the FO pin to the SD pin permits all the high-
and low-side transistors to turn off, when the IC detects
an abnormal condition (i.e., some or all of the
protections such as TSD, OCP, and UVLO are activated).
11.2.11 FO
This pin operates as the fault signal output and the
low-side shutdown signal input. Sections 11.3.1 and
11.3.2 explain the two functions in detail, respectively.
Figure 11-9 illustrates an internal circuit diagram of the
FO pin and its pe ripheral circuit.
5 V
50 Ω
2 kΩ1 MΩ
Blanking
filter
Output SW turn-off
a nd Q
FO
turn-on
Q
FO
3.0 µs (typ.)
V
FO
C
FO
INT
R
FO
U1
FO
COM
Figure 11-9. Internal Circu it Diagra m of FO Pin and
Its Peripheral Circuit
Because of its open-collector nature, the FO pin
should be tied by a pull-up resistor, RFO, to the external
power supply. The external power supply voltage (i.e.,
the FO Pin Pull-up Voltage, VFO) should range from
3.0 V to 5.5 V.
When the pull-up resistor, RFO, has a too small
resistance, the FO pin voltage at fault signal output
becomes high due to the saturation voltage drop of a
built-in transistor, QFO. Therefore, it is recommended to
use a 3.3 kΩ to 10 kΩ pull-up resistor.
To suppress noise, add a filter capacitor, CFO, near the
IC with minimizing a trace length between the FO and
COMx pins.
To avoid the repetition of OCP activations, the
external microcontroller must shut off any input signals
to the I C withi n a n OCP ho ld t i me, tP, which o c cur s after
the internal MOSFET (QFO) turn-on. tP is 20 μs where
minimum values of thermal characteristics are taken into
account. (For more details, see Section 11.3.5.) Our
recommendation is to use a 0.001 μF to 0.01 μF filter
capacitor.
11.3 Protections
This section describes the various protection circuits
provided in the SX6800xMH series. The protection
circuits include the undervoltage lockout for power
supplies (UVLO), the overcurrent protection (OCP), and
the the rmal sh ut down (TSD).
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In case one or more of these protection circuits are
activated, the FO pin outputs a fault signal; as a result,
the external microcontroller can stop the operations of
the three phases by receiving the fault signal. The
external microcontroller can also shut down the IC
operations by input ting a fault signal to the FO p in.
In the following functional descriptions, “HOx”
denotes a gate input signal on the high-side transistor,
whereas “LOx” denotes a gate input signal on the low-
side transistor. VBxHSx” refers to the voltages
between the VBx pin and output pins (U, V/V1, and
W1).
11.3.1 Fault Signal Output
In case one or more of the following protections are
actuated, an internal transistor, QFO, turns on, then the
FO pin becomes logic low (≤0.5 V).
Low-side undervoltage lockout (UVLO_VCC)
Overcurrent protection (OCP)
Thermal shutdown (TSD)
While the FO pin is in the low state, all the low-side
transistors turn off. In normal operation, the FO pin
outputs a high signal of 5 V. OCP The fault signal
output time of the FO pin at OCP activation is the OCP
hold time (tP) of 25 μs (typ.), fixed by a built-in feature
of the IC itself (see Section 11.3.5). The external
microcontroller receives the fault signals with its
interrupt pin (INT), and must be programmed to put the
HINx and LINx pins to logic low within the
predetermined OCP hold time, tP.
11.3.2 Shutdo wn Signa l Input
The FO pin also acts as the input pin of shutdown
signals. When the FO pin becomes logic low, all the
low-side transistors turn off. The voltages and pulse
widths of the shutdown signals to be applied between
the FO and C OMx pins are listed in Table 11-2.
Table 11-2. Shutdown Signals
Parameter
High Level Sig nal
Low Level Signal
Input
Voltage
3 V < VIN < 5.5 V 0 V < VIN < 0.5 V
Input
Pulse
Width
6 μs
11.3.3 Undervoltage Lockout for Power
Supply (UVLO)
In case the gate-driving voltages of the output
transistors decrease, their steady-state power dissipa tions
increase. This overheating condition may cause
permanent damage to the IC in the worst case. To
prevent this event, the SX6800xMH series has the
undervoltage lockout (UVLO) circuits for both of the
high- and low-side power supplies in the monolithic IC
(MIC).
11.3.3.1. Undervoltage Lockout for High-
side Power Supply (UVLO_VB)
Figure 11-10 shows operational waveforms of the
undervoltage lockout operation for high-side power
supply (i.e., UVLO_VB).
When the voltage between the VBx and output pins
(VBxHSx) decreases to the Logic Operation Stop
Voltage (VBS(OFF), 10.0 V) o r less, the UVLO_VB circuit
in the corresponding phase gets activated and sets an
HOx signal to lo gic low.
When the voltage between the VBx and HSx pins
increases to the Logic Operation Start Voltage (VBS(ON),
10.5 V) or more, the IC releases the UVLO_VB
operation. Then, the HOx signal becomes logic high at
the rising edge of the first input command after the
UVLO_VB release.
Any fault signals are not output from the VFO pin
during the UVLO_VB operation. In addition, the VBx
pin has an internal UVLO_VB filter of about 3 μs, in
order to prevent noise-induc ed mal func tions.
LINx
HINx
VBx-HSx
HOx
LOx
FO
VBS(OFF)VBS(ON)
N o F O output at UVLO _VB.
0
0
0
0
0
0
UV LO rele ase
UVLO_VB
operation
About 3 µs
HO x restar ts at
p osi tiv e edge after
UVLO_VB release.
Figure 11-10. UVLO_VB Operational Waveforms
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11.3.3.2. Undervoltage Lockout for Low-
side Power Supply (UVLO_VCC)
Figure 11-11 shows operational waveforms of the
undervoltage lockout operation for low-side power
supply (i.e., UVLO_VCC).
When the VCC2 pin voltage decreases to the Logic
Operation Stop Voltage (VCC(OFF), 11.0 V) or less, the
UVLO_VCC circuit in the corresponding phase gets
acti vated a nd set s bo th of HO x and LOx s ignal s to lo gic
low. Whe n the VCC2 pi n volta ge incre ases to t he Log ic
Operation Start Voltage (VCC(ON), 11.5 V) or more, the
IC releases the UVLO_VCC operation.
Then, the IC resumes the following transmissions: an
LOx signa l according to a n LI Nx pin input comma nd; an
HOx signal according to the rising edge of the first
HINx p in inp ut co mma nd aft er the UVLO_VCC release.
During the UVLO_VCC operation, the FO pin becomes
logic low and sends fault signals.
In addition, the VCC2 pin has an internal
UVLO_VCC filter of about 3 μs, in order to prevent
noise-ind uce d mal functio ns.
About 3 µs
LINx
HINx
VCC2
HOx
LOx
FO
VCC(OFF)VCC(ON)
LOx responds to input signal.
0
0
0
0
0
0
UVLO_VCC
operation
Figure 11-11. UVLO_VCC Operational Waveforms
11.3.4 Overcurrent Limit (OCL)
The overcurrent limit (OCL) is a protection against
relatively low overcurrent conditio ns.
Figure 11-12 shows an internal circuit of the OCL
pin; Figure 11-13 shows OCL operational wa veforms.
When the LS pin voltage increases to the Current
Limit Reference Voltage (VLIM, 0.6500 V) or more, and
remains in this condition for a period of the Current
Limit Blanking T ime (tBK(OCP), 2 μs) or longer, the OCL
circuit is activated. Then, the O CL pin goes logic high.
During the O CL opera tion, the gate log ic levels of the
low-side transistors respond to an input command on the
LIN x pin.
To turn off the high-side transistors during the OCL
operation, connect the OCL and SD pins on a PCB. The
SD pin has an internal filter of about 3.3 μs (typ.).
When t he LS p in volta ge falls b elo w VLIM (0.6500 V),
the OCL pin logic level becomes low.
After the OCL pin logic has become low, the high-
side transistors remain turned off until the first low-to-
high transition on an HINx input signal occurs (i.e.,
edge-triggered).
LS
COM2
200 kΩ
U1
2 kΩ
17
14
OCL
0.65 VFilter
200 kΩ
2 kΩ
9
Figure 11-12. Internal Circuit Diagram of OCL Pin
LINx
HINx
LS
HOx
LOx
OCL
(SD)
V
LIM
0
0
0
0
0
0
t
BK(OCP)
3.3 µs (typ.)
HO x restar ts at pos itive
edge after OCL r elease.
Figure 11-13. OCL Operational Waveforms
(OCL = SD)
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11.3.5 Overcurrent Protection (OCP)
The overcurrent protection (OCP) is a protection
against large inrush currents (i.e., high di/dt). Figure
11-14 is an internal circuit diagram describing the LS
pin and its peripheral circuit. The OCP circuit, which is
connected to the LS pin, detects overcurrents with
voltage across a n exte rnal sh unt resistor, RS. Because the
LS pin is internally pulled down, the LS pin voltage
increases proportionally to a rise in the current running
thro ugh the shunt resistor, RS.
VBB1
COM
COM2
R
S
D
RS
V
TRIP
200 kΩBlanking
filter
Output SW turn-off
a nd Q
FO
turn-on
-
+
1.65 µs (typ.)
17
22
U1
2 kΩ
14 LS
Figure 11-14. Internal Circuit Diagram of OCP Pin
and Its Per ipheral Circuit
Figure 11-15 is a timing chart that represents
operation waveforms during OCP operation. When the
LS pin voltage increases to the OCP Threshold Voltage
(VTRIP, 1.0 V) or more, and remains in this condition for
a period of the OCP Blanking T ime (tBK, 2 μs) or longer,
the OCP circuit is activated.
The enabled OCP circuit shuts off the low-side
transistors, a nd puts the FO pin into a low state.
Then, output current decreases as a result of the
output transistors turn-off. Even if the OCP pin voltage
falls below VTRIP, the IC holds the FO pin in the low
state for a fixed OCP hold time (tP) o f 25 μs (typ.). Then,
the output trans istors opera te a c c ording to input signals.
The OCP is used for detecting abnormal conditions,
such a s an o utput tran sistor shorted. In case short-circuit
conditions occur repeatedly, the o utput transistors can be
destroyed. To prevent such event, motor operation must
be controlled by the external microcontroller so that it
can immediately stop the motor when fault signals are
detected. To resume IC operations thereafter, set the IC
to be resumed after a lapse of ≥2 seconds.
For proper shunt resistor setting, your application
must meet the following:
Use the shunt resistor that has a recommended
resistance, RS (see Section 2).
Set the LS pin input voltage to vary within the rated
LS pin voltages , VLS (see Section 1).
Keep the current through the output transistors belo w
the rated output current (puls e), IOP (see Section 1).
It is required to use a resistor with low internal
inductance because high-frequency switching current
will flow through the shunt resistor, RS. In addition,
choose a resistor with allowable power dissipation
according to your application.
Note that overcurrents are undetectable when one or
more of the U, V/V 1/V2, and W1/W 2 pins or their traces
are shorted to ground (ground fault). In case any of these
pins falls into a state of ground fault, the output
transistors may be destroyed.
LINx
HINx
HOx
LOx
FO
0
0
0
0
0
LS
VTRIP
tBK tBK
tP
tBK
HOx responds to input signal.
FO restarts
aut omatically af ter tP.
0
Figure 11-15. OCP Operational Waveforms
11.3.6 Thermal Shutdown (TSD)
The SX6800xMH series incorporates a thermal
shutdown (TSD) circuit. Figure 11-16 shows TSD
operational waveforms. In case of overheating (e.g.,
increased power dissipation due to overload, a rise in
ambient temperature at the device, etc.), the IC shuts
down the low-side outp ut transistors.
The T SD circuit in the monolithic I C (MIC) monitors
temperatures (see Section 6). When the temperature of
the monolithic IC (MIC) exceeds the TSD Operating
Temperature (TDH, 150 °C), the TSD circuit is activated.
When the temperature of the monolithic IC (MIC)
decreases to the TSD Releasing Temperature (TDL,
120 °C) or less, the shutdown operation is released. The
transistors then resume operating according to input
signals. During the TSD operation, the FO pin becomes
logic low and transmits fault signals. Note that junction
tempe ratur es of t he outp ut tr ansi stors t hemse lves a re not
monitored; therefore, do not use the TSD function as a n
overte mperature p revention for the output transi s tors.
SX6800xMH Series
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© SANKEN ELECTRIC CO., LTD. 2013
LINx
HINx
Tj(MIC)
HOx
LOx
FO
LOx responds to input signal.
TDH
TDL
0
0
0
0
0
0
TSD opera tion
Figure 11-16. TSD Operational Waveforms
12. Design Notes
12.1 PCB Pattern Layout
Figure 12-1 shows a schematic diagram of a motor
driver circuit. The motor driver circuit consists of
curr ent pat hs havi ng hig h freq uencie s and hi gh volt ages,
which also bring about negative influences on IC
operation, noise interference, and power dissipation.
Therefore, PCB trace layout s and component placements
play a n important role in circuit designing.
Current loops, which have high frequencies and high
voltages, should be as small and wide as possible, in
order to maintain a low-impedance state. In addition,
ground traces should be as wide and short as possible so
that radiated EMI levels can be reduced.
M
V
DC
High-frequency, high-voltage
current loops should be as
small and wide as possible.
Ground traces
should be wide
and short.
W1
V1
VBB1
W2
V2
22
U
20
LS
19
18
MIC
24
17
23
VBB2
26
Figure 12-1. High-frequency, High-vo lta ge Curr e nt
Paths
12.2 Considerations in IC Characteristics
Measurement
When measuring the breakdown voltage or leakage
current of the transis tors inco rpo rate d in the IC, note that
the gate and emitter (source) of each transistor should
have the same potential. Moreover, care should be taken
when performing the measurements, because each
transistor is connected as follows:
All the high-side transistors (drains) are internally
connected to the VBBx pin.
In the U-phase, the high-side transistor (source) and
the low-side toransistor (drain) are internally
connected, and are also connected to the U pin.
(In the V- and W-phases, the high- and low-side
transistors are unconnected inside the IC.)
The gates of t he high -side transistors are pulled down
to the corresponding output (U, V/V1, and W1) pins;
similarly, the gates of the low-side transistors are pulled
down to the COM2 pin.
When measuring the breakdown voltage or leakage
current of the transistors, note that all of the output (U,
V/V1/V2, and W1/W2), LS, and COMx pins must be
appropriately connected. Otherwise the switching
trans istors may result in permanent damage .
The following are circuit diagrams representing
typical measurement circuits for breakdown voltage:
Figure 12-2 shows the high-side transistor (QUH) in the
U-phase; Figure 12-3 shows the low-side transistor
(QUL) in the U-phase.
When measuring the high-side transistors, leave all
the pins not be measured open. When measuring the
low-side transistors, connect the LS pin to be measured
to the COMx pin, then l eave other unused pins o pen.
COM2
COM14
QUH
QWL QVL QUL
QVH
QWH
V
14
V1
W1
VBB1
W2
V2
22
U
20
LS
19
18
23
17
24
MIC
VBB2
26
Figure 12-2. Typical Meas urement Circuit for High-
side Transist or (QUH) in U-phase
SX6800xMH Series
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COM2
COM1
Q
UH
Q
WL
Q
VL
Q
UL
Q
VH
Q
WH
V
V1
W1
VBB1
W2
V2
22
U
20
LS
19
18
23
17
24
MIC
4
14
VBB2
26
Figure 12-3. Typical Meas urement Circuit for Lo w-
side Transist or (QUL) in U-phase
13. Calculating Power Losses and
Estimating Junction Temperature
This section describes the procedures to calculate
power losses in switching transistors, and to estimate a
junction temperature. Note that the descriptions listed
here are applicable to the SIM6800M series, which is
controlled by a 3-phase sine-wave PWM driving
strategy.
For quick and easy references, we offer calculation
support tools online. Please visit our website to find out
more.
DT0041: SX6800xMH Calculation T ool
http://www.semicon.sanken-ele.co.jp/en/calc-
tool/sx6800xmh_caltool_en.html
13.1 Power MOSFET
Total power loss in a power MOSFET can be
obtained by taking the sum of the following losses:
steady-state loss, PRON; switching loss, PSW; the steady-
state loss of a body diode, PSD. In the calculation
procedure we offer, the recovery loss of a body diode,
PRR, is considered negligibly small compared with the
ratios of other losses.
The following subsections contain the mathematical
procedures to calculate these losses (PRON, PSW, and PSD)
and the junction temperature of all power MOSFETs
operating.
13.1.1 Power MOSFET Steady-state Loss,
PRON
Steady-state loss in a power MOSFET can be
computed by using the RDS(ON) vs. ID curves, listed in
Section 14.3.1. As expressed by the curves in Figure
13-1, linear approximations at a range the ID is actually
used are obtained by: RDS(ON) = α × ID + β. The values
gained by the above calculation are then applied as
parameters in Equation (4), below. Hence, the equation
to obtain the power MOSFET steady-state loss, PRON, is:
P

=1
2I
()
× R
()
()×DT × d
= 22 1
3
+3
32
M × cos I
+ 21
8
+1
3
M × cos I . (4)
Where:
ID is the drain current of the power MOSFET (A),
RDS(ON) is the drain-to-source on-resistance of the
power MOSFET (Ω),
DT is the duty cycle, which is given by
DT =1 + M × sin(+)
2 ,
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the slope of the linear appr oxi mation in the RDS(ON)
vs. ID curve, and
β is the intercept of the linear approximation in the
RDS(ON) vs. ID curve.
Figure 13-1. Linear Appr oximate Equatio n of RDS(ON)
vs. ID Curve
y = 0.2865x + 2.1374
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0
R
DS(ON)
(Ω)
I
D
(A)
VCC = 15 V
25°C
75°C
125°C
SX68001MH
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13.1.2 Power MOSFET Switching Loss,
PSW
Switching loss i n a power M OSFET can be calculated
by Eq uation (5), letting IM be the effective current value
of the motor:
P
 =2 × f×× I×V
300 .
(5)
Where:
fC is the PWM carrier frequency (Hz),
VDC is the main power supply voltage (V), i.e., the
VBBx pi n input voltage, and
αE is the slope on the s witching loss cur ve (see Section
14.3.2).
13.1.3 Body Diode Steady-state Loss, PSD
Steady-state loss in the body diode of a power
MOSFET can be computed by using the VSD vs. ISD
curves, listed in Section 14.3.1. As expressed by the
curves in Figure 13-2, linear approximations at a range
the I SD is actually used are obtained by: VSD = α × ISD +
β. The values gained by the above calculation are then
applied as parameters in Equation (6), below. Hence, the
equation to obtain the body diode steady-state loss, PSD,
is:
P

=1
2V

()× I

()×(1DT)× d
= 1
2
1
2
4
3
M × cos I
+2
1
2
8
M × cos I . (6)
Where:
VSD is t he so urce -to-drain diode forward voltage of the
power MOSFET (V),
ISD is the source-to-drain diode forward current of the
power MOSFET (A),
DT is the duty c ycle, whic h is given by
DT =1 + M × sin(+)
2 ,
M is the modulation index (0 to 1),
cosθ is the motor power factor (0 to 1),
IM is the effective motor current (A),
α is the s l ope of the linear approximation in the VSD vs.
ISD curve, and
β is the intercept of the linear approximation in the VSD
vs. ISD curve.
Figure 13-2. Linear Appr oximate Equatio n of VSD vs.
ISD Curve
13.1.4 Estimating Junction Temperature
of Power MOSFET
The junction temperature of all power MOSFETs
operat ing, TJ, can be estimated with Equation (7):
T= R ×{(P
 + P
 + P
)× 6}+ T .
(7)
Where:
RJ-C is the junction-to-case thermal resistance (°C/W)
of all the power MOSFETs operating, and
TC is the case temperature (°C), measured at the point
defined in Figure 3-1.
y = 0.2014x + 0.6855
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5 2.0
VSD (V)
ISD (A)
125°C
75°C
25°C
SX68001MH
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14. Performance Curves
14.1 Transient Thermal Resistance Curves
The following graphs represent transient thermal resistance (the ratios of transient thermal resistance), with steady-
state thermal resistance = 1.
Figure 14-1. Ratio of Transient Thermal Resistance: SX68001MH
Figure 14-2. Ratio of Transient Thermal Resistance: SX68002MH
Figure 14-3. Ratio of Transient Thermal Resistance: SX68003MH
0.01
0.10
1.00
0.001 0.01 0.1 1 10
Ratio of Transient Thermal
Resistance
Time (s )
0.01
0.10
1.00
0.001 0.01 0.1 1 10
Ratio of Transient Thermal
Resistance
Time (s )
0.01
0.10
1.00
0.001 0.01 0.1 1 10
Ratio of Transient Thermal
Resistance
Time (s )
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14.2 Performance Curves of Control Parts
Figure 14-4 to Figure 14-28 provide performance curves of the control parts integrated in the SX6800xMH series,
including variety-dependent characteristics and thermal characteristics. TJ represents the junction temperature of the
control pa rts.
Table 14-1. Typical Characteristics of Control Parts
Figure Number
Figure Caption
Figure 14-4
Logic Supply Curre nt , ICC vs. T C (INx = 0 V)
Figure 14-5
Logic S upp l y Cur r ent , ICC vs. T C (INx = 5 V)
Figure 14-6
Logic S upp l y Cur r ent , ICC vs. VCCx Pin Voltage , VCC
Figure 14-7
Logic Supply Curr ent in 1-phase Operation (HINx = 0 V), I BS vs. TC
Figure 14-8
Logic Supply Curr ent in 1-phase Operation (HINx = 5 V), I BS vs. TC
Figure 14-9
VBx Pin Voltage, VB vs. Logic Supply Current IBS curve (HINx = 0 V)
Figure 14-10
Logic Operation Start Voltage, VBS(ON) vs. TC
Figure 14-11
Logic Op e ration Stop Voltage, V BS(OFF) vs. TC
Figure 14-12
Logic Operation Start Voltage, VCC(ON) vs. TC
Figure 14-13
Logic Operation Stop Volta ge, VCC(OFF) vs. TC
Figure 14-14
UVLO_VB Filtering Time vs. TC
Figure 14-15
UVLO_VCC Fi l t ering Time vs. TC
Figure 14-16
High Level Inp ut Signal Threshold Voltage, VIH vs. TC
Figure 14-17
Low Level Input Signal Thre s hold Voltage, VIL vs. TC
Figure 14-18
Input Current at High Leve l (HINx or LIN x), IIN vs. T C
Figure 14-19
High-side Turn-on Propagation Delay vs. TC (from HINx to HOx)
Figure 14-20
Low-side Turn-on P ropagati on Del ay vs. TC ( from LIN x to LOx)
Figure 14-21
Minimum Tr a nsmittable Pul se Width for High-side Switching, tHIN(MIN) vs. TC
Figure 14-22
Minimum Tr a nsmittable Pul se Width for Low-side Switchi ng, tLIN(MIN) vs. TC
Figure 14-23
SD P in Filte ring Time vs. TC
Figure 14-24
FO P in Filte ring Time vs. TC
Figure 14-25
Current Limit Reference Voltage, VLIM vs. TC
Figure 14-26
OCP Thr eshold Vo l tage, VTRIP vs. TC
Figure 14-27
OCP Hold T ime, tP vs. TC
Figure 14-28
OCP Blanking Time, tBK(OCP) vs. TC; Current Limit Blanking Time, tBK(OCL) vs. TC
Figure 14-29
REG Pin Voltage, VREG vs. TC
SX6800xMH Series
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Figure 14-4. Logic Supply Current, I CC vs. TC
(INx = 0 V) Figure 14-5. Logic Supply C urrent , ICC v s. TC (I Nx = 5 V)
Figure 14-6. Logic Supply Current, I CC vs. V CCx P i n
Voltage, VCC Figure 14-7. Logic Supply Current in 1-phase Operation
(HINx = 0 V), IBS vs. TC
Figure 14-8. Logic Supply Current in 1-phase
Operation (HINx = 5 V), IBS vs. TC Figure 14-9. VBx Pin Voltage, V B vs. Logic Supply
Current IBS curve (HI Nx = 0 V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
ICC (mA)
TC (°C)
Max.
Typ.
Min.
VCCx = 15 V, HINx = 0 V, LINx = 0 V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
ICC (mA)
TC (°C)
Max.
Typ.
Min.
VCCx = 15 V, HINx = 5 V, LINx = 5 V
2.6
2.8
3.0
3.2
3.4
3.6
3.8
12 13 14 15 16 17 18 19 20
ICC (mA)
VCC (V)
HINx = 0 V, LINx = 0 V
30°C
25°C
125°C
0
50
100
150
200
250
-30 0 30 60 90 120 150
IBS (µA)
TC (°C)
VBx = 15 V, HINx = 0 V
Max.
Typ.
Min.
0
50
100
150
200
250
300
-30 0 30 60 90 120 150
IBS (µA)
TC (°C)
VBx = 15 V, HINx = 5 V
Max.
Typ.
Min.
40
60
80
100
120
140
160
180
12 13 14 15 16 17 18 19 20
IBS (µA)
VB (V)
VBx = 15 V, HINx = 0 V
30°C
25°C
125°C
SX6800xMH Series
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Figure 14-10. Logic Operation Start Voltage, VBS(ON)
vs. TC Figure 14-11. Logic Operation Stop V oltage, VBS(OFF)
vs. TC
Figure 14-12. Logic Operation Start Voltage, VCC(ON)
vs. TC Figure 14-13. Logic Opera tion Stop Voltage, V CC(OFF)
vs. TC
Figure 14-14. UVLO_VB Filtering Time vs. TC Figure 14-15. UVLO_VCC Filtering Ti me vs. TC
9.5
9.7
9.9
10.1
10.3
10.5
10.7
10.9
11.1
11.3
11.5
-30 0 30 60 90 120 150
V
BS(ON)
(V)
TC (°C)
Max.
Typ.
Min.
9.0
9.2
9.4
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
-30 0 30 60 90 120 150
VBS(OFF) (V)
TC (°C)
Max.
Typ.
Min.
10.5
10.7
10.9
11.1
11.3
11.5
11.7
11.9
12.1
12.3
12.5
-30 0 30 60 90 120 150
VCC(ON) (V)
TC (°C)
Max.
Typ.
Min.
10.0
10.2
10.4
10.6
10.8
11.0
11.2
11.4
11.6
11.8
12.0
-30 0 30 60 90 120 150
VCC(OFF) (V)
TC (°C)
Max.
Typ.
Min.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
UVLO_VB Filtering Time (µs)
TC (°C)
Max.
Typ.
Min.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-30 0 30 60 90 120 150
UVLO_VB Filtering Time ( µs)
TC (°C)
Max.
Typ.
Min.
SX6800xMH Series
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Figure 14-16. High Level Input Signal Thresho l d
Voltage, VIH vs. TC Figure 14-17. Low Level Input Signal Thre shol d
Voltage, VIL vs. TC
Figure 14-18. Input Curr ent at High Level (HINx or
LINx), IIN vs. TC Figure 14-19. High-side Turn-on Pr opa gatio n Delay vs.
TC (from HINx to HOx)
Figure 14-20. Low-side Turn-on Prop agation Delay
vs. TC (from LI Nx t o LOx) Figure 14-21. Minimum Transmittab le Pulse Width for
High-side Switc hing, tHIN(MIN) vs. TC
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
-30 0 30 60 90 120 150
VIH (V)
TC (°C)
Max.
Typ.
Min.
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-30 0 30 60 90 120 150
VIL (V)
TC (°C)
Max.
Typ.
Min.
0
50
100
150
200
250
300
350
400
-30 0 30 60 90 120 150
IIN (µA)
TC (°C)
INHx/INLx = 5 V
Max.
Typ.
Min.
0
100
200
300
400
500
600
700
800
-30 0 30 60 90 120 150
High-side Tur n-on
Propagation Delay (ns)
TC (°C)
Max.
Typ.
Min.
0
100
200
300
400
500
600
700
-30 0 30 60 90 120 150
Low-side Turn-on
Propagation Delay (ns)
TC (°C)
Max.
Typ.
Min.
0
50
100
150
200
250
300
350
400
-30 0 30 60 90 120 150
tHIN(MIN) (ns)
TC (°C)
Max.
Typ.
Min.
SX6800xMH Series
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Figure 14-22. Minimum Transmittable Pulse Width
for Low-side Switchin g, tLIN(MIN) vs. TC Figure 14-23. SD Pin Filtering T ime vs. TC
Figure 14-24. FO Pin Filteri ng Time vs. TC Figure 14-25. Current Limit Reference Voltage, VLIM vs.
TC
Figure 14-26. OCP Threshold Vol tage, VTRIP vs. TC Figure 14-27. OCP Hold Time, tP vs. TC
0
50
100
150
200
250
300
350
400
-30 0 30 60 90 120 150
t
LIN(MIN)
(ns)
TC (°C)
Max.
Typ.
Min.
0
1
2
3
4
5
6
-30 0 30 60 90 120 150
tSD (ns)
TC (°C)
Max.
Typ.
Min.
0
1
2
3
4
5
6
-30 0 30 60 90 120 150
tFO (ns)
TC (°C)
Max.
Typ.
Min.
0.550
0.575
0.600
0.625
0.650
0.675
0.700
0.725
0.750
-30 0 30 60 90 120 150
VLIM (ns)
TC (°C)
Max.
Typ.
Min.
0.90
0.92
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
-30 0 30 60 90 120 150
VTRIP (ns)
TC (°C)
Max.
Typ.
Min.
0
5
10
15
20
25
30
35
40
45
50
-30 0 30 60 90 120 150
tP (µs)
TC (°C)
Max.
Typ.
Min.
SX6800xMH Series
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Figure 14-28. OCP Bla nking Time, tBK(OCP) vs. TC;
Current Limit Blanking T ime, tBK(OCL) vs. TC Figure 14-29. REG Pin Volta ge, V REG vs. TC
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-30 0 30 60 90 120 150
t
BK
(µs)
TC (°C)
Max.
Typ.
Min.
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
-30 0 30 60 90 120 150
VREG (V)
TC (°C)
Max.
Typ.
Min.
SX6800xMH Series
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14.3 Performance Curves of Output Parts
14.3.1 Output Transistor Performance Curves
14.3.1.1. SX68001MH
Figure 14-30. Power MOSFET RDS(ON) vs. ID Figure 14-31. Power MOSFET VSD vs. ISD
14.3.1.2. SX68002MH
Figure 14-32. Power MOSFET RDS(ON) vs. ID Figure 14-33. Power MOSFET VSD vs. ISD
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0
R
DS(ON)
(Ω)
ID (A)
VCCx = 15 V
25°C
75°C
125°C
SX68001MH
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5 2.0
VSD (V)
ISD (A)
125°C
75°C
25°C
SX68001MH
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
0.0 0.5 1.0 1.5
RDS(ON) (Ω)
ID (A)
VCCx = 15 V
25°C
75°C
125°C
SX68002MH
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5
VSD (V)
ISD (A)
125°C
75°C
25°C
SX68002MH
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 35
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14.3.1.3. SX68003MH
Figure 14-34. Power MOSFET RDS(ON) vs. ID Figure 14-35. Power MOSFET VSD vs. ISD
14.3.2 Switching Losses
Conditions: VB Bx = 300 V, half-bridge circuit with inductive load.
Switching Loss, E , is the sum o f tur n-on los s and turn-off loss.
14.3.2.1. SX68001MH
Figure 14-36. High-side Switc hing Loss Figure 14-37. Low-side Swit ching Los s
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.0 0.5 1.0 1.5 2.0 2.5
R
DS(ON)
(Ω)
I
D
(A)
VCCx = 15 V
25°C
75°C
125°C
SX68003MH
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0 0.5 1.0 1.5 2.0 2.5
VSD (V)
ISD (A)
125°C
75°C
25°C
SX68003MH
0
10
20
30
40
50
60
0.0 0.5 1.0 1.5 2.0
E (µJ)
ID (A)
VB = 15 V
SX68001MH
0
10
20
30
40
50
60
0.0 0.5 1.0 1.5 2.0
E (µJ)
ID (A)
VCC = 15 V
SX68001MH
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 36
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14.3.2.2. SX68002MH
Figure 14-38. High-side Switc hing Loss Figure 14-39. Low-side Swit ching Los s
14.3.2.3. SX68003MH
Figure 14-40. High-side Switc hing Loss Figure 14-41. Low-side Swit ching Los s
0
20
40
60
80
100
120
140
160
0.0 0.5 1.0 1.5
E (µJ)
I
D
(A)
VB = 15 V
SX68002MH
0
20
40
60
80
100
120
140
160
0.0 0.5 1.0 1.5
E (µJ)
ID (A)
VCC = 15 V
SX68002MH
0
50
100
150
200
250
300
350
0.0 0.5 1.0 1.5 2.0 2.5
E (µJ)
ID (A)
VB = 15 V
SX68003MH
0
50
100
150
200
250
300
350
0.0 0.5 1.0 1.5 2.0 2.5
E (µJ)
ID (A)
VCC = 15 V
SX68003MH
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 37
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© SANKEN ELECTRIC CO., LTD. 2013
14.4 Allowable Effective Current Curves
The following curves represent allowable effective currents in 3-pha se si ne -wa ve P W M d rivin g wit h p ar a mete r s suc h
as typical RDS(ON) or VCE(SAT), and typical s wi tching losses.
Operating conditions: VBBx pin inpu t volta ge, VDC = 30 0 V; VC C x pi n i np ut vo ltage, VCC = 1 5 V; modulatio n inde x,
M = 0.9; motor power factor, cosθ = 0.8; junction temperature, TJ = 150 °C.
14.4.1 SX68001MH
Figure 14-42. Allowable Effec tive Current (fC = 2 kHz): SX68001MH
Figure 14-43. Allowable Effective C urrent (fC = 1 6 kHz): SX68001MH
0.0
0.5
1.0
1.5
2.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
0.5
1.0
1.5
2.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 38
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© SANKEN ELECTRIC CO., LTD. 2013
14.4.2 SX68002MH
Figure 14-44. Allowable Effec tive Current (fC = 2 kHz): SX68002MH
Figure 14-45. Allowable Effective Current (fC = 16 kHz): SX68002MH
0.0
0.2
0.4
0.6
0.8
1.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
0.0
0.2
0.4
0.6
0.8
1.0
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 39
Aug. 10, 2018 http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2013
14.4.3 SX68003MH
Figure 14-46. Allowable Effec tive Current (fC = 2 kHz): SX68003MH
Figure 14-47. Allowable Effec tive Current (fC = 16 kHz): SX68003MH
(0.0)
0.3
0.6
0.9
1.2
1.5
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 2 kHz
(0.0)
0.3
0.6
0.9
1.2
1.5
25 50 75 100 125 150
Allowable Effective Current (Arms)
TC (°C)
fC = 16 kHz
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 40
Aug. 10, 2018 http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2013
15. Pattern Layout Example
Thi s sec ti on c o nta i ns t he schemati c d i agr a ms o f a P C B p a tter n layout e xample u sing a n SX6800xMH series device.
For details on the land pattern example of the IC, see Section 9.
Figure 15-1. Pa ttern Layout Example (Two-layer Board)
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 41
Aug. 10, 2018 http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2013
R9
R8
C12
CX1
R10
CN2
3
2
1
C4
1
2
CN1
SD
VCC1
VB1
VB31
W2
U
FO
COM2
LIN1
LIN2
LIN3
VCC2
COM1
HIN2
HIN3
OCL
W1
V1
VBB1
V2
LS
V
VB2VBB2
15
11
10
7
6
5
4
3
26
25
22
19
CN3HIN1
CN4
18
20
21
23
24
1
2
8
9
16
17
14
12
R1
R2
C11
C17
C8
C2 C6
C7 C3
C5
C1
REG
13
VB32 27
6
5
4
3
2
1
6
5
4
3
2
1
10
C9C10
9
8
7
Figure 15-2. Circuit Dia gra m o f P CB Pattern La yout Example
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 42
Aug. 10, 2018 http://www.sanken-ele.co.jp/en/
© SANKEN ELECTRIC CO., LTD. 2013
16. Typical Motor Driver Application
This section contai ns the i nfor mation o n the typica l motor dr iver ap plicatio n listed in the p revious section, i ncludi ng
a circuit diagram, specifications, and the bill of the materials used.
Motor Driver Specifications
IC SX68003MH
Main Supply Voltage, V
DC
300 VDC (typ.)
Rate d Output Power 50 W
Circuit Diag r am
See Figure 15-2.
Bill of Materials
Symbol
Part Type
Ratings
Symbol
Part Type
Ratings
C1
Electrolytic 22 μF, 35 V CX1 Film 0.01 μF, 630 V
C2
Electrolytic 22 μF, 35 V
R1
General 0 Ω, 1/8 W
C3
Electrolytic 22 μF, 35 V
R2
General 4.7 kΩ, 1/8 W
C4 Electrolytic 47 μF, 35 V R8* Metal plate 10 kΩ, 1/8 W
C5
Ceramic 0.1 μF, 50 V
R9
* Metal plate 1 Ω, 2 W
C6
Ceramic 0.1 μF, 50 V
R10
* General Open
C7 Ceramic 0.1 μF, 50 V IPM1 IC SX68003MH
C8
Ceramic 0.1 μF, 50 V
CN1
Pin header Equiv. to B2P3-VH
C9
Ceramic 0.1 μF, 50 V
CN2
Pin header Equiv. to B2P5-VH
C10
Ceramic 0.1 μF, 50 V
CN3
Connector Equiv. to MA10-1
C11
Ceramic 0.1 μF, 50 V
CN4
Connector Equiv. to MA06-1
C16
Ceramic 100 pF, 50 V
C17
Ceramic 0.1 μF, 50 V
* Refers to a par t that requires adjustment based o n operation performance i n an actual application.
SX6800xMH Series
SX6800xMH-DSE Rev.1.0 SANKEN ELECTRIC CO., LTD. 43
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© SANKEN ELECTRIC CO., LTD. 2013
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