ANALOG LC?M0s DEVICES Parallel Loading Dual 12-Bit DAC AD7947 REV. A 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS 12-bit digital-to-analog converter. The D/A converters provide 4-quadrant multiplication capabilities with separate reference inputs and feedback resistors. Each D/A converter is preceeded by a 12-bit data latch for direct interfacing to 12- and 16-bit microprocessor. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number" -l AD75478(X)/883B ~2 AD7547T(X)/883B -3 AD7547U(X)/883B NOTE 'To complete the part number substitute the package identifier as shown in paragraph 1.2.3. 1.2.3 Case Outline. See Appendix 1 of General Specification ADI-M-1000: package outline: (X) Package Description Q Q-24 24-Pin Cerdip, 0.3 Width E E-28A 28-Contact LCC 1.3 Absolute Maximum Ratings. (T, = 25C unless otherwise noted, Pin numbers refer to DIP package) Vpp (Pin 21)toDGND.. 2. ee et nee -0.3V, +17V VREFA> Vrerp (Pins 4,22)to AGND .. 0 2. ee ee te +25V Versa, Vaeep (Pins 3, 23)toAGND .. 2... 2 ee ee +25V Digital Input Voltage (Pins 5-20)te DGND ...........2.. 00002 -0.3V, Vpp +0.3V Vez VpinzatoDGND .......0. 2.000. ee ee eee eas -0.3V, Vpp +0.3V AGND toDGND ........ 2.000: pee ee tee te te ee ees 0.3V, Vpp +0.3V Power Dissipation Upto +75 we ee ee 450mW Derates above +75h 20 1 ee ee 6mW/C Operating Temperature Range 2... 1. ee te ee ee ~ 55C to +125C Lead Temperature (Soldering 10sec) 2.0... tt ee ee te es + 300C 1.5 Thermal Characteristics. Thermal Resistance @j = 35C/W for Q-24 and E-28A ya = 120C/W for Q-24 and E-28A DIGITAL-TO-ANALOG CONVERTERS 8-153 DIGITAL-TO-ANALOG CONVERTERS =AD7547SPECIFICATIONS Table 1. Design Sub Sub Sub Limit Group| Group| Group Test Symbol] Device | Tries Tuas| } 2,3 4 Test Condition'/Comments Units Resolution RES -1,2,3 | 12 Bits Relative Accuracy RA -1 1 1 1 Vpp = 10.8V and 16.5V + LSB max ~2,3 12 1 V2 1/2 Differential Nonlinearity DNL | -1,2,3.| 1 1 1 All Grades Guaranteed Monotonic | + LSB max to 12 Bits from Tin tO Tins: Vpp = 10.8V and 16.5V. Gain Error Ag ~1 6 6 6 Measured Using Re, and Reg. Both | + LSB max -2 3 6 3 3 DAC Registers Loaded with All 1s. -3 2 6 2 2 Vopp = 10.8V. Gain Temperature Coefficient dAg/dT| -1,2,3] 5 Typical Value is Ilppm/C + ppay/C max Output Leakage Current (Pin 2) Ioura | 1,2,3] 250 10 250 DAC A Register Loaded with pA max All0s; Vpp = 16.5V Output Leakage Current (Pin 24) | Iours | 1,2,3] 250 10 250 DACB Register Loaded with nA max All0s; Vpp= 16.5V Reference Input Resistance R, -1,2,3 19 9 9 Typical Input Resistance is 14k kf min (Pin 4, Pin 22) 20 20 20 Von = 10.8V kf} max Reference Input Resistance Match |RMm | 1,2 3 3 3 Typically + 0.5% +% max VRera; Vrera ~3 1 3 I I Vpp = 10.8V Digital Input High Voltage Vin -1,2,3 | 2.4 2.4 2.4 Vpp = 10.8V and 16.5V Vmin Digital Input Low Voltage Vi. -1,2,3 | 0.8 0.8 0.8 Vpp = 10.8V and 16.5V Vmax Digital Input Current lw -1,2,3] 10 1 10 Vin = Vpp = 16.5V pA max Digital Input Capacitance Cc -1,2,3] 10 pF max Power Supply Voltage Vop -1,2,3 | 10.8 V min 16.5 Vmax Power Supply Current Ipp -1,2,3] 2 2 2 Vop = 16.5V mA max Output Current Settling Time @ 25C tsp -1,2,3] 1.5 To 0.01% of Full-Scale Range. ps max Tout Load = 100. Cextr= 13pF. DAC Output Measured from Rising Edge of WR. Typical Value of Setding Time is 0.8y5. AC Feedthrough Vreratoloura | FT -1,2,3) 65 Vrera, Vrers = 20V p-p 10kHz dB max and Vaers to lours Sine-Wave DAC Register Loaded with All 0s. Power Supply Rejection Ratio PSRR | -1,2,3 | 0.02 0.01 0.02 AVpp= Vpp max- Vpp min; + %/% max (AGain/AVpp) Vpn= 10.89 Output Capacitance for Cour | -1,2,3] 70 DACA, DACB Loaded with All0s. | pF max DAC A and DAC B 140 DAC A, DACB Loaded with All Is. Data Setup Time, t, tos -1,2,3] 80 os min Data Hold Time, t, ton 1,2,3| 25 ns min Chip Select to Write Setup Time, t; | tows ~1,2,3] 100 ns min Chip Select to Write Hold Time, | town -1,2,3] 0 nsmin Write Pulse Width, t; tw -1,2,3 | 100 ns min NOTES Wop = + 12V to + 1SV + 10% except where outherwise stated; Vacra = Vaure = 10V; Voeinz = Venza = Vein = OV. Output amplifiers are AD644. Pin numbers refer to DIP Package. 8-154 DIGITAL-TO-ANALOG CONVERTERS REV. AAD7947 DATA a NOTES = __ Lo 1. ALL INPUT SIG! SIGNAL RISE AND FALL TIMES MEASURED FROM 10. 30% To 5V. Ons. 2. TIMING MEASUREMENT REFERENCE LEVEL IS Vint ve Figure 1. Timing Diagram for AD7547 3.2.1 Functional Block Diagram and Terminal Assignments. Voo =={21) @)- AD7547 12 DAC A REGISTER 2 3) Reon 2) louta 4 DAC A 1) AGNO eSa(s cse 4)v, a Go CONTROL mera wats LOGIC = 22) Vaere 23) Rene L__4 24) tours DAC B REGISTER 7 12 as) (6 DGND B11 - DBO 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (80). REV. A Q Package (DIP) Vv acno [1] 26] loure lous [2] 23] Free Paa [3] [zz] Vnere Vera [a] 21] V, cea [ ase) oeo [6 | [20] 3B [19] wai AD7547 pet (7 | (Not to Bestel [1a] 0813 (se) vez [3] 7] oe10 ves [| [16] bee ves [10 [15] ose vas [11 [14] vB? oan fiz 13] pes E Package (LCC) < 9 2 die! 432 1 28 27 26 Aull Vaera CSA (LSB) DBO NC DBI DB2 OB3 11 omen mo uw 10 AD7547 TOP VIEW {Not to Scale} WR NC DB11 (MSB} be10 bes 12 13 14 15 16 17 18 ZB2285 NC = NOCONNECT DIGITAL-TO-ANALOG CONVERTERS 8-155 DIGITAL-TO-ANALOG CONVERTERS =AD7547 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). AGND louts louta Rras ~Vner (- 10V) 24 [2s Pron Vrera 22 }H__4_ Vaer (10V) Vaca Voo 2} Voo (15V} a ae l3 J 4 LY -[s| cst tsz {20}, =| vo a 1. 10k TO WR INPUTS {s] wr [19 } wv {7 D1 p11 fi1g ee) D2 p10 [17 >a | D3 Do [16 >{10 | D4 bs 715 kl Ds o7 [14 {72} oGno De 413 10k TO DATA INPUTS AAA vv Vee (5V) GND T Vee (5V) 3 470 GND aks EXTERNAL CLOCK V/P 16 15] [14] [a3] [rz] [x1] [79] [>] DC TO 100kHz T DIODES = 1N914 CLR PR a J a D CK rap cK ar kK a PR SN5476 CLR Vee | | 8-156 DIGITAL-TO-ANALOG CONVERTERS REV. AAD7547 5.0 Unipolar Binary Operation (2-Quadrant Multiplication) Figure 2 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 2 is given in Table 2. Operational amplifiers Al and A2 can be in a single package (AD644) or separate packages (AD544, AD OP-27). Capacitors C1 and C2 provide phase compensation to help prevent overshoot and ringing when high-speed op amps are used. For zero offset adjustment, the appropriate DAC register is loaded with all Os and amplifier offset adjusted so that Vouta or Vours is OV. Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 (R3) so that Voura (Vouts)= Vin (4095/4096). For high temperature operation, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7547, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting Rl, R2, R3, R4 and trimming the reference voltage magnitude. AD7547 Figure 2. AD7547 Unipolar Binary Operation Table 2. Unipolar Binary Code Table for Cicuit of Figure 2 Binary Number in DAC Register Analog Output, MSB LSB Voura or Vours WH wn nn ~Viw (S952) 1000 0000 0000 ~ Vin (258 | = -12Viy 0000 0000 0001 ~Viw( ang) 0000 0000 0000 ov REV. A DIGITAL-TO-ANALOG CONVERTERS 8-157 DIGITAL-TO-ANALOG CONVERTERS aAD7947 6.0 Bipolar Operation (4-Quadrant Multiplication) The recommended circuit diagram for bipolar operation is shown in Figure 3. Offset binary coding is used. With the appropriate DAC register loaded to 1000 0000 0000, adjust R1 (R3) so that Voura (Vouts) = OV. Alternatively, Rl, R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10) varied for Vouta (Vours) = OV. Full-scale trimming can be accomplished by adjusting the amplitude of Vp or by varying the value of RS (R8). If Rl, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8, R9, R10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. When operating over a wide tem- perature range, it is important that the resistors be of the same type so that their temperature coefficients match. The code table for Figure 3 is given in Table 3. Voo wa Re 12 20k. AD712 a2 Me A? fours 10ki tt AD7547* Ra 20kit BE Voura Vine CONTROL CIRCUITRY OMITTED FOR CLARITY V Figure 3. Bipolar Operation (Offset Binary Coding) Table 3. Bipolar Code Table for Offset Binary Circuit of Figure 3. Binary Number in DAC Register Analog Output, MSB LSB Voura or Vouts wad an + Vin (3042) 1000 0000 0001 + Vin aoe] 1000 0000 0000 ov ond 1a ain -Viv( p48) 0000 0000 0000 ~ Vin 3048) = -Vay 8-158 DIGITAL-TO-ANALOG CONVERTERS REV. A