MB81E161622-10FH-X - Fujitsu - Datasheet.Directory

DS05-11406-1E

FUJITSU SEMICONDUCTOR

DATA SHEET

MEMORY

CMOS

2 ×

××

× 512 K ×

××

× 16 Bit

Single Data Rate I

F FCRAM

(Extended Temp.Version)

Consumer/Embedded Application Specific Memory

MB81E161622-10-X/-12-X

CMOS 2-Bank ×

××

× 524,288-Word ×

××

× 16 Bit

Fast Cycle Random Access Memory (FCRAM) with Single Data Rate

■DESCRIPTION

The Fujitsu MB81E161622 is a Fast Cycle Random Access Memory (FCRAM*) containing 16,777,216 memory

cells accessible in a 16-bit for mat. The MB81E161622 features a fully synchronous operation referenced to a

positive edge clock, whereby all operations are synchronized at a clock input which enables high perfor mance

and simple user interface coexistence.

The MB81E161622 is utilized using a Fujitsu advanced FCRAM core technology and designed to improve the

random access performance and the complexity of controlling regular synchronous DRAM (SDRAM) which require

many wait state due to long latency constraints.

The MB81E161622 is ideally suited for various embedded/consumer applications including digital AVs, printers

and file storage where a large band width memory is needed.

* : FCRAM is a trademark of Fujitsu Limited, Japan.

■PRODUCT LINEUP

Parameter MB81E161622

-10-X -12-X

Clock Frequency @CL = 2 100 MHz Max. 84 MHz Max.

Burst Mode Cycle Time CL = 1 15 ns Min. 20 ns Min.

CL = 2 10 ns Min. 12 ns Min.

Access Time From Clock CL = 1 10 ns Max. 14 ns Max.

CL = 2 6 ns Max. 7 ns Max.

RAS Cycle Time 30 ns Min. 36 ns Min.

Operating Current (ICC1) 130 mA Max. 120 mA Max.

Power Down Mode Current (ICC2P) 0.6 mA Max.

MB81E161622-10-X/-12-X

■ FEATURES

■PACKAGE

• Single +3.3 V Supply ±0.3 V tolerance

• LVTTL compatible I/O interface

• Two-bank operation

• Programmable burst type, burst length, and

CAS latency

• 4 K refresh cycles every 32 ms

• Auto-refresh

• CKE power down mode

• Output Enable and Input Data Mask

54-pin Plastic TSOP (II) Package

(FPT-54P-M02)

(Normal Bend)

Marking side

MB81E161622-10-X/-12-X

■PIN ASSIGNMENT

■PIN DESCRIPTION

*: These pins are connected internally in the chip.

Symbol Function

VCC, VCCQ Supply Voltage

VSS, VSSQ * Ground

DQ0 to DQ15 Data I/O • Lower Byte : DQ0 to DQ7

• Upper Byte : DQ8 to DQ15

DQML, DQMU Input/Output Mask

WE Write Enable

CAS Column Address Strobe

RAS Row Address Strobe

CS Chip Select

BA Bank Select

AP Auto Precharge Enable

A0 to A10 Address Input • Row : A0 to A10

• Column : A0 to A7

CKE Clock Enable

CLK Clock Input

NC No Connection

TSOP (II)

(TOP VIEW)

< Normal Bend : FPT-54P-M02 >

(Marking side)

VCC

DQ0

VCCQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VCCQ

DQ5

DQ6

VSSQ

DQ7

VCC

DQML

CAS

RAS

A10/AP

VCC

VSS

DQ15

VSSQ

DQ14

DQ13

VCCQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VCCQ

DQ8

VSS

DQMU

CLK

CKE

VSS

MB81E161622-10-X/-12-X

■BLOCK DIAGRAM

CKE

CLK

RAS

CAS

RAS

CAS

DQML,

DQMU

DQ0

DQ15

A0 to A9,

A10/AP

I/O

VCC

VSS/VSSQ

VCCQ

CLOCK

BUFFER

COMMAND

DECODER

ADDRESS

BUFFER/

BANK SELECT

I/O DATA

BUFFER/

To each block

CONTROL

SIGNAL

LATCH

MODE

COLUMN

ADDRESS

COUNTER

DRAM

CORE

(2,048 × 256 × 16)

BANK-1

BANK-0

COL.

ADDR.

ROW

ADDR.

Fig. 1 −

−−

− MB81E161622 BLOCK DIAGRAM

MB81E161622-10-X/-12-X

■FUNCTIONAL TRUTH TABLE *1

•

••

• COMMAND TRUTH TABLE *2, *3, *4

*1:V = Valid, L = Logic Low, H = Logic High, X = either L or H.

*2:All commands assume no CSUS command on previous rising edge of clock.

*3:All commands are assumed to be valid state transitions.

*4:All inputs are latched on the rising edge of the clock.

*5:The NOP and DESL commands hav e the same effect on the part. Unless specifically noted, NOP will represent

both NOP and DESL commands in later descriptions.

*6:The READ, READA, WRIT and WRITA commands should be issued only after the corresponding bank has been

activated (ACTV command) . Refer to “STATE DIAGRAM” in section “■ FUNCTIONAL DESCRIPTION.”

*7:The A CTV command should be issued only after the corresponding bank has been precharged (PRE or PALL

command) .

*8:Required after power up. Refer to “PO WER-UP INITIALIZATION” in section “■ FUNCTIONAL DESCRIPTION.”

*9:The MRS command should be issued only after all banks hav e been precharged (PRE or PALL command) and

DQ is in High-Z. Refer to “STATE DIAGRAM” in section “■ FUNCTIONAL DESCRIPTION.”

Function Com-

mand

CKE CS RAS CAS WE BA A10

(AP) A9,

n-1 n

Device Deselect *5DESLHXHXXXXXXX

No Operation *5NOPHXLHHHXXXX

Burst Stop BSTHXLHHLXXXX

Read *6 READ H X L H L H V L X V

Read with Auto-precharge *6 READA H X L H L H V H X V

Write *6WRITHXLHLLVLXV

Write with Auto-precharge *6 WRITA H X L H L L V H X V

Bank Active *7ACTVHXLLHHVVVV

Precharge Single Bank *8 PRE H X L L H L V L X X

Precharge All Banks *8 PALL H X L L H L X H X X

Mode Register Set *8, 9MRSHXLLLLXXVV

MB81E161622-10-X/-12-X

•

••

• DQM TRUTH TABLE

Note : DQML and DQMU control DQ0-7 and DQ8-15, respectively.

•

••

• CKE TRUTH TABLE

*1:The CSUS command requires that at least one bank is active. Refer to “STATE DIAGRAM” in section

“■ FUNCTIONAL DESCRIPTION.”

*2:The REF command should be issued only after all banks have been precharged (PRE or PALL command) .

Refer to “STATE DIAGRAM” in section “■ FUNCTIONAL DESCRIPTION.”

*3:The PD command should be issued only after the last read data have been appeared on DQ.

Function Command CKE DQML DQMU

n-1 n

Data Write/Output Enable for Lower Byte ENBL L H X L X

Data Write/Output Enable for Upper Byte ENBL U H X X L

Data Mask/Output Disable for Lower Byte MASK L H X H X

Data Mask/Output Disable for Upper Byte MASK U H X X H

Current

State Function Com-

mand

CKE CS RAS CAS WE BA A10

(AP)

n-1 n

Bank Active Clock Suspend Mode Entry *1 CSUS H L X X X X X X X

Any

(Except Idle) Clock Suspend Continue *1 LLXX XXXXX

Clock

Suspend Clock Suspend Mode Exit LHXX XXXXX

Idle Auto-refresh Command *2 REF H H L L L H X X X

Idle Power Down Entry *3 PD HLL H H HX X X

HLHX XXXXX

Power Down Power Down Exit LHL H H HX X X

LHHX XXXXX

MB81E161622-10-X/-12-X

•

••

• OPERATION COMMAND TABLE (Applicable to single bank)

(Continued)

Current

State CS RAS CAS WE Addr Command Function

Idle

H X X X X DESL NOP

LHHH X NOP NOP

LHHL X BST NOP *1

L H L H BA, CA, AP READ/READA Illegal *2

L H L L BA, CA, AP WRIT/WRITA Illegal *2

L L H H BA, RA ACTV Bank Active after tRCD

L L H L BA, AP PRE NOP

L L H L AP PALL NOP *1

LLLH X REF Auto-refresh *3

LLLL MODE MRS Mode Register Set

(Idle after tRSC) *3, *5

Bank Active

H X X X X DESL NOP

LHHH X NOP NOP

LHHL X BST NOP

L H L H BA, CA, AP READ/READA Begin Read; Determine AP

L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE Precharge

L L H L AP PALL Precharge *1

L L L H X REF Illegal

LLLL MODE MRS Illegal

Read

H X X X X DESL NOP (Continue Burst to End →

Bank Active)

LHHH X NOP NOP (Continue Burst to End →

Bank Active)

L H H L X BST Burst Stop → Bank Active

L H L H BA, CA, AP READ/READA Terminate Burst, New Read;

Determine AP

L H L L BA, CA, AP WRIT/WRITA Terminate Burst, Start Write;

Determine AP *4

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE Terminate Burst, Precharge → Idle

L L H L AP PALL Terminate Burst, Precharge → Idle *1

L L L H X REF Illegal

LLLL MODE MRS Illegal

MB81E161622-10-X/-12-X

(Continued)

Current

State CS RAS CAS WE Addr Command Function

Write

H X X X X DESL NOP (Continue Burst to End →

Bank Active)

LHHH X NOP NOP (Continue Burst to End →

Bank Active)

L H H L X BST Burst Stop → Bank Active

L H L H BA, CA, AP READ/READA Terminate Burst, Start Read;

Determine AP *4

L H L L BA, CA, AP WRIT/WRITA Terminate Burst, New Write;

Determine AP

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE Terminate Burst, Precharge → Idle

L L H L AP PALL Terminate Burst, Precharge → Idle *1

L L L H X REF Illegal

LLLL MODE MRS Illegal

Read with

Auto-

precharge

H X X X X DESL NOP (Continue Burst to End →

Precharge → Idle)

LHHH X NOP NOP (Continue Burst to End →

Precharge → Idle)

L H H L X BST Illegal

L H L H BA, CA, AP READ/READA Illegal *2

L H L L BA, CA, AP WRIT/WRITA Illegal *2

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE Illegal *2

L L H L AP PALL Illegal

L L L H X REF Illegal

LLLL MODE MRS Illegal

MB81E161622-10-X/-12-X

(Continued)

Current

State CS RAS CAS WE Addr Command Function

Write with

Auto-

precharge

H X X X X DESL NOP (Continue Burst to End →

Precharge → Idle)

LHHH X NOP NOP (Continue Burst to End →

Precharge → Idle)

L H H L X BST Illegal

L H L H BA, CA, AP READ/READA Illegal *2

L H L L BA, CA, AP WRIT/WRITA Illegal *2

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE Illegal *2

L L H L AP PALL Illegal

L L L H X REF Illegal

LLLL MODE MRS Illegal

Precharging

H X X X X DESL NOP (Idle after tRP)

L H H H X NOP NOP (Idle after tRP)

L H H L X BST NOP (Idle after tRP)

L H L H BA, CA, AP READ/READA Illegal *2

L H L L BA, CA, AP WRIT/WRITA Illegal *2

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE NOP

L L H L AP PALL NOP *1

L L L H X REF Illegal

LLLL MODE MRS Illegal

Bank

Activating

H X X X X DESL NOP (Bank Active after tRCD)

L H H H X NOP NOP (Bank Active after tRCD)

L H H L X BST NOP (Bank Active after tRCD) *1

L H L H BA, CA, AP READ/READA Illegal *2

L H L L BA, CA, AP WRIT/WRITA Illegal *2

L L H H BA, RA ACTV Illegal *2

L L H L BA, AP PRE Illegal *2

L L H L AP PALL Illegal

L L L H X REF Illegal

LLLL MODE MRS Illegal

MB81E161622-10-X/-12-X

(Continued)

ABBREVIATIONS :

RA = Row Address BA = Bank Address

CA = Column Address AP = Auto Precharge

*1:Entry may affect other bank.

*2:Illegal to the bank in specified state; entry may be legal to the bank specified by BA, depending on the state of

that bank.

*3:Illegal if any bank is not idle.

*4:Must satisfy bus contention, bus turn around, and/or write recovery requirements.

Refer to “TIMING DIAGRAM -11 & -12” in section “■ TIMIMG DIAGRAMS.”

*5:The MRS command should be issued only when all DQ are in High-Z.

Note: All entries in “OPERATION COMMAND TABLE” assume that the CKE was High during the proceeding clock

cycle and the current clock cycle.

Illegal means that the device operation and/or data-integrity are not guaranteed. If used, power up sequence

will be asserted after power shut down.

Current

State CS RAS CAS WE Addr Command Function

Refreshing H X X X X DESL NOP (Idle after tREFC)

L H H X X NOP/BST NOP (Idle after tREFC)

LHLX X READ/READA/

WRIT/WRITA Illegal

LLHX X ACTV/

PRE/PALL Illegal

LLLX X REF/

MRS Illegal

Mode

Setting

H X X X X DESL NOP (Idle after tRSC)

L H H H X NOP NOP (Idle after tRSC)

L H H L X BST Illegal

LHLX X READ/READA/

WRIT/WRITA Illegal

LLXX X ACTV/PRE/

PALL/REF/MRS Illegal

MB81E161622-10-X/-12-X

•

••

• COMMAND TRUTH TABLE FOR CKE

Note: All entries in “COMMAND TRUTH TABLE FOR CKE” are specified at CKE (n) state and CKE input from

CKE (n−1) to CKE (n) state must satisfy the corresponding setup and hold time for CKE.

Current

State CKE

(n-1) CKE

(n) CS RAS CAS WE Addr Function

Power

Down

HXXXXX X Invalid

LHHXXX X Exit Power Down Mode → Idle

LHLHHH X

L L X X X X X NOP (Maintain Power Down Mode)

L H L L X X X Illegal

LHLHLX X Illegal

LHLHHX X Illegal

All

Banks

Idle

H H H X X X V Refer to “Operation Command Table”.

H H L H X X V Refer to “Operation Command Table”.

H H L L H X V Refer to “Operation Command Table”.

HHLLLH X Auto-refresh

HHLLLL V Refer to “Operation Command Table”.

H L H X X X X Power Down

H L L H H H X Power Down

H L L H H L X Illegal

H L L H L X X Illegal

HLLLHX X Illegal

HLLLLL X Illegal

LXXXXX X Invalid

Bank Active

Bank

Activating

Read/Write

Read with

Auto-

precharge/

Write with

Auto-

precharge

H H X X X X X Refer to “Operation Command Table”.

H L X X X X X Begin Clock Suspend next cycle

LXXXXX X Invalid

Clock

Suspend

HXXXXX X Invalid

L H X X X X X Exit Clock Suspend next cycle

L L X X X X X Maintain Clock Suspend

Any State

Other Than

Listed

Above

LXXXXX X Invalid

H H X X X X X Refer to “Operation Command Table“.

HLXXXX X Illegal

MB81E161622-10-X/-12-X

■FUNCTIONAL DESCRIPTION

SDRAM BASIC FUNCTION

Three major differences between SDRAMs and conventional DRAMs are : a synchronized operation, a burst

mode, and a mode register.

The synchronized operation is the fundamental difference. An SDRAM uses a clock input fo r synchronization,

while a DRAM is basically asynchronous memory although it has been using two clocks, RAS and CAS. Each

operation of a DRAM is determined by their timing phase differences while each operation of the SDRAM is

deter mined by commands and all operations are referenced to a rising edge of a clock. Fig 2 shows the basic

timing diagram differences between SDRAMs and DRAMs.

The burst mode is a very high speed access mode utilizing an internal column address generator. Once a column

address for the first access is set, following addresses are automatically generated by the internal column address

counter.

The mode register is to configure the SDRAM operation and function into desired system conditions . “■ MODE

programming.

FCRAMTM

The MB81E161622 utilizes FCRAM core technolog y. The FCRAM is an acronym f or Fast Cycle Random Access

Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.

CLOCK (CLK) and CLOCK ENABLE (CKE)

All input and output signals of the SDRAM use register type buffers. A CLK is used as a trigger for the register

and internal burst counter increment. All inputs are latched by a rising edge of a CLK. All outputs are v alidated

by the CLK. A CKE is a high activ e clock enab le signal. When CKE = Low is latched at a clock input during active

cycle, the next clock will be internally masked. During idle state (all banks have been precharged ) , the Power

Down mode (standby) is entered with CKE = Low and this will make extremely low standby current.

CHIP SELECT (CS)

A CS enab les all command inputs, RAS, CAS, WE and address inputs. When the CS is High, command signals

are negated but internal operations such as a burst cycle will not be suspended. If such a control isn’t needed,

the CS can be tied to ground level.

COMMAND INPUT (RAS, CAS and WE)

Unlike a conventional DRAM, RAS, CAS, and WE do not directly imply SDRAM operations, such as Row address

strobe by RAS . Instead, each combination of RAS, CAS, and WE inputs in conjunction with CS input at the rising

edge of the CLK determines SDRAM operations. Refer to “■ FUNCTIONAL TRUTH TABLE.”

ADDRESS INPUT (A0 to A10)

Address input selects an arbitrary location of a total of 524,288 words of each memor y cell matrix. A total of

nineteen address input signals are required to decode such a matrix. The SDRAM adopts an address multiplexer

in order to reduce the pin count of the address line. At a Bank Activ e command (A CTV) , ele v en Row addresses

are initially latched and the remainder of eight Column addresses are then latched by a Column address strobe

command of either a Read command (READ or READA) or a Write command (WRIT or WRITA) .

BANK SELECT (BA)

This SDRAM has two banks and each bank contains 512 K words by 16-bit.

Bank selection by A11 occurs at Bank Activ e command (ACTV) f ollowed by read (READ or READA) , write (WRIT

or WRITA) , and precharge commands (PRE or PALL) .

MB81E161622-10-X/-12-X

DATA INPUTS AND OUTPUTS (DQ0 to DQ15)

Input data is latched and written into the memory at the clock following the write command input. Data output is

obtained by the following conditions followed by a read command input :

tRAC : from the bank active command when tRCD (Min.) is satisfied. (This parameter is reference only.)

tCAC : from the read command when tRCD is greater than tRCD (Min.) at CL = 1.

tAC : from the clock edge after tRAC and tCAC.

The polarity of the output data is identical to that of input data. Data is valid between access time (determined

by the three conditions above) and the next positive clock edge (tOH) .

DATA I/O MASK (DQML/DQMU)

DQML and DQMU are an activ e high enable input and ha v e an output disab le and input mask functions. During

burst cycle and when DQML/DQMU = High is latched b y a clock, input is masked at the same clock and output

will be masked at the second clock later while internal burst counter will increment by one or will go to the next

stage depending on the burst type.

BURST MODE OPERATION

The burst mode provides faster memory access. The burst mode is implemented by keeping the same Row

address and by automatically strobing column address. Access time and cycle time of Burst mode is specified

as tCAC/tAC and tCK, respectively. The internal column address counter operation is determined by a mode register

which defines burst type and the b urst count length of 1, 2, 4 or 8 bits of boundary. In order to terminate or move

from the current burst mode to the next stage while the remaining burst count is more than 1, the following

combinations will be required :

BURST TYPE

The burst type can be selected either sequential or interleave mode if bu rst length is 2, 4 or 8. The sequential

mode is an incremental decoding scheme within a boundary address to be determined by count length, it assigns

+1 to the previous (or initial) address until reaching the end of boundary address and then wraps around to the

least significant address ( = 0) . The interleave mode is a scrambled decoding scheme for A0 through A2. If the

first access of column address is even (0) , the next address will be odd (1) , or vice-versa.

Current Stage Next Stage Method (Assert the following command)

Burst Read Burst Read Read Command

Burst Read Burst Write 1st Step Mask Command (Normally 3 clock cycles)

2nd Step Write Command after lOWD

Burst Write Burst Write Write Command

Burst Write Burst Read Read Command

Burst Read Precharge Precharge Command

Burst Write Precharge Precharge Command

MB81E161622-10-X/-12-X

FULL COLUMN BURST AND BU RST STOP COMMAND (BST)

The full column burst is an option of burst length and available only at sequential mode of burst type. This full

column burst mode is repeatedly access to the same row. If burst mode reaches the end of column address,

then it wraps around to the first column address ( = 0) and continues to count until interrupted by the new read

(READ) /write (WRIT) , precharge (PRE) , or burst stop (BST) commands. The selection of Auto-precharge

option is illegal during the full column burst operation.

The BST command is applicable to terminate the burst operation. If the BST command is asserted dur ing the

burst mode, its operation is terminated immediately and the internal state moves to Bank Active.

When a read mode is interrupted by the BST command, the output will be in High-Z.

For the detailed rule, please refer to “TIMING DIAGRAM-8” in section “■ TIMING DIAGRAMS.”

When a write mode is interr upted by the BST command, the data to be applied at the same time with the BST

command will be ignored.

PRECHARGE AND PRECHARGE OPTION (PRE, PALL)

The SDRAM memory core is the same as a conv entional DRAM’s, requiring precharge and refresh operations.

Precharge rewrites the bit line and reset the internal Row address line and is executed by the Precharge command

(PRE) . With the Precharge command, the SDRAM will automatically be in standby state after precharge time

(tRP) .

The precharged bank is selected by combination of AP and BA when the Precharge command is asserted. If

AP = High, all banks are precharged regardless of BA (PALL) . If AP = Low, a bank to be selected by A11 is

precharged (PRE) .

The auto-precharge enters precharge mode at the end of burst mode of read or write without the Precharge

command assertion.

This auto precharge is entered by AP = High when a read or write command is asser ted. Refer to “■ FUNC-

TIONAL TRUTH TABLE.”

Burst

Length

Starting Column

Address

A2 A1 A0Sequential Mode Interleave Mode

2X X 0 0 − 10 − 1

X X 1 1 − 01 − 0

X 0 0 0 − 1 − 2 − 30 − 1 − 2 − 3

X 0 1 1 − 2 − 3 − 01 − 0 − 3 − 2

X 1 0 2 − 3 − 0 − 12 − 3 − 0 − 1

X 1 1 3 − 0 − 1 − 23 − 2 − 1 − 0

0 0 0 0 − 1 − 2 − 3 − 4 − 5 − 6 − 70 − 1 − 2 − 3 − 4 − 5 − 6 − 7

0 0 1 1 − 2 − 3 − 4 − 5 − 6 − 7 − 01 − 0 − 3 − 2 − 5 − 4 − 7 − 6

0 1 0 2 − 3 − 4 − 5 − 6 − 7 − 0 − 12 − 3 − 0 − 1 − 6 − 7 − 4 − 5

0 1 1 3 − 4 − 5 − 6 − 7 − 0 − 1 − 23 − 2 − 1 − 0 − 7 − 6 − 5 − 4

1 0 0 4 − 5 − 6 − 7 − 0 − 1 − 2 − 34 − 5 − 6 − 7 − 0 − 1 − 2 − 3

1 0 1 5 − 6 − 7 − 0 − 1 − 2 − 3 − 45 − 4 − 7 − 6 − 1 − 0 − 3 − 2

1 1 0 6 − 7 − 0 − 1 − 2 − 3 − 4 − 56 − 7 − 4 − 5 − 2 − 3 − 0 − 1

1 1 1 7 − 0 − 1 − 2 − 3 − 4 − 5 − 67 − 6 − 5 − 4 − 3 − 2 − 1 − 0

MB81E161622-10-X/-12-X

AUTO-REFRESH (REF)

The Auto-refresh uses the internal refresh address counter. The SDRAM Auto-refresh command (REF) gener-

ates the Precharge command internally. All banks of the SDRAM should be precharged prior to the Auto-refresh

command. The A uto-refresh command should also be asserted ev ery 7.8 µs or a total 4096 refresh commands

within a 32 ms period.

MODE REGISTER SET (MRS)

The mode register of the SDRAM provides a v ariety of operations. The register consists of three operation fields;

Burst Length, Burst Type, and CAS latency. Refer to “■ MODE REGISTER TABLE.”

The mode register can be programmed by the Mode Register Set command (MRS) . Each field is set by the

address line. Once a mode register is prog rammed, the contents of the register will be held until re-programmed

by another MRS command (or part loses power) . The MRS command should be issued only when DQ is in

High-Z.

The condition of the mode register is undefined after the power-up stage. It is required to set each field after

initialization of the SDRAM. Refer to “POWER-UP INITIALIZATION” below.

POWER-UP INITIALIZATION

The SDRAM inter nal condition after power-up will be undefined. It is required to follow the following Power On

Sequence to execute read or write operation.

1. Apply the po w er and start the clock. Attempt to maintain either the NOP or DESL command at the input.

2. Maintain stable power, stable clock, and NOP condition for a minimum of 100 µs.

3. Precharge all banks by the Precharge (PRE) or Precharge All command (PALL) .

4. Assert minimum of 2 Auto-refresh commands (REF) .

5. Program the mode register by the Mode Register Set command (MRS) .

In addition, it is recommended that DQM and CKE track VCC to insure that output is High-Z state. The Mode

MB81E161622-10-X/-12-X

CLK

CKE

RAS

CAS

RAS

CAS

HH H

tHItSI

Address

Active Read/Write Precharge

H : Read

RA BA

Burst Length = 4

Row Address Select Column Address Select Precharge

L : Write

CAS Latency = 2 BA

AP (A10)

Fig. 2 −

−−

− BASIC TIMING FOR CONVENTIONAL DRAM vs. SYNCHRONOUS DYNAMIC RAM

< SDRAM >

< Conventional DRAM >

MB81E161622-10-X/-12-X

QQ Q Q Q

012345678910

ACT RD PRE ACT RD PRE ACT

ACT RDA ACT RDA ACT RDA ACT RDA ACT RDA ACT

tRC = 75 ns tRAC = 36 ns

tRC = 30 ns tRAC = 25 ns

SDRAM

tRC = 5 clock

CL = 2

SDR FCRAM

tRC = 2 clock

CL = 1

QQQ

012345678910

ACT RD PRE ACT RD PRE

ACT RD PRE ACT RD PRE ACT RD PRE ACT RD

tRC = 60 ns tRAC = 37 ns

tRC = 30 ns tRAC = 26 ns

SDRAM

tRC = 6 clock

CL = 2

SDR FCRAM

tRC = 3 clock

CL = 2

Example of Random Cycle Operation @ 67 MHz

Example of Random Cycle Operation @ 100 MHz

Fig. 3 −

−−

− TIMING COMPARISON BETWEEN SDRAM AND SDR FCRAM

MB81E161622-10-X/-12-X

MRS

AUTO

REFRESH

REF

CKE

CKE\

(PD)

ACTV

CKE\ (CSUS)

CKE BST BST

WRIT WRIT READ READ

CKE

WRITA

WRITA WRITA

READA

READ

READA READA

WRIT

CKE\ (CSUS) CKE\ (CSUS)

CKE\ (CSUS)

PRE or PALL

PRE

PALL

PRE or PALL

PRE

PALL

MODE

SET IDLE

POWER

DOWN

BANK

ACTIVE

BANK

ACTIVE

SUSPEND

WRITE

WRITE WITH

AUTO

PRECHARGE

READ WITH

AUTO

PRECHARGE

WRITE

SUSPEND

WRITE

SUSPEND

POWER

APPLIED

PRECHARGE

READ READ

SUSPEND

READ

SUSPEND

Manual

Input Automatic

Sequence

DEFINITION OF ALLOWS

Fig. 4 −

−−

− STATE DIAGRAM (Simplified for Single BANK Operation State Diagram)

Note: CKE\ means CKE goes Low-level from High-level

MB81E161622-10-X/-12-X

■BANK OPERATION COMMAND TABLE

•

••

• MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION

*1:Assume all banks are in idle state.

*2:Assume output is in High-Z state.

*3:Assume tRAS (Min.) is satisfied.

*4:Assume no I/O conflict.

Second

command

(same

bank) MRS ACTV READ

READA WRIT

WRITA PRE PALL REF BST

First

command

MRS tRSC tRSC tRSC tRSC tRSC tRSC

ACTV tRCD tRCD tRCD tRCD tRAS tRAS 1

READ 11*4

1*4

1*3

1 1

READA *1

CL + BL CL + BL-1

CL + BL-1

WRIT tWR tWR 11*3

tDPL

tDPL 1

WRITA *1

BL-1 + tDAL BL-1 + tDAL

BL-1 + tDAL

PRE

*1, *2

tRP tRP 1*3

1*1

tRP 1

PALL

tRP tRP 11tRP 1

REF tREFC tREFC tREFC tREFC tREFC tREFC

Illegal Command.

MB81E161622-10-X/-12-X

•

••

• MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION

*1:Assume all banks are in idle state.

*2:Assume output is in High-Z state.

*3:tRRD (Min.) of other bank (the second command will be asserted) is satisfied.

*4:Assume other bank is in active, read or write state.

*5:Assume tRAS (Min.) is satisfied.

*6:Assume other banks are not in READA/WRITA state.

*7:Assume no I/O conflict.

Second

command

(other

bank)MRS ACTV

READ

*4, *5

READA

WRIT

*4, *5

WRITA PRE PALL REF BST

First

command

MRS tRSC tRSC tRSC tRSC tRSC tRSC

ACTV *1

tRRD

1*6

1*5, *6

1*6

tRAS 1

READ *1, *3

111*7

1*7

1*5

READA *1

CL + BL

*1, *3

1*5

1*5, *7

1*5

CL + BL-1

WRIT *1, *3

11111*5

1*5

tDPL 1

WRITA *1

BL-1 + tDAL

*1, *3

1*5

BL-1 + tDAL

PRE *1, *2

tRP

*1, *3

1*6

1*5, *6

1*6

1*1

tRP 1

PALL *2

tRP tRP 11tRP 1

REF tREFC tREFC tREFC tREFC tREFC tREFC

Illegal Command.

MB81E161622-10-X/-12-X

■MODE REGISTER TABLE

MODE REGISTER SET

BA A10 A9A8A7A6A5A4A3A2A1A0ADDRESS

0 0000 CL BT BL MODE

*: BL = 1 and Full Column are not applicable to the interleave mode.

A6A5A4CAS Latency

Reserved

A2A1A0Burst Length

BT =

= 0 BT =

= 1 *

Reserved

Full Column

Reserved

A3Burst Type

1Sequential (Wrap around, Binary-up)

Interleave (Wrap around, Binary-up)

MB81E161622-10-X/-12-X

■ABSOLUTE MAXIMUM RATINGS

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■RECOMMENDED OPERATING CONDITIONS

*1 : All voltages are referenced to VSS.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

Parameter Symbol Rating Unit

Min. Max.

Voltage of VCC Supply Relative to VSS VCC, VCCQ −0.5 to +4.6 V

Voltage at Any Pin Relative to VSS VIN, VOUT −0.5 to +4.6 V

Short Circuit Output Current IOUT −50 to +50 mA

Power Dissipation PD1.3 W

Storage Temperature TSTG −55 to +125 °C

Parameter Symbol Value Unit

Min. Typ. Max.

Supply Voltage *1 VCC, VCCQ 3.0 3.3 3.6 V

VSS, VSSQ 000V

Input High Voltage *2 VIH 2.0 VCC + 0.5 V

Input Low Voltage *3 VIL −0.5 +0.8 V

Ambient Temperature Ta −40 +85 °C

4.6 V

VIH

VIL Pulse width < 5 ns

VIH Min.

50% of pulse amplitude

−1.5 V

VIH

VIL

Pulse width < 5 ns

VIL Max.

50% of pulse amplitude

*2:Overshoot limit :

VIH (Max.) = 4.6 V for pulse width ≤ 5 ns acceptable,

pulse width measured at 50% of pulse amplitude.

*3:Undershoot limit :

VIL (Min.) = VSS − 1.5 V for pulse width ≤ 5 ns acceptable,

pulse width measured at 50% of pulse amplitude.

MB81E161622-10-X/-12-X

■PIN CAPACITANCE (Ta = +25 °C, f = 1 MHz)

Parameter Symbol Value Unit

Min. Typ. Max.

Input Capacitance, Except for CLK CIN1 2.5 5.0 pF

Input Capacitance for CLK CIN2 2.5 4.0 pF

I/O Capacitance CI/O4.0 6.5 pF

MB81E161622-10-X/-12-X

■ELECTRICAL CHARACTERISTICS

1. DC Characteristics

(At recommended operating conditions unless otherwise noted.)

(Continued)

Parameter Symbol Condition Value Unit

Min. Max.

Output High Voltage VOH (DC) IOH = −2 mA 2.4 V

Output Low Voltage VOL (DC) IOL = 2 mA 0.4 V

Input Leakage Current (Any Input) ILI 0 V ≤ VIN ≤ VCC;

All other pins not under

test = 0 V −5+5µA

Output Leakage Current ILO 0 V ≤ VIN ≤ VCC;

Data out disabled −5+5µA

Operating Current

(Average Power

Supply Current)

MB81E161622-10-X

ICC1

Burst Length = 4

tRC = Min. for BL = 4

tCK = Min.

One bank active

Output pin open

Addresses changed up to

one time during tCK (Min.)

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC



130

MB81E161622-12-X 120

Precharge Standby Current

(Power Supply Current)

ICC2P

CKE = VIL

All banks idle, tCK = Min.

Power down mode

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

0.6 mA

ICC2PS

CKE = VIL, All banks idle

CLK = VIH or VIL

Power down mode

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

0.6 mA

Precharge Standby Current

(Power Supply Current)

ICC2N

CKE = VIH , All banks idle

tCK = 15 ns

NOP command only,

Input signals (except to

CMD) are changed one

time during 30 ns

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

20 mA

ICC2NS

CKE = VIH

All banks idle

CLK = VIH or VIL

Input signal are stable

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

2mA

MB81E161622-10-X/-12-X

(Continued)

Notes: • All voltages are referenced to VSS.

• DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.

• ICC depends on output termination, load conditions, clock rate, number of address and/or command change

within certain period. The specified values are obtained with the output open.

Parameter Symbol Condition Value Unit

Min. Max.

Active Standby Current

(Power Supply Current)

ICC3P

CKE = VIL

Any bank active

tCK = Min.

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

1mA

ICC3PS

CKE = VIL

Any bank active

CLK = VIH or VIL

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

1mA

ICC3N

CKE = VIH

Any bank active

tCK = 15 ns

NOP command only,

Input signals (except to

CMD) are changed one

time during 30 ns

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

20 mA

ICC3NS

CKE = VIH

Any bank active

CLK = VIH or VIL

Input signals are stable

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

2mA

Burst mode Current

(Average Power

Supply Current)

MB81E161622-10-X

ICC4

tCK = Min.

Burst Length = 4

Output pin open

All-banks active

Gapless data

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC



100

MB81E161622-12-X 90

Refresh Current #1

(Average Power

Supply Current)

MB81E161622-10-X ICC5

Auto-refresh;

tCK = Min.

tREFC = Min.

0 V ≤ VIN ≤ VIL Max.

VIH Min. ≤ VIN ≤ VCC

80 mA

MB81E161622-12-X 70

MB81E161622-10-X/-12-X

2. AC Characteristics

(At recommended operating conditions unless otherwise noted.) *1, *2, and *3

Parameter Symbol MB81E161622-

10-X MB81E161622-

12-X Unit

Min. Max. Min. Max.

Clock Period CL = 1t

CK1 15 20 ns

CL = 2t

CK2 10 12 ns

Clock High Time *4 tCH 34ns

Clock Low Time *4 tCL 34ns

Input Setup Time *4 tSI 22ns

Input Hold Time except for CKE *4 tHI 11.5 ns

RAS Access Time *5 tRAC 25 34 ns

CAS Access Time *4, *6 tCAC 10 14 ns

Access Time from Clock

(tCK = Min.) *4, *6, *7 CL = 1t

AC1 10 14 ns

CL = 2t

AC2 67ns

Output in Low-Z *4 tLZ 00ns

Output in High-Z *4, *8 CL = 1tHZ1 1.5 10 1.5 14 ns

CL = 2t

HZ2 67ns

Output Hold Time *4, *6 tOH 1.5 1.5 ns

Time between Auto-Refresh command interval *5 tREFI 7.8 7.8 µs

Time between Refresh tREF 32 32 ms

Transition Time *4 tT0.5 10 0.5 10 ns

CKE Setup Time for Power Down

Exit Time *4 tCKSP 33ns

MB81E161622-10-X/-12-X

BASE VALUES FOR CLOCK COUNT/ LATENCY

CLOCK COUNT FORMULA *10

Parameter Symbol

MB81E161622

Unit-10-X -12-X

Min. Max. Min. Max.

RAS Cycle Time *9 tRC 30 36 ns

RAS Precharge Time tRP 10 12 ns

RAS Active Time tRAS 15 110000 20 110000 ns

RAS to CAS Delay Time tRCD 10 12 ns

Write Recovery Time tWR 10 12 ns

RAS to RAS Bank Active Delay Time tRRD 10 12 ns

Data-in to Precharge Lead Time tDPL 10 12 ns

Data-in to Active/

Refresh

Command Period

CL = 1t

DAL1 15 20 ns

CL = 2t

DAL2 20 24 ns

Refresh Cycle Time tREFC 50 60 ns

Mode Resister Set Cycle Time tRSC 10 12 ns

Clock ≥ Base Value

Clock Period (Round up to a whole number)

MB81E161622-10-X/-12-X

LATENCY - FIXED VALUES

(The latency values on these parameters are fixed regardless of clock period.)

*1:AC characteristics are measured after following the POWER-UP INITIALIZATION procedure.

*2:AC characteristics assume tT = 1 ns and 50 Ω of terminated load.

*3:1.4 V is the reference level for measuring timing of input signals. Transition times are measured between

VIH (Min.) and VIL (Max.) . Refer to Fig. 5.

*4:If input signal transition time (tT) is longer than 1 ns; [ (tT / 2) − 0.5] ns should be added to tCAC (Max.) , tAC (Max.) ,

tHZ (Max.) , and tCKSP (Min.) spec v alues, [ (tT / 2) − 0.5] ns should be subtracted from tLZ (Min.) , tHZ (Min.) , and

tOH (Min.) spec v alues, and (tT − 1.0) ns should be added to tCH (Min.) , tCL (Min.) , tSI (Min.) , and tHI (Min.) spec

values.

*5:This value is for reference only.

*6:Measured under AC test load circuit shown in Fig. 4.

*7:tAC also specifies the access time at burst mode except for first access at CL = 1.

*8:Specified where output buffer is no longer driven.

*9:tRC (Min.) is not sum of tRAS (Min.) and tRP (Min.) . Actual clock count of tRC (lRC) must satisfy tRC (Min.) , tRAS (Min.)

and tRP (Min.) .

*10:All base values are measured from the clock edge at the command input to the clock edge for the next command

input. All clock counts are calculated by a simple formula : clock count equals base value divided by clock period

(round up to a whole number) .

Parameter Symbol MB81E161622

-10-X MB81E161622

-12-X Unit

CKE to Clock Disable lCKE 1 1 cycle

DQM to Output in High-Z lDQZ 2 2 cycle

DQM to Input Data Delay lDQD 0 0 cycle

Last Output to Write Command Delay lOWD 2 2 cycle

Write Command to Input Data Delay lDWD 0 0 cycle

Precharge to Output in High-Z Delay CL = 1l

ROH1 1 1 cycle

CL = 2lROH2 2 2 cycle

Burst Stop Command to Output in High-Z Delay CL = 1l

BSH1 1 1 cycle

CL = 2l

BSH2 2 2 cycle

CAS to CAS Delay (Min.) lCCD 1 1 cycle

CAS Bank Delay (Min.) lCBD 1 1 cycle

MB81E161622-10-X/-12-X

Output R1 = 50 Ω1.4 V

CL = 30 pF

Fig. 5 −

−−

− OUTPUT LOAD CIRCUIT

LVTTL

MB81E161622-10-X/-12-X

2.4 V

0.4 V

1.4 V

1.4 V 2.4 V

2.4 V

0.4 V

1.4 V

tCK

tCH

tSI tHI

tAC

tLZ

tHZ

tOH

tCL

CLK

Output

Input

(Control,

Addr. & Data)

Note : Reference level of input signal is 1.4 V for LVTTL.

Access time is measured at 1.4 V for LVTTL.

AC characteri stics are also measured in this condition.

Fig. 6 −

−−

− TIMING DIAGRAM, SETUP, HOLD AND DELAY TIME

CLK

CKE

tCKSP (Min.)

NOP NOP ACTV

Command

H or L

1 clock (Min.)

Fig. 7 −

−−

− TIMING DIAGRAM, DELAY TIME FOR POWER DOWN EXIT

MB81E161622-10-X/-12-X

tRC, tRP, tRAS, tRCD, tWR, tREFI, tREFC,

tDPL, tDAL, tRSC, tRRD, tCKSP

CLK

Input

(Control) Command Command

Fig. 8 −

−−

− TIMING DIAGRAM, PULSE WIDTH

Note : These parameters are a limit value of the rising edge of the clock from one command input to the

next input. tCKSP is the latency value from the rising edge of the CKE.

Measurement reference voltage is 1.4 V.

CLK

RAS

CAS

(Output)

tAC

tRCD

tRAC

tAC tAC

1 clock at CL = 2

Q (Valid) Q (Valid) Q (Valid)

tCAC

Fig. 9 −

−−

− TIMING DIAGRAM, ACCESS TIME

MB81E161622-10-X/-12-X

■TIMING DIAGRAMS

lCKE (1 clock) lCKE (1 clock)

CLK

CKE

CLK

(Internal)

(Read)

(Write) D1 D2 NOT

WRITTEN

NOT

WRITTEN D3 D4

Q1 Q2 (NO CHANGE) (NO CHANGE)Q3 Q4

*1*1

*2*2

tSI tHI tSI tHI tSI tHI

TIMING DIAGRAM −

−−

− 1 : CLOCK ENABLE - READ AND WRITE SUSPEND (@ BL =

= 4)

*1:The latency of the CKE (lCKE) is one clock.

*2:During the read mode, burst counter will not be incremented/decremented at the ne xt clock of the CSUS

command. Output data remains the same data.

*3:During the write mode, data at the next clock of the CSUS command is ignored.

CLK

CKE

Command

tCKSP (Min.) 1 clock (Min.)

tREF (Max.)

NOP PD (NOP) H or L NOP NOP ACTV *4

TIMING DIAGRAM −

−−

− 2 : CLOCK ENABLE - POWER DOWN ENTRY AND EXIT

*1:The Precharge command (PRE or PALL) should be asserted if any bank is active and in the burst mode.

*2:The Precharge command can be posted in conjunction with CKE after the last read data has been appeared

on DQ.

*3:It is recommended to apply the NOP command in conjunction with CKE.

*4:The ACTV command can be latched after tCKSP (Min.) + 1 clock (Min.) .

MB81E161622-10-X/-12-X

CLK

RAS

CAS

Address

tRCD (Min.) lCCDlCCD

lCCD

(1 clock)

ROW

ADDRESS COLUMN

ADDRESS

lCCD

TIMING DIAGRAM −

−−

− 3 : COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY

Note : CAS to CAS delay can be one or more clock period.

Address

CLK

RAS

CAS

A11 (BA)

tRCD (Min.) or more

tRCD (Min.)

tRRD (Min.)

lCBD

(1 clock) lCBD

Bank 1Bank 0Bank 1Bank 1 Bank 0Bank 0

ROW

ADDRESS ROW

ADDRESS COLUMN

ADDRESS

TIMING DIAGRAM −

−−

− 4 : DIFFERENT BANK ADDRESS INPUT DELAY

Note : CAS Bank delay can be one or more clock period.

MB81E161622-10-X/-12-X

CLK

DQML, DQMU

(@ Read)

DQML, DQMU

(@ Write)

(@ Write) D1

Q1 Q2

IDQZ (2 clocks)

D4D3MASKED

High-Z End of burst

End of burst

IDQD (same clock)

TIMING DIAGRAM −

−−

− 5 : DQMU, DQML - INPUT MASK AND OUTPUT DISABLE (@ BL =

= 4)

CLK

Command ACTV PRECHARGE

tRAS (Min.)

TIMING DIAGRAM −

−−

− 6 : PRECHARGE TIMING (APPLIED TO THE SAME BANK)

Note : PRECHARGE means ‘PRE’ or ‘PALL’.

MB81E161622-10-X/-12-X

High-Z

CLK

Command

PRECHARGE

IROH (2 clocks)

No effect (end of burst)

Q1 Q2

Q1 Q2 Q3 Q4

Q1 High-Z

High-Z

PRECHARGE

TIMING DIAGRAM −

−−

− 7 : READ INTERRUPTED BY PRECHARGE (EXAMPLE @ CL =

= 2, BL =

= 4)

Notes : In case of CL = 1, the lROH is 1 clock.

In case of CL = 2, the lROH is 2 clocks.

PRECHARGE means ‘PRE’ or ‘PALL’.

MB81E161622-10-X/-12-X

BST

QnQn − 2 Qn − 1

BST

QnQn − 2 Qn − 1 Qn + 1

IBSH (2 clocks)

IBSH (1 clock)

CLK

Command

(CL = 1)

Command

(CL = 2)

High-Z

TIMING DIAGRAM −

−−

− 8 : READ INTERRUPTED BY BURST STOP (EXAMPLE @ BL =

= Full Column)

BST COMMAND

CLK

Command

DQ LAST DnMasked

by BST

TIMING DIAGRAM −

−−

− 9 : WRITE INTERRUPTED BY BURST STOP (EXAMPLE @ BL = 2)

MB81E161622-10-X/-12-X

CLK

Command

PRECHARGE ACTV

tDPL (Min.)

Dn − 1 LAST DnMASKED

by Precharge

tRP (Min.)

TIMING DIAGRAM −

−−

− 10 : WRITE INTERRUPTED BY PRECHARGE

Note : The precharge command (PRE) should be issued only after the tDPL of final data input is satisfied.

PRECHARGE means ‘PRE’ or ‘PALL’.

CLK

Command

DQM

(DQML, DQMU)

READ WRIT

IDQZ (2 clocks)

IOWD (2 clocks)

IDWD (same clock)

Q1Masked D1D2

*1*2*3

TIMING DIAGRAM −

−−

− 11 : READ INTERRUPTED BY WRITE (EXAMPLE @ CL =

= 2, BL =

= 4)

*1:The First DQM makes high-impedance state High-Z between the last output and the first input data.

*2:The Second DQM makes internal output data mask to avoid bus contention.

*3:The Third DQM in illustrated above also makes internal output data mask. If burst read ends (the final

data output) at or after the second clock of burst write, this third DQM is required to avoid internal bus

contention.

MB81E161622-10-X/-12-X

CLK

Command

DQM

(DQML, DQMU)

WRIT READ

D1 D2 D3

Masked

by READ

Q3Q2Q1

tWR (Min.)

tACtAC

tCAC (Max.) tAC

TIMING DIAGRAM −

−−

− 12 : WRITE TO READ TIMING (EXAMPLE @ CL =

= 1, BL =

= 4)

Notes : The Read command should be issued after tWR of the final data input is satisfied.

The write data after the READ command is masked by the READ command.

ACTV

CLK

Command

DQM

(DQML, DQMU)

CL + BL − 1 *

ACTV

READA

Q1 Q2

NOP or DESL

TIMING DIAGRAM −

−−

− 13 : READ WITH AUTO-PRECHARGE

(EXAPLE @ CL =

= 2, BL =

= 2 Applied to same bank)

*: The Next ACTV command should be issued after CL + BL − 1 from the READA command.

MB81E161622-10-X/-12-X

ACTV

CLK

Command

DQM

(DQML, DQMU)

tDAL (Min.)

(BL − 1) + tDAL*4

ACTV

WRITA

D1 D2

NOP or DESL

TIMING DIAGRAM −

−−

− 14 : WRITE WITH AUTO-PRECHARGE *1, *2, *3

(EXAMPLE @ CL =

= 2, BL =

= 2 Applied to same bank)

*1:If the final data is masked by DQM, the precharge does not start at the clock of the final data input.

*2:Once the auto precharge command is asserted, no new command within the same bank can be issued.

*3:The Auto-precharge command can not be invoked at full column burst operation.

*4:The Next command should be issued after (BL − 1) + tDAL from the WRITA command.

REF *1REFNOP *3NOP *4

tREFC (Min.) tREFC (Min.)

NOP NOP Command *4

CLK

Command

BA H or L*2BA

H or L*2

TIMING DIAGRAM −

−−

− 15 : AUTO-REFRESH TIMING

*1:All banks should be precharged prior to the first Auto-refresh command (REF) .

*2:Bank select is ignored at the REF command. The refresh address and bank select are selected by the

internal refresh counter.

*3:Either the NOP or DESL command should be asserted within tRC period during Auto-refresh mode.

*4:Any activ ation command such as the A CTV or MRS commands other than the REF command should be

asserted after tREFC from the last REF command.

MB81E161622-10-X/-12-X

ACTVMRS NOP or DESL

ROW

ADDRESS

MODE

tRSC (Min.)

CLK

Command

Address

TIMING DIAGRAM −

−−

− 16 : MODE REGISTER SET TIMING

Note : The Mode Register Set command (MRS) should be asserted only after all banks have been

precharged and DQ is in High-Z.

MB81E161622-10-X/-12-X

■ORDERING INFORMATION

Part Number Package Remarks

MB81E161622-10FH-X

MB81E161622-12FH-X 54 pin, Plastic TSOP (II)

(FPT-54P-M02)

MB81E161622-10-X/-12-X

■PACKAGE DIMENSION

54-pin plastic TSOP (II)

(FPT-54P-M02) Note1)Resin protrusion. (Each side : 0.15 (.006) MAX)

Note2)Pins width and pins thickness include plating thickness.

Dimensions in mm (inches)

2000 FUJITSU LIMITED F54003S-c-2-3

54 28

1 27

INDEX

0.16(.006)

0.10(.004) 0.10±0.05

(.004±.002)

11.76±0.20(.463±.008)

10.16±0.10(.400±.004)

Details of "A" part

LEAD No.

1.15±0.05

(.045±.002)

.013 –.003

+.003

–0.07

+0.08

0.32 (Mounting height)

0.80(.031)

(Stand off)

.006 –.001

+.002

–0.03

+0.05

0.145

"A"

0.45/0.75

(.018/.030)

0.25(.010)

0°~8°

20.80(.819)REF

22.22±0.10(.875±.004)

MB81E161622-10-X/-12-X

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0112

 FUJITSU LIMITED Printed in Japan