LM3450AMT/NOPB - NATIONAL SEMICONDUCTOR

LM3450

LM3450 LM3450A LED Drivers with Active Power Factor Correction and

Phase Dimming Decoder

Literature Number: SNVS681C

LM3450

LM3450A

June 20, 2011

LED Drivers with Active Power Factor Correction and

Phase Dimming Decoder

General Description

The LM3450/50A is a power factor controller (PFC) with sep-

arate phase dimming decoder. The PFC regulates the output

voltage while maintaining excellent power factor. The phase

dimming decoder interprets the phase angle and remaps it to

a 500Hz PWM output. This device is ideal for implementing a

dimmable off-line LED driver for 10-100W loads.

The phase dimming decoder has several unique features.

The input-output mapping is programmable for design flexi-

bility, while a dynamic filter and variable sampling rate provide

smooth uniform dimming. A dynamic hold circuit ensures that

the phase dimmer angle is decoded properly while minimizing

extra power loss.

The LM3450A is identical to the LM3450 with the exception

of one circuit operation. The dynamic hold current is sampled

in the LM3450 while it continuously operates in the LM3450A.

This difference between the two devices defines the suitable

applications for each. The following is a general guideline for

choosing the correct device:

•Any 120V designs with POUT > 15W - LM3450A

•Any 230V designs with POUT > 25W - LM3450A

•120V 2-Stage designs with POUT < 15W - LM3450

•230V 2-Stage designs with POUT < 25W - LM3450

Features

■Critical conduction mode PFC

■Over-voltage protection

■Feedback short circuit protection

■70:1 PWM decoded from phase dimmer

■Analog dimming

■Programmable dimming range

■Digital angle and dimmer detection

■Dynamic holding current

■Smooth dimming transitions

■Low power operation

■Start-up pre-regulator bias

■Precision voltage reference

Applications

■Dimmable downlights, troffers, and lowbays

■Large form factor bulbs

■Indoor and outdoor area SSL

■Power supply PFC

Typical Application

30127401

LM3450 LM3450A LED Drivers with Active Power Factor Correction and Phase Dimming Decoder

Connection Diagram

Top View

30127402

16-Lead TSSOP

NS Package Number MTC16

Ordering Information

Order Number Spec. Package Type NSC Package

Drawing Supplied As

LM3450MT NOPB TSSOP-16 MTC16 92 Units, Rail

LM3450MTX NOPB TSSOP-16 MTC16 2500 Units, Tape and Reel

LM3450AMT NOPB TSSOP-16 MTC16 92 Units, Rail

LM3450AMTX NOPB TSSOP-16 MTC16 2500 Units, Tape and Reel

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LM3450 LM3450A

Pin Descriptions

Pin Name Description Application Information

1VREF 3V Reference Reference Output: Connect directly to VADJ or to resistor divider feeding VADJ and

to necessary external circuits.

2VADJ Analog Adjust

Analog Dim and Phase Dimming Range Input: Connect directly to VREF to force

standard 70% phase dimming range. Connect to resistor divider from VREF to

extend usable range of some phase dimmers or for analog dimming. Connect to

GND for low power mode.

3 FLT2 Filter 2 Ramp Comparator Input: Connect a series resistor from FLT1 capacitor and a

capacitor to GND to establish second filter pole.

4 FLT1 Filter 1 Angle Decoder Output: Connect a series resistor to a capacitor to GND to

establish first filter pole.

5 DIM 500 Hz

PWM Output

Open Drain PWM Dim Output: Connect to dimming input of output stage LED

driver (directly or with isolation) to provide decoded dimming command.

6VAC

Sampled

Rectified Line

Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC

line.

7 COMP Compensation Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND

to set the compensation.

8 FB Feedback

Error Amplifier Inverting Input: Connect to output voltage via resistor divider to

control PFC voltage loop for non-isolated designs. Connect a 5.11kΩ resistor to

GND for isolated designs (bypasses error amplifier). Also includes over-voltage

protection and shutdown modes.

9ISEN

Input Current

Sense

Input Current Sense Non-Inverting Input: Connect to diode bridge return and

resistor to GND to sense input current for dynamic hold. Connect a 0.1µF

capacitor and Schottky diode to GND, and a 0.22µF capacitor to HOLD.

10 GND Power Ground System Ground

11 CS Current Sense MosFET Current Sense Input: Connect to positive terminal of sense resistor in

PFC MosFET source.

12 GATE Gate Drive Gate Drive Output: Connect to gate of main power MosFET for PFC.

13 VCC Input Supply Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass

capacitor to ground.

14 ZCD Zero Crossing

Detector

Demagnetization Sense Input: Connect a 100kΩ resistor to transformer/inductor

winding to detect when all energy has been transferred.

15 HOLD Dynamic Hold Open Drain Dynamic Hold Input: Connect to holding resistor which is connected

to source of passFET.

16 BIAS Pre-regulator

Gate Bias

Pre-regulator Gate Bias Output: Connect to gate of passFET and through resistor

to rectified AC (drain of passFET) to aid with startup.

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LM3450 LM3450A

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

VCC, HOLD, DIM, BIAS -0.3V to 25.0V

HOLD Power 250 mW Continuous

BIAS Current 5.0mA Continuous

ZCD Current +/- 10mA

COMP, FB, VAC, FLT1, FLT2,

VREF, CS, VADJ -0.3V to 7.0V

ISEN -7.0V to 7.0V

GATE -0.3V to 18V Continuous

-2.5V for 100ns

20.5V for 100ns

-1mA to +1mA Continuous

Continuous Power

Dissipation Internally Limited

Maximum Junction

Temperature Internally Limited

Storage Temperature Range -65°C to +150°C

Maximum Lead Temperature

(Solder and Reflow) (Note 2)

260°C

ESD Susceptibility (Note 3)

HBM 2kV

MM 200V

FICDM 750V

Operating Conditions (Note 1)

VCC Range 8.5V to 20V

Junction Temperature Range -40°C to +125°C

Electrical Characteristics (Note 1)

Unless otherwise specified VCC = 14V. Specifications in standard type face are for TJ = 25°C and those with boldface type apply

over the full Operating Temperature Range ( TJ = −40°C to +125°C). Typical values represent the most likely parametric norm

at TA = TJ = +25°C, and are provided for reference purposes only.

Symbol Parameter Conditions Min

(Note 4)

Typ

(Note 5)

Max

(Note 4)Units

SUPPLY VOLTAGE INPUT (VCC)

VCC-RISE Controller Enable Threshold VCC Rising 12.2 13.0 13.6 V

VCC-FALL Controller Disable Threshold VCC Falling 7.4 7.9 8.5

Glitch Filter Delay 9 µs

Turn-on Delay 40

IQVCC Quiescent Current No Switching 1.6 mA

IQ-SD VCC Shutdown Current VFB = 0V 515 625 µA

ERROR AMPLIFIER & COMPENSATION (FB, COMP)

VFB FB Reference (Normal Operation) 2.43 2.50 2.57 V

Input Bias Current VFB = 2.5V 100 nA

GMTransconductance VFB = 2.5V 69 115 161 µS

Output Source / Sink Capability 60 85 110 µA

FB Pull-up Current Source VFB < 1.8V 43 51 59

COMP Pull-up Resistor 5 kΩ

VCMP-B COMP Low Threshold (Burst) VCMP Falling VTHM -0.08 V

COMP Low Hysteresis 20

VFB-SD Low Threshold (Shutdown) VFB Falling 150 168 186

FB Low Hysteresis 20

VFB-EAD FB Mid Threshold (EA Disabled) VFB Falling 328 346 368

FB Mid Hysteresis 20

VFB-OV FB High Threshold (Over-voltage) 1.20 x VFB 1.22 x VFB V

COMP Pre-bias Source Current VCMP = 0.5V 415 µA

VTHM Minimum COMP Voltage (Normal) 1.47 V

ANGLE DEMODULATION & MULTIPLIER (COMP, VAC)

VAC-DET VAC Angle Detection Threshold 334 356 378 mV

Angle Demodulation Delay Time Both edges 8 µs

VAC Dynamic Input Voltage Range 0 to 5.5

COMP Dynamic Input Voltage Range VTHM to VTHM

VAC Input Impedance 500 kΩ

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LM3450 LM3450A

Symbol Parameter Conditions Min

(Note 4)

Typ

(Note 5)

Max

(Note 4)Units

KMMultiplier Gain (Includes Internal

Resistor Divider)

VAC = 3V, VCMP

= VTHM+1.5V 0.5 1/V

ZERO CURRENT DETECTOR (ZCD)

VZCD-RIS ZCD Input Threshold VZCD Rising 1.45 1.5 1.55 V

Hysteresis 150 200 250 mV

Delay to Output 135 ns

VZCD-H Positive Clamp Voltage IZCD = 1mA 6.0 V

VZCD-L Negative Clamp Voltage IZCD = -50µA 0.61

PWM COMPARATOR (CS)

VOS PWM Comparator Input Offset Voltage 30 mV

PWM Comparator Input Bias Current 20 nA

VLIM CS Current Limit Threshold 1.40 1.50 1.60 V

CS Delay to Output 100 ns

CS Blanking Sinking Impedance 1 kΩ

tLEB Leading Edge Blanking (LEB) Time 140 ns

ANALOG ADJUST INPUT (VADJ)

VADJ-LP VADJ Low Threshold (Low Power Mode) VADJ Falling 56 75 mV

VADJ Low Hysteresis 50

VADJ Pull-up Current Source 1 µA

VADJ Open Voltage VADJ Open 3 V

DYNAMIC HOLD CIRCUIT (HOLD, ISEN)

RDSON-HD HOLD MosFET On-Resistance ISEN Short to

GND 22 30 42 Ω

VSEN-REF ISEN Reference Voltage 162 200 232 mV

ISEN Bias Current 5 µA

PRE-REGULATOR GATE DRIVE OUTPUT (BIAS)

VBIAS BIAS High Voltage @ 100µA VCC < VCC-FALL 18.8 21 22.6 V

BIAS Low Voltage @ 100µA VCC > VCC-RISE 13.5 14 14.5

GATE DRIVER OUTPUT (GATE)

VGATE-H GATE Voltage High IGATE = 20mA 11.5 V

IGATE = 200mA 10.5

GATE Pull Down Resistance 2 8Ω

GATE Peak Current (Note 6) ±1.5 A

REFERENCE VOLTAGE OUTPUT (VREF)

VREF Reference Voltage No Load 2.85 33.15 V

Current Limit 1.5 2.0 3.0 mA

DIMMING OUTPUT (DIM, FLT1, FLT2)

FLT1 Output Impedance Standby Mode 500

kΩ

Transition

Mode

1.6

Triangle Waveform Compared to FLT2 High 1.49 V

Low 15 mV

fDIM DIM Frequency 180 460 700 Hz

OFF-TIMERS

tOFF-MAX Maximum Off-Time (Normal Operation) 340 µs

tOFF-LP Off-Time (Low Power Mode) 42

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LM3450 LM3450A

Symbol Parameter Conditions Min

(Note 4)

Typ

(Note 5)

Max

(Note 4)Units

THERMAL SHUTDOWN

Thermal Limit Threshold (Note 6) 160 °C

Thermal Limit Hysteresis 20

THERMAL RESISTANCE

θJA Junction to Ambient TSSOP-16

(Note 6, Note 7)

38.0 °C/W

θJC Junction to Case 10.0

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed and do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical

Characteristics table. All voltages are with respect to the potential at the GND pin, unless otherwise specified.

Note 2: Refer to National’s packaging website for more detailed information and mounting techniques. http://www.national.com/analog/packaging/

Note 3: Human Body Model, applicable std. JESD22-A114-C. Machine Model, applicable std. JESD22-A115-A. Field Induced Charge Device Model, applicable

std. JESD22-C101-C.

Note 4: All limits guaranteed at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100%

production tested. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. All limits are used

to calculate Average Outgoing Quality Level (AOQL).

Note 5: Typical numbers are at 25°C and represent the most likely norm.

Note 6: These electrical parameters are guaranteed by design, and are not verified by test.

Note 7: Junction-to-ambient thermal resistance is highly board-layout dependent. In applications where high maximum power dissipation exists, namely driving

a large MOSFET at high switching frequency from a high input voltage, special care must be paid to thermal dissipation issues during board design. In high-power

dissipation applications, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum

operating junction temperature (TJ-MAX-OP = 125°C for Q1, or 150°C for Q0), the maximum power dissipation of the device in the application (PD-MAX), and the

junction-to ambient thermal resistance of the package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

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LM3450 LM3450A

Typical Performance Characteristics TA=+25°C and VCC = 14V unless otherwise specified

HOLD RDSON vs. Junction Temperature

30127415

Leading Edge Blanking vs. Junction Temperature

30127404

Current Limit Threshold vs. Junction Temperature

VAC = 3V; VCMP = VTHM + 1.5V

30127405

Multiplier Gain vs. Junction Temperature

VAC = 3V; VCMP = VTHM + 1.5V

30127406

Transconductance

VFB = 2.5V; ΔVFB = 50mV

30127407

BIAS Voltage vs. Junction Temperature

High @ VCC < VCCFALL; Low @ VCC > VCCRISE

30127408

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LM3450 LM3450A

VCC UVLO Threshold vs. Junction Temperature

30127409

Shutdown Current vs. Junction Temperature

30127410

VREF Reference vs. Junction Temperature

30127411

FB Reference vs. Junction Temperature

30127412

ISEN Reference vs. Junction Temperature

30127413

VAC Detection Threshold vs. Junction Temperature

30127414

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LM3450 LM3450A

Transconductance vs. VFB

30127416

Current Sense Threshold vs. VCOMP and VAC

30127417

Decoder Mapping from VAC to DIM

0.0 0.2 0.4 0.6 0.8 1.0

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

DIM PIN DUTY CYCLE

DEMODULATED VAC PIN DUTY CYCLE

VADJ=3V

1.5V

0.5V

2.5V

30127419

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LM3450 LM3450A

Block Diagram

30127421

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LM3450 LM3450A

30127422

FIGURE 1. Typical Flyback Application

Theory of Operation

The LM3450/50A is a single device with both power factor

control (PFC) and phase dimming decoder functions. This

device is designed to control isolated flyback converters and

provide active power factor correction. In addition to being a

PFC, the LM3450/50A can interpret a phase dimming (fre-

quently called triac dimming) input and provide a correspond-

ing PWM output to properly dim an LED load. This

combination of features provides an excellent method to con-

vert a standard AC mains input to a dimmable LED output of

10-100W. It should be noted that the LM3450/50A can control

a boost converter in a similar manner. However, this

datasheet will focus mostly on the flyback topology due to the

high demand for isolated LED driver applications. Discussion

of the LM3450/50A functionality will refer to Figure 1 compo-

nent designators.

The PFC control operates in critical conduction mode (CRM)

using zero crossing detection (ZCD) to terminate the off-time.

The PFC portion of this device includes an error amplifier,

multiplier, current sense circuit, zero crossing detector, and

gate driver. The internal error amplifier is used for feedback

of the output voltage in non-isolated designs. However, it can

be disabled for isolated designs where the error amplifier

needs to be on the secondary side.

The phase dimmer decoder detects the dimming angle of the

rectified AC line, decodes, filters and remaps it to a 500Hz

PWM output. The PWM output can then be sent directly, or

through optical isolation, to the dimming input of a second

stage LED driver. To ensure the decoder properly interprets

the dimming angle, dynamic hold is provided which prevents

the phase dimmer from misfiring. The input current is sensed

and when the current drops below a preset minimum, the

system adds more current.

Both the dynamic hold and the decoder are sampled syn-

chronously in the LM3450 to reduce the overall efficiency drop

due to the additional hold current. When a decoding sample

period occurs, the dynamic hold is activated to ensure a prop-

er angle is decoded. Because of this sampling method, non-

sampled cycles will potentially cause the phase dimmer to

misfire but should not affect the output LED current regulation.

For higher power applications, where the dynamic hold pro-

vides much less current on average, the LM3450A can be

used. The LM3450A has continuous dynamic hold which pre-

vents the dimmer from ever misfiring. This is extremely helpful

when designing for single stage solutions, where there is no

second stage to provide good line rejection. The continuous

dynamic hold is also helpful for the higher power two stage

applications where the input capacitance is larger.

One last feature of the phase decoder is a dynamic filter that,

combined with the variable sampling rate, provides fast,

smooth dimming transitions.

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LM3450 LM3450A

30127423

FIGURE 2. PFC System Architecture

PFC BACKGROUND

Power factor (PF) is a number between 0 and 1 that indicates

how well energy is transmitted from input to output of a sys-

tem. It can be described by average power (PAVG), RMS

voltage (VRMS), and RMS current (IRMS):

Or by distortion factor (KDIST) and displacement factor

(KDISP):

With a purely resistive system, PF = 1. The addition of reactive

elements necessary in any converter, such as EMI filters and

energy storage, will induce some amount of displacement

(phase shift between the input voltage and input current). The

addition of switching devices will also create distortion (ener-

gy present in the harmonics relative to the switching frequen-

cies). These non-idealities decrease the PF towards zero.

Active power factor correction attempts to make the input

impedance look as resistive as possible to the power source.

Since the output of the converter is usually a regulated voltage

or current, there is a need for large energy storage elements

to remove the twice line frequency (100Hz or 120Hz) ripple.

A power factor control architecture, as shown in Figure 2, has

very little capacitance at the input. Instead, the twice line fre-

quency content is removed with large energy storage capac-

itance at the output.

Using this control architecture, the converter is able to provide

two important functions at the same time:

•Shape the input current

•Regulate the output voltage

The PFC control approach requires two separate control

loops to achieve both functions: a fast loop which shapes the

input current, and a slow loop that regulates the output volt-

age.

The fast control loop shapes the input current to have the

same sinusoidal shape as the AC input voltage. Assuming

both are perfect sinusoids with zero distortion or phase shift,

the power factor will be perfect (unity). Unfortunately, distor-

tion is always present in switching converters. An input filter,

which is required to comply with EMI standards, helps to at-

tenuate the switching content, thereby reducing distortion.

However, the added filter capacitance will increase the phase

shift at the same time. Though perfect PF is not achievable

within real applications, extremely high PF (>.99) is possible

using most active PFCs.

The output voltage has to be regulated slowly to ensure the

converter ignores the twice line frequency ripple present on

the output. Therefore, the voltage loop containing the error

amplifier should have a bandwidth at least an order of mag-

nitude slower (<20Hz is common). Sometimes the bandwidth

is increased to improve transient response, which is the case

with off-line dimmable LED drivers. Though PF decreases

with the increase in bandwidth, high PF (>.95) is still possible.

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LM3450 LM3450A

30127424

FIGURE 3. Basic CRM Inductor Current Waveform

CRM BACKGROUND

During critical conduction mode (CRM), a converter operates

at the boundary of continuous conduction mode (CCM) and

discontinuous conduction mode (DCM). This is usually im-

plemented as follows. The main switching MosFET (QSW) is

turned on and the inductor current rises to a peak threshold.

QSW is then turned off and the current falls until it reaches

zero. At this point, QSW is turned on and the cycle repeats.

Near zero voltage switching, enabled by the inductor current

return to zero, gives CRM topologies an efficiency improve-

ment compared to CCM topologies. Figure 3 shows the re-

sulting inductor current waveform, where the average induc-

tor current (IL) is half of the peak current (IL-MAX).

In a CRM flyback PFC application, the rectified AC input is fed

forward to the control loop, creating a sinusoidal primary peak

current envelope (IP-pk) as shown in Figure 4. The secondary

peak current envelope (IS-pk) will simply be a scaled version

of the primary according to the turns ratio of the transformer.

Assuming good attenuation of the switching ripple via the EMI

filter, the average input current (IIN), represented by the red

line in Figure 4, can also be approximated as a sinusoid pro-

portional to the duty cycle (D(t)):

Since CRM operation is hysteretic and the input voltage is fed-

forward, the input current shaping loop is as fast as possible.

Only the output voltage needs to be regulated with a narrow

bandwidth error amplifier, which greatly simplifies the system

dynamics.

30127425

FIGURE 4. CRM Flyback Current Waveforms

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LM3450 LM3450A

30127426

FIGURE 5. PFC Control Circuit

POWER FACTOR CONTROLLER

The LM3450/50A uses CRM control to regulate the output

voltage and provide power factor correction. In a non-isolated

boost topology, an external voltage divider (RFB1, RFB2) is

used to sense the output voltage, as shown in Figure 5. The

divider is connected to the inverting input (FB) of the internal

error amplifier. The LM3450/50A regulates the feedback volt-

age (VFB) to 2.5V in a closed loop fashion.

The FB pin has a shutdown mode to protect against a feed-

back short and an OVP mode which terminates switching

when output over-voltage is sensed.

With the FB shutdown mode, it is necessary to have a pre-

liminary biasing method for the output of the error amplifier

(COMP). Otherwise, the converter would never start. COMP

is pre-biased with a 415µA current until the voltage at COMP

(VCMP) exceeds the minimum operational voltage (VTHM).

For an isolated flyback topology, where the error amplifier is

on the secondary, the LM3450/50A internal error amplifier

can be bypassed using a single 5.11kΩ resistor (RFB1) from

FB to GND. This engages an internal 5kΩ pull-up resistor at

COMP. COMP can then be connected directly to the optical

isolation as shown in Figure 5.

COMP and the sensed rectified AC input voltage (VAC), pro-

vided via a resistor divider (RAC1, RAC2), are inputs to the

multiplier. The current through the sense resistor (RCS) pro-

duces a voltage (VCS) that is compared to the multiplier out-

put. When VCS exceeds the multiplier output, QSW is turned

off. The peak detect threshold and the current slope during

an on-time are proportionally changing which yields a nearly

constant on-time, shown in Figure 4:

Once QSW is turned off, the LM3450/50A waits until the in-

ductor (boost) or transformer (flyback) is demagnetized to

turn QSW on again. Demagnetization, sensed at ZCD, occurs

when the current through the magnetic component falls to

zero. Since the output voltage is regulated, the slope of the

current remains relatively constant and, coupled with the vari-

able peak detect, creates a variable off-time.

The sinusoidal peak detection envelope creates an input cur-

rent that is sinusoidal and in phase with the input voltage

providing excellent PF. The PWM comparator 30mV input

offset voltage ensures current is drawn at the zero-crossings

of the AC line, reducing distortion and further improving PF.

CURRENT SENSE

The LM3450/50A senses current through QSW via a sense

resistor (RCS) between the source of QSW and GND. When

VCS exceeds the output of the multiplier (VMLT), QSW is turned

off. VMLT is variable over the line cycle and is a function of the

scaled rectified AC voltage (VAC), the COMP voltage refer-

enced from its operational minimum (VCOMP-VTHM), the mul-

tiplier gain (KM) and the PWM comparator offset (VOS):

The LM3450/50A has a leading edge blanking (LEB) circuit

that pulls the current sense input to the PWM comparator low

for 140µs at the beginning of each on-time. The LEB blanks

the current spike and associated ringing due to the turn-on

transient of QSW, limiting the minimum achievable duty cycle.

OVER CURRENT PROTECTION

The LM3450/50A has a current limit threshold (VLIM = 1.5V)

at CS to protect the system from over-current conditions. If

VCS exceeds VLIM, QSW is immediately turned off until ZCD

triggers a new on-time.

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LM3450 LM3450A

30127427

FIGURE 6. ZCD Waveforms for Flyback Design

ZERO CURRENT DETECTION

ZCD is implemented with a 100kΩ resistor from the ZCD pin

to a coupled winding on the transformer or inductor as shown

in Figure 5. This winding is also used to bootstrap VCC after

start-up. When QSW turns off, the voltage at the ZCD pin

(VZCD) increases as energy is transferred through the auxiliary

winding. The circuit arms when VZCD exceeds 1.5V. Then,

when the energy is fully transferred, VZCD decreases towards

zero. When VZCD falls below 1.3V, the transformer is assumed

to be demagnetized, the circuit disarms, and QSW is turned

back on as shown in Figure 6. The ZCD pin voltage will remain

low until QSW is turned off via peak detection and the cycle

repeats.

SWITCHING FREQUENCY

With a constant on-time and variable off-time, there is a vari-

able switching frequency:

Figure 4 shows that the minimum switching frequency occurs

at the peak of the rectified AC waveform, while the maximum

switching frequency occurs at the valley.

ERROR AMPLIFIER

The LM3450/50A internal error amplifier is used for non-iso-

lated designs (boost) where the output voltage can be directly

sensed, via a resistor divider, at the FB pin. The FB pin is the

inverting input of the trans-conductance amplifier which is

regulated to 2.5V. The COMP pin is the output of the amplifier

and external compensation is placed from COMP to GND in

the form of a single capacitor (CCMP) as shown in Figure 5, a

series resistor and capacitor, or both. The output of the am-

plifier sources or sinks current as necessary to force the

inputs of the amplifier to be equal. The compensation method

depends upon the transient performance desired and re-

quires a loop gain analysis. This analysis can be somewhat

complex and cumbersome. A detailed analysis can be found

Application Notes AN-2098 and/or AN-2150.

If the COMP pin voltage (VCMP) falls below 1.4V at any time,

the device enters burst mode where the GATE is off for 340µs

then is turned on. If VCMP is still below 1.4V at the end of the

on-time then another 340µs off-time occurs. However, if

VCMP has risen above 1.4V, the converter continues switching

until it falls below the threshold again. This feature is neces-

sary to prevent the output of the converter from rising arbi-

trarily high because the minimum on-time of the device

prevents less energy transfer.

The LM3450/50A also implements both feedback short circuit

protection and output over-voltage protection (OVP) functions

at the FB pin. If VFB exceeds 3V, then OVP is engaged and

the part stops switching until VFB falls below 3V. In the same

manner, if VFB falls below 168mV, then shutdown is engaged

and switching stops until VFB exceeds 188mV.

The flyback topology is frequently used to provide isolation

from input to output. Since, the current transfer ratio (CTR) of

standard optical isolation varies over temperature, proper

regulation using primary error amplifiers is difficult. An error

amplifier is usually placed in the secondary to regulate the

output voltage accurately. To accommodate isolated designs,

the LM3450/50A internal error amplifier can be bypassed by

placing a 5.11kΩ resistor from FB to GND. This engages a

5kΩ pull-up resistor from COMP to an internal 5V rail.

SECONDARY ERROR AMPLIFIER

For isolated designs, the error amplifier on the secondary

should take the form of a proportional integral (PI) compen-

sator. The amplifier is frequently implemented with an

LMV431. The output voltage resistor divider (RFB1, RFB2) pro-

vides the sensed output voltage to the LMV431 inverting

input. The PI compensation is achieved by connecting RSC

and CSC in between the LMV431 input and output, shown in

Figure 7. In addition, CCMP is placed from COMP to GND on

the primary for higher frequency noise attenuation.

In addition to the basic error amplifier, a soft-start circuit can

be implemented using a capacitor, two diodes and a Zener

diode as shown in Figure 7. This secondary softstart circuit

has no restart mechanism, therefore a primary side softstart

is recommended as described in the SOFTSTART section of

this document.

30127428

FIGURE 7. Secondary Error Amplifier

15 www.national.com

LM3450 LM3450A

PRECISION VOLTAGE REFERENCE

The LM3450/50A provides a 3V voltage reference (VREF) for

biasing the VADJ pin as well as any external circuitry. VREF is

regulated once VCC exceeds 3V. There is a 2mA current limit

for the reference. A 10nF ceramic bypass capacitor should be

placed from VREF to GND.

LOW POWER SHUTDOWN

The LM3450/50A can be placed into a low power shutdown

by grounding the VADJ pin (any voltage below 75mV). During

low power shutdown, the device will turn on the GATE for one

cycle followed by a fixed off-time of 42µs and the cycle re-

peats. During shutdown, the DIM output will be high (zero light

output) since the buffer rail at FLT1 will be at or near zero.

This feature is designed to hold up the PFC output voltage

while removing the load (turning the LEDs off).

THERMAL SHUTDOWN

Internal thermal shutdown circuitry is provided to protect the

IC in the event that the maximum junction temperature is ex-

ceeded. The threshold for thermal shutdown is 160°C with a

20°C hysteresis. During thermal shutdown GATE is disabled.

30127430

FIGURE 8. Phase Dimming Waveforms

PHASE DIMMER OPERATION

A simplified schematic of a phase dimmer is shown in Figure

9. An RC network consisting of R1, R2, and C1 delay the turn-

on of the triac until the voltage on C1 reaches the trigger

voltage of the diac. Increasing the resistance of the poten-

tiometer (wiper moving downward) increases the turn-on de-

lay which decreases the on-time or “conduction angle” of the

triac (θ). This reduces the average power delivered to the

load.

30127429

FIGURE 9. Basic Forward Phase Dimmer

Phase dimmer voltage waveforms are shown in Figure 8.

Figure 8a shows the full sinusoid of the input voltage. Even

when set to full brightness; few dimmers will provide 100%

conduction angle.

Figure 8b shows a waveform from a forward phase dimmer.

The off-time can be referred to as the firing angle and is simply

180° – θ.

Figure 8c shows the waveform of a reverse phase dimmer

(also called an electronic dimmer in the lighting industry).

These typically or more expensive, microcontroller based

dimmers that use switching devices other than triacs. Note

that the conduction angle starts from the zero-crossing, and

terminates some time later. This method of control reduces

the noise spike at the transition.

Any form of phase dimming modulates the incoming AC

waveform by chopping part of the sinusoid, reducing the av-

erage power to the load. These dimmers work very well with

standard incandescent bulbs, but not with power converters.

A converter attempts to regulate the load in with presence of

any input, effectively ignoring the phase angle. To implement

a dimmable converter, the angle must be sensed at the input,

decoded and used to properly control the LED current regu-

lator.

www.national.com 16

LM3450 LM3450A

30127431

FIGURE 10. Dimming Decoder Circuit

PHASE DIMMING DECODER

The LM3450/50A uses the rectified AC line voltage to inter-

pret the conduction angle. Figure 10 shows the LM3450/50A

decoder circuit with associated external circuitry. The rectified

AC line voltage is scaled via a resistor divider (RAC1, RAC2)

and connected to the VAC pin. VAC is compared to a 356mV

reference to generate a twice line frequency PWM signal with

corresponding duty cycle as shown in Figure 11.

30127432

FIGURE 11. Phase Angle Demodulation

For best results, RAC1 and RAC2 are suggested to be sized so

that the VAC voltage crosses the 356mV threshold when the

rectified AC line is as follows:

•120V systems: 25V to 45V

•230V systems: 40V to 70V

The demodulated duty cycle is sampled and logarithmically

remapped to a 300Hz PWM signal improving the resolution

of low dimming levels to the human eye. A minimum duty cy-

cle limits the maximum achievable contrast ratio to approxi-

mately 70:1. The remapped PWM signal is buffered and

output at FLT1 with amplitude equal to VADJ as shown in Fig-

ure 12.

30127433

FIGURE 12. FLT1 to FLT2 Mapping

The FLT1 signal is routed through a 2 pole low pass filter

(RF1, CF1, RF2, CF2), as shown in Figure 10, to remove the

twice line frequency ripple. The resulting analog signal at

FLT2 is compared to a 500Hz Triangle wave to create the

inverted PWM signal at the DIM pin as shown in Figure 13:

30127434

FIGURE 13. FLT2 to DIM Mapping

17 www.national.com

LM3450 LM3450A

This PWM signal at the DIM pin can be used as the dim input

to a secondary LED driver. DIM is an open drain output de-

signed for isolated solutions. Optical isolation is used to trans-

mit signals across the isolation boundary. With most opto-

isolators, the edge rate is dependent on the amount of drive

current through the photodiode. The open-drain configuration

allows the primary bias supply (VCC) to provide the current as

shown in Figure 10. The choice of resistor (RPB) between

VCC and the photodiode anode will set the drive current. This

enables the user to trade-off PWM accuracy with system ef-

ficiency.

The open drain configuration also ensures that the secondary

has a resistor from the phototransistor’s emitter to secondary

ground (not from collector to secondary bias). During system

turn-off, this prevents an undesired LED blink because the

secondary stage LED driver is forced off.

A variable sample rate and dynamic filter ensure fast, smooth

dimming transitions (movement of the dimmer) while main-

taining robust flicker-free behavior when the dimmer is static.

The sample rate depends on past and present angle infor-

mation. The dynamic filter is a dual mode filter. During stand-

by mode, when a transition has not been made and the

dimmer is static, a 500kΩ series resistor is connected be-

tween the buffered output and FLT1 as shown in Figure 10.

The 500kΩ resistor is shorted when the LM3450/50A senses

a large transition of the dimmer. This increases the filter speed

while the dimmer is transitioning between levels to improve

response time.

The FLT1 and FLT2 poles created by each RC pair (RF1 and

CF1, RF2 and CF2) should be set as follows:

•CF1 and CF2 can be 1µF ceramic capacitors for all designs.

•RF1 and RF2 should be set between 15kΩ (~10Hz) and

75kΩ (~2Hz).

2 Hz poles provide a “smooth fade” while 10Hz poles create

a “snappy” response.

These component values ensure that the static filter condition

in standby mode has 1 pole approximately a decade lower

than the nominal in order to provide good noise immunity to

the system.

0.0 0.2 0.4 0.6 0.8 1.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

DIM PIN DUTY CYCLE (INVERTED)

LM3450/A DEMODULATED VAC PIN DUTY CYCLE

0.5V

2.5V

1.5V

VADJ=3V

30127418

FIGURE 14. Complete Decoder Mapping

Since the buffered decoder output has amplitude equal to

VADJ and the resulting PWM signal is filtered into an analog

voltage at FLT2, the VADJ pin can be used to change the

mapping as shown in Figure 14. The maximum LED current

(DIM = 0) when VADJ = 3V corresponds to decoded angles of

70% or greater. Some dimmers have a maximum angle

greater than this. If VADJ is reduced to 2.5V, the maximum

LED current will correspond to an angle of 80% and at VADJ

= 2V the maximum will occur at a decoded angle of 95%.

The VADJ pin can also be used to implement a standard ana-

log adjust function. If the demodulated phase angle at VAC is

above 85%, then the fast filter is always enabled (500kΩ

shorted) and the VADJ pin can solely be used to scale the DIM

pin duty cycle. When VADJ is pulled below 75mV the part en-

ters low power shutdown so the maximum attainable contrast

ratio using VADJ only is approximately 40:1.

Both FLT1 and FLT2 have pull-down MosFETs that are

turned on when VCC UVLO falling threshold is triggered. This

provides a quick discharge path for the capacitors and elimi-

nates the possibility of an undesired light level at the next

startup.

www.national.com 18

LM3450 LM3450A

30127435

FIGURE 15. Dynamic Hold Circuit

DYNAMIC HOLD

A forward phase “triac” dimmer requires a minimum amount

of current to be flowing through it during the entire conduction

angle. This is referred to as hold current. If the minimum hold

current requirement is not met, the triac will shut off (misfire).

During normal operation, the converter will demand some

amount of input current. However, at any point during the cy-

cle, the input current can be low enough to cause a misfire.

During an LM3450/50A sampling period, the triac should not

misfire or the decoded angle will be inaccurate as shown in

Figure 16. Since the triac is asymmetrical phase-to-phase,

misfires can occur at different points in the waveform. After

the triac misfires, the voltage returns to zero exponentially.

This can create a large difference between decoded angles

which can be observed as a “fluttering” of the light.

30127436

FIGURE 16. Forward Phase Waveform

To ensure the triac does not misfire during a sampling period

and the angle is correctly decoded, a dynamic hold function

is enabled. The input current is sensed with a resistor (RSEN)

from GND to ISEN (the return of the full bridge rectifier). If the

voltage across this resistor is less than 200mV, the device

adds holding current via the HOLD circuitry to maintain

200mV across RSEN.

The hold current is added by linearly adjusting the gate volt-

age of QHLD as shown in Figure 15. As the gate voltage of

QHLD is increased, the HOLD pin voltage decreases, forcing

a voltage across the resistance (RHLD) from the source of

QPS to HOLD. This extra current is drawn from the input

through the triac, but is not processed by the converter. Figure

17 shows a typical dynamic hold waveform of the LM3450

where interval 1 is a non-sampled conduction angle, 2 is the

firing angle, and 3 is a sampled conduction angle. It should

be noted that using the LM3450A will ensure every conduc-

tion angle looks like interval 3 in Figure 17.

30127437

FIGURE 17. Dynamic Hold Waveform

The dynamic hold function is also necessary for reverse

phase dimmers, but for a different reason. Reverse phase

dimmers do not use triacs, therefore they do not require a

minimum “holding” current. Instead, they need what is com-

monly called bleeder current. When a reverse phase dimmer

turns off, the AC voltage is at a high value. There is an RC

time constant associated with discharging the total effective

input capacitance (EMI capacitors, PFC capacitor, damper

19 www.national.com

LM3450 LM3450A

capacitance). The decoder does not record the angle until the

voltage reaches the 356mV threshold. This can cause the

decoded angle to be much larger than it actually is and de-

pendent on the RC time constant as shown in Figure 18.

30127438

FIGURE 18. Reverse Phase Waveforms

The dynamic hold will quickly bleed off the excess charge in

an attempt to regulate the voltage across RSEN. This will pre-

serve the accuracy of the decoded phase angle.

During the conduction angle (θ), dynamic hold is enabled only

during a sample period for the LM3450. However, during the

firing angle (delay time), dynamic hold is always enabled with

the LM3450. This will ensure the rectified line voltage does

not begin to rise due to leakage currents through the phase

dimmer. Again, with the LM3450A the dynamic hold is con-

tinuously active during all conduction and firing angles.

The minimum regulated input current can be calculated:

The maximum possible additional holding current (which can

occur when HOLD is still transitioning usually at the rising

edge of the triac firing) can be approximated:

It is recommended that the maximum hold current is set

10-15% higher than the minimum regulated input current.

A minimum of 0.1µF capacitance should be placed between

ISEN and HOLD to limit the bandwidth of the dynamic hold cir-

cuit to well below the switching frequency. However, if too

large a capacitor is used, the bandwidth will be too low to re-

spond to line transients. A maximum of 0.47µF should ensure

good performance.

Finally, a small Schottky diode should be placed from GND to

ISEN to absorb the large current spikes associated with the

triac firing edge. This diode should have a forward voltage

above 200mV at the worst-case operating temperature so

that it won’t interfere with dynamic hold regulation.

THERMAL PROTECTION

With the LM3450A, QPS has to dissipate more power than with

the LM3450. During worst case conditions such as open LED

load, the converter will be demanding very little current re-

gardless of the triac position. If the phase dimmer conduction

angle is large and the load is not present, QPS has to dissipate

many watts since the dynamic hold is attempting to regulate

the current to ten's of mA. Using the LM3450, this is nominally

not a problem since it is sampling the dynamic hold infre-

quently. However, the LM3450A is drawing the hold current

every cycle which becomes a problem very quickly. It should

be noted that If the input AC line is very noisy, the VAC input

to the decoder could have enough variation in steady state to

cause the decoder to think the dimmer is transitioning all of

the time. This would increase the sampling rate dramatically,

putting much more thermal strain on the passFET in LM3450

applications as well.

To mitigate these problems, a thermal protection circuit

should be implemented on the LM3450A designs (and can be

on the LM3450 designs as well) as shown in red in Figure

15. The NTC thermistor should be placed on the opposite side

of the PCB directly under the drain of QPS. This will provide

the best thermal coupling while maintaining the necessary

high voltage spacing constraints. At startup the NTC is at a

high resistance value, turning the PNP fully on which provides

the dynamic hold path. As the NTC heats up the resistance

decreases and the base voltage increases. Eventually, the

PNP will transition into linear mode and the effective resis-

tance from collector to emitter will increase. This will decrease

the maximum holding current, thereby decreasing the thermal

stress on QPS. Given enough headroom, the circuit should

reach thermal equilibrium in a safe controlled manner.

Since this method of thermal protection linearly reduces the

maximum hold current with increasing temperature, the fold-

back will not be perceptible to the consumer. Instead, the

result of the foldback will simply be a reduction of contrast

ratio, meaning the minimum achievable LED current will in-

crease as the temperature increases beyond the foldback

level.

www.national.com 20

LM3450 LM3450A

30127439

FIGURE 19. Primary Bias Circuitry

PRIMARY BIAS SUPPLY

The LM3450/50A requires a supply voltage at VCC, not to ex-

ceed 25V. The device has VCC under-voltage lockout (UVLO)

with rising and falling thresholds of 12.9V and 7.9V respec-

tively. A 24V Zener diode should be placed from the VCC pin

to GND to protect the device from substantial spikes that

could cause damage.

Figure 19 shows how the LM3450/50A provides a quick way

to generate the necessary primary bias supply at start-up.

Since the AC line peak voltage is always higher than the rating

of the controller, all designs require an N-channel MosFET

(passFET). The passFET (QPS) is connected with its drain at-

tached to the rectified AC. The gate of QPS is connected to

the BIAS pin which has a stack of 2 Zener diodes internal to

the device. These diodes are then biased from the rectified

AC line through series resistance (RBS). The source of QPS is

held at a VGS below the Zener voltage and current flows

through QPS to charge up whatever capacitance is present. If

the capacitance is large enough, the source voltage will re-

main relatively constant over the line cycle and this becomes

the input bias supply at VCC.

This bias circuit enables instant turn-on. However, once the

circuit is operational it is desirable to bootstrap VCC to an aux-

iliary winding of the inductor or transformer (also used for

ZCD). The two bias paths are each connected to VCC through

a diode to ensure the higher of the two is providing VCC cur-

rent. This bootstrapping greatly improves efficiency when

quick start-up is necessary.

To ensure that the auxiliary winding is powering VCC at all

times except start-up, the LM3450/50A has a dual BIAS

mode. The BIAS voltage at startup is 20V through two Zener

diodes. When the VCC UVLO rising threshold is exceeded and

the device turns on, the BIAS pin voltage is reduced to 14V

(bottom 6V Zener is shorted). Once the VCC UVLO falling

threshold is reached again, the BIAS pin will return to 20V to

attempt to restart the device.

It should be noted that the large hysteresis of VCC UVLO and

the dual BIAS mode allow for a large variation of the auxiliary

bias circuitry easing the design of the magnetics.

SOFTSTART

As in any off-line system, softstart is an important part of the

design. Since the LM3450/50A are used with phase dimming

applications, the typical startup problems are magnified since

a phase dimmer is frequently turned on and off rapidly. This

requires a softstart mechanism that quickly resets when the

LM3450/50A turns off. Since the LM3450/50A has two distinct

functional parts (PFC and phase decoder), ideally both should

be softstarted simultaneously. This will ensure the most con-

trolled start-up possible.

The circuit in Figure 20 provides this exact functionality. Both

VADJ and COMP are diode or'ed into an RC charging circuit

fed from VCC. The reset mechanism is accomplished using an

18V Zener from BIAS, a current limiting resistor and an NPN

transistor. The reset is activated when VCC uvlo falling is trig-

gered and BIAS transitions to 20V. This discharges the RC to

zero and as soon as VCC uvlo rising is passed BIAS transitions

to 14V again, releasing the clamp on the RC softstart circuit.

The RC will charge up to the 3.9V Zener clamp (which is

above the dynamic range of COMP and VADJ and become

effectively out of the circuit until the next turn-off.

30127450

FIGURE 20. Dual Softstart Circuit

21 www.national.com

LM3450 LM3450A

Design Information

HOW TO SELECT THE CORRECT DEVICE (LM3450 or

LM3450A)

What application(s) are suitable for the LM3450, and when is

the LM3450A appropriate? The difference centers on the

power dissipation in the passFET. The passFET stands off

the high AC voltage from the LM3450/50A, and provides a

path for the hold current. The passFET operates in the linear

region and dissipates power equal to the product of the volt-

age across it and the current through it.

The LM3450 was designed to minimize the power dissipation

in the passFET by applying holding current in a sampled form.

The standby sampling rate (when the dimmer is not moving)

is infrequent, allowing minimal impact on the thermal consid-

erations of the passFET. Sampling of the dynamic hold is not

desired for some applications although. An example where

the sampled hold current may cause undesirable effects is the

single stage flyback topology where the output of the flyback

is directly connected to the LEDs. If the phase dimmer is al-

lowed to misfire or create erratic differences in the input

voltage and current waveforms, this behavior will appear as

a "fluttering" of the LED light output at the sampling rate when

the single stage topology is used. The light flutter is most ob-

servable at low input currents (dimming). A small perturbation

in the input voltage due to phase dimmer misfire can create

a visible difference in the output light. Using a secondary LED

driver stage eliminates this problem.

Cost sensitive applications may drive the design to a single

stage solution, and the LM3450A was developed to address

this market. The LM3450A provides continuous dynamic hold

current on every AC cycle preventing the phase dimmer from

misfire, and the sampling frequency from appearing at the

output. Another design consideration where continuous dy-

namic hold may be advantageous is the reduced stresses on

input EMI R/C snubber networks.

The designer must pay close attention to the power loss of

the passFET when using the LM3450A. Designers must con-

sider worst case possibilities with any power conversion de-

signs. Worst case operating conditions with the LM3450A are

usually found with the largest triac holding current require-

ments. Many phase dimmers require 25mA-40mA of holding

current, and frequently designers are choosing 50mA as their

minimum holding current requirement. The passFET package

for common LM3450/50A designs should be capable of dis-

sipating between 1W and 1.5W. The pass-FET can always

be increased in size and/or the hold current can be reduced.

Power calculations for the dynamic hold circuit as well as ef-

fective thermal protection are both described in the DYNAMIC

HOLD section.

The LM3450 and LM3450A is best differentiated in terms of

the appropriate applications for each device. The Device Se-

lection Guide can be used as a general guide for when to use

each part.

Device Selection Guide

Product AC

Input

Output

Power Device Topology

High End

Downlight

120V POUT < 15W LM3450

Two Stage

Design

POUT > 15W LM3450A

230V POUT < 25W LM3450

POUT > 25W LM3450A

Low Cost

Downlight

Large

High End

Bulb

120V POUT > 15W

LM3450A

Single

Stage

Design

230V POUT > 25W

www.national.com 22

LM3450 LM3450A

Applications Information

See AN-2098 and/or AN-2150 for detailed design and application information.

TWO STAGE LED DRIVER – LM3450 PRIMARY AND LM3409HV SECONDARY

30127440

23 www.national.com

LM3450 LM3450A

15W TWO STAGE DESIGN SPECIFICATIONS

AC Input Voltage: 120VAC nominal (90VAC - 135VAC) or 230VAC nominal (180VAC - 265VAC)

Regulated Flyback Output Voltage: 50V

Regulated LED Current: 350mA

LED Stack Voltage Maximum: 45V

Bill of Materials

*Components are used in both versions unless otherwise noted

Reference Designator Description Manufacturer Part Number

LM3450 IC PFC CONT 16-TSSOP NSC LM3450MT

LM3409HV IC LED DRIVR 10-eMSOP NSC LM3409HVMY

LMV431 IC SHUNT REG SOT-23 NSC LMV431AIM5

C1a, C1b, C5a,

C5b

120V CAP CER 0.22µF 250V 1210 MURATA GRM32DR72E224KW01L

230V CAP CER 68nF 250V 1210 MURATA GRM32QR72E683KW01L

C2 CAP MPY 33nF 250VAC X1 RAD EPCOS B32912A3333M

C3 CAP CER 47µF 6.3V 0805 TAIYO YUDEN JMK212BJ476MG-T

C4 120V CAP MPY 0.1µF 400V RAD EPCOS B32612A4104J008

230V CAP MPY 33nF 1000V RAD WIMA MKP10 - .033/1000/10

C6 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0

C7a CAP ELEC 470µF 63V RAD NICHICON UPW1J471MHD3

C7b, C8b, C9b, C11, C15 CAP CER 0.1µF 50V 1206 MURATA GRM188R71H104KA93D

C8a, C9a CAP ELEC 100µF 50V RAD NICHICON UHE1H101MPD

C10 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D

C12, C13 C14, C21 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D

C16 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K

C17 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L

C18, C20 CAP CER 1µF 100V 1206 TDK C3216X7R2A105M

C19 CAP CER 2.2µF 6.3V 0603 TDK C1608X5R0J225M

C22 CAP CER 470pF 100V 0603 TDK C1608C0G2A471J

D1 120V DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

230V DIODE FAST 400V 1A DO-214AC FAIRCHILD ES1G

D2 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

D3, D5 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914

D4 DIODE DUAL SCHOTTKY 20V 0.5A SOT-23 NXP SEMI PMEG3005CT,215

D6 120V DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A

230V DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A

D7 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J

D8 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP

D9 DIODE SCHOTTKY 20V 3A SMA FAIRCHILD ES2AA-13-F

D10 DIODE RECT 600V 0.5A Minidip COMCHIP HD06

D11, D12 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B

D13 DIODE ULTRAFAST 70V 0.2A SOT-23 FAIRCHILD BAV99

D14 DIODE ZENER 3.3V 500mW SOD-123 ON-SEMI MMSZ3V3T1G

D15 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G

D16 DIODE SCHOTTKY 60V 2A SMB ON-SEMI SS26T3G

D17 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G

D18 DIODE ZENER 18V 500MW SOD-123 ON-SEMI MMSZ5248T1G

L1, L2, L3 IND SHIELD 1mH 0.46A SMT COILCRAFT MSS1038-105KL

L4 IND SHIELD 470µH 1.06A SMT COILCRAFT MSS1278-474KLB

Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4

www.national.com 24

LM3450 LM3450A

Reference Designator Description Manufacturer Part Number

Q2 120V MOSFET N-CH 600V 4.4A DPAK INFINEON IPD60R950C6

230V MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4

Q3, Q4 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401

Q5 MOSFET P-CH 70V 5.7A DPAK ZETEX ZXMP7A17K

Q6 TRANS PNP 40V 0.2A SOT-23 FAIRCHILD MMBT3904

R1 120V RES 330Ω 5% 1W 2512 VISHAY CRCW2512330RJNEG

230V RES 510Ω 5% 1W 2512 VISHAY CRCW2512510RJNEG

R2 120V RES 430Ω 5% 1W 2512 VISHAY CRCW2512430RJNEG

230V RES 1.6kΩ 5% 1W 2512 VISHAY CRCW25121K60JNEG

R3 120V RES 402kΩ 1% 0.25W 1206 VISHAY CRCW1206402KFKEA

230V RES 953kΩ 1% 0.25W 1206 VISHAY CRCW1206953KFKEA

R4 RES 100Ω 1% 1W 2512 VISHAY WSL2512100RFKEA

R5 RES 100kΩ 1% 0.1W 0603 VISHAY CRCW0603100KFKEA

R6 RES 6.04kΩ 1% 0.1W 0603 VISHAY CRCW06036K04FKEA

R7 RES 499kΩ 1% 0.1W 0603 VISHAY CRCW0603499KFKEA

R8, R9 RES 75.0kΩ 1% 0.1W 0603 VISHAY CRCW060375K0FKEA

R10 RES 20.0kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA

R11 120V RES 1.00MΩ 1% 0.25W 1206 VISHAY CRCW12061M00FKEA

230V RES 2.00MΩ 1% 0.25W 1206 VISHAY CRCW12062M00FKEA

R12 RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA

R13 RES 5.11kΩ 1% 0.1W 0603 VISHAY CRCW06035K11FKEA

R14a RES 10Ω 1% 0.25W 1206 VISHAY CRCW120610R0FKEA

R14b RES 1.00Ω 1% 0.33W 1210 VISHAY CRCW12101R00FNEA

R15a, R15b RES 5.62Ω 1% 0.25W 1206 VISHAY CRCW12065R62FNEA

R16 RES 2.00kΩ 1% 0.125W 0805 VISHAY CRCW08052K00FKEA

R17 120V RES 20.0kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA

230V RES 10.0kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA

R18 RES 105kΩ 1% 0.125W 0805 VISHAY CRCW0805105KFKEA

R19 RES 2.67kΩ 1% 0.1W 0603 VISHAY CRCW06032K67FKEA

R20 RES 6.04kΩ 1% 0.125W 0805 VISHAY CRCW08056K04FKEA

R21 RES 10.0kΩ 1% 0.125W 0805 VISHAY CRCW080510K0FKEA

R22 RES 80.6kΩ 1% 0.1W 0603 VISHAY CRCW060380K6FKEA

R23 RES .62Ω 1% 0.5 2010 SMD ROHM MCR50JZHFLR620

R24, R25 RES 10kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA

R27, R28 120V RES 10Ω 10% 2W FILM WELWYN EMC2-10R0

230V RES 22Ω 10% 2W FILM WELWYN EMC2-22R0

OPTO1, OPTO2 OPTO-ISOLATOR SMD LITE ON CNY17F-3S

T1 120V XFORMER 120V 15W OUTPUT 50V WURTH 750813550

230V XFORMER 230V 15W OUTPUT 50V WURTH 750817550

25 www.national.com

LM3450 LM3450A

SINGLE STAGE LED DRIVER – LM3450A FLYBACK

30127441

www.national.com 26

LM3450 LM3450A

30W SINGLE STAGE DESIGN SPECIFICATIONS

AC Input Voltage: 120VAC nominal (90VAC - 135VAC) or 230VAC nominal (180VAC - 265VAC)

Flyback Output Voltage Maximum: 60V

Regulated LED Current: 700mA

Bill of Materials

*Components are used in both versions unless otherwise noted

Reference Designator Description Manufacturer Part Number

LM3450A IC PFC CONT 16-TSSOP NSC LM3450AMT

LMV431 IC SHUNT REG SOT-23 NSC LMV431AIM5

U1 IC DUAL OP-AMP NSC LM2904

C1a, C1b, C1c,

C5a, C5b, C5c

120V CAP CER 0.22µF 250V 1210 MURATA GRM32DR72E224KW01L

230V CAP CER 68nF 250V 1210 MURATA GRM32QR72E683KW01L

C2 CAP MPY 33nF 250VAC X1 RAD EPCOS B32912A3333M

C3 CAP CER 47µF 6.3V 0805 TAIYO YUDEN JMK212BJ476MG-T

C4 120V CAP MPY 0.22µF 400V RAD WIMA MKP10-.22/400/20

230V CAP MPY 62nF 1000V RAD VISHAY BFC238330623

C6 CAP CER 4.7nF 500VAC Y1 RAD EPCOS VY1472M63Y5UQ63V0

C7a CAP ELEC 1mF 63V RAD NICHICON UPW1J102MHD

C7b, C8b, C9b, C11, C15 CAP CER 0.1µF 50V 1206 MURATA GRM188R71H104KA93D

C8a, C9a CAP ELEC 220µF 50V RAD NICHICON UHE1H221MPD

C10 CAP CER 10nF 25V 0603 MURATA GRM188R71E103KA01D

C12, C13, C14, C18, C19 CAP CER 1µF 16V 0603 MURATA GRM188R71C105KA12D

C16 CAP CER 0.22µF 16V 0603 TDK C1608X7R1C224K

C17 CAP CER 10µF 16V 1206 MURATA GRM31CR71C106KAC7L

D1a, D1b 120V DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

230V DIODE FAST 400V 1A DO-214AC FAIRCHILD ES1G

D2 DIODE ULTRAFAST 200V 1A SMA FAIRCHILD ES1D

D3, D5 DIODE ULTRAFAST 100V 0.2A SOT-23 FAIRCHILD MMBD914

D4 DIODE DUAL SCHOTTKY 20V 0.5A SOT-23 NXP SEMI PMEG3005CT,215

D6 120V DIODE TVS 150V 600W UNI SMB LITTLEFUSE SMBJ150A

230V DIODE TVS 220V 600W UNI SMB LITTLEFUSE SMBJ220A

D7 DIODE ULTRAFAST 600V 1A SMA FAIRCHILD ES1J

D8 DIODE ZENER 24V 1.5W SMA MICRO-SEMI SMAJ5934B-TP

D9 DIODE SCHOTTKY 20V 3A SMA FAIRCHILD ES2AA-13-F

D10 DIODE RECT 600V 0.5A Minidip COMCHIP HD06

D11, D12 DIODE ZENER 10V 500mW SOD-123 FAIRCHILD MMSZ5240B

D13 DIODE ZENER 1.8V 500MW SOD-123 ON-SEMI MMSZ4678T1G

D17 DIODE ZENER 3.9V 500MW SOD-123 ON-SEMI MMSZ4686T1G

D18 DIODE ZENER 18V 500MW SOD-123 ON-SEMI MMSZ5248T1G

D19 DIODE SCHOTTKY 30V 200mA SOT-23 FAIRCHILD BAT54

L1 IND LINE FILTER 6mH 0.3A 11M PANASONIC ELF-11M030E

L1, L2, L3 IND SHIELD 1mH 1.18A SMT COILCRAFT MSS1278-105KL

L4 IND SHIELD 270µH 2.34A SMT COILCRAFT MSS1278-274KLB

Q1 MOSFET N-CH 800V 3A DPAK ST MICRO STD4NK80ZT4

Q2 120V MOSFET N-CH 500V 9A DPAK ST MICRO STD11NM50N

230V MOSFET N-CH 800V 6A DPAK INFINEON SPD06N80C3

Q3, Q4 TRANS NPN 40V 0.6A SOT-23 FAIRCHILD MMBT4401

Q6 TRANS NPN 40V 0.2A SOT-23 FAIRCHILD MMBT3904

27 www.national.com

LM3450 LM3450A

Reference Designator Description Manufacturer Part Number

R1 120V RES 330Ω 5% 1W 2512 VISHAY CRCW2512330RJNEG

230V RES 510Ω 5% 1W 2512 VISHAY CRCW2512510RJNEG

R2 120V RES 430Ω 5% 1W 2512 VISHAY CRCW2512430RJNEG

230V RES 1.6kΩ 5% 1W 2512 VISHAY CRCW25121K60JNEG

R3 120V RES 402kΩ 1% 0.25W 1206 VISHAY CRCW1206402KFKEA

230V RES 953kΩ 1% 0.25W 1206 VISHAY CRCW1206953KFKEA

R4 RES 100Ω 1% 1W 2512 VISHAY WSL2512100RFKEA

R5 RES 100kΩ 1% 0.1W 0603 VISHAY CRCW0603100KFKEA

R6 RES 6.04kΩ 1% 0.1W 0603 VISHAY CRCW06036K04FKEA

R7 RES 499kΩ 1% 0.1W 0603 VISHAY CRCW0603499KFKEA

R8, R9 RES 49.9kΩ 1% 0.1W 0603 VISHAY CRCW060349K9FKEA

R10 RES 20kΩ 1% 0.1W 0603 VISHAY CRCW060320K0FKEA

R11 120V RES 1.00MΩ 1% 0.25W 1206 VISHAY CRCW12061M00FKEA

230V RES 2.00MΩ 1% 0.25W 1206 VISHAY CRCW12062M00FKEA

R12 RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA

R13 RES 5.11kΩ 1% 0.1W 0603 VISHAY CRCW06035K11FKEA

R14a, R14b, R23a, R23b,

R23c

RES 1.00Ω 1% 0.33W 1206 VISHAY CRCW12061R00FKEA

R15a, R15b RES 5.62Ω 1% 0.25W 1206 VISHAY CRCW12065R62FKEA

R16 RES 1.00kΩ 1% 0.125W 0805 VISHAY CRCW08051K00FKEA

R17 120V RES 30.1kΩ 1% 0.1W 0603 VISHAY CRCW060330K1FKEA

230V RES 15.0kΩ 1% 0.1W 0603 VISHAY CRCW060315K0FKEA

R18 RES 105kΩ 1% 0.125W 0805 VISHAY CRCW0805105KFKEA

R19 RES 2.49kΩ 1% 0.1W 0603 VISHAY CRCW06035K49FKEA

R20 RES 6.04kΩ 1% 0.125W 0805 VISHAY CRCW08056K04FKEA

R21 RES 10.0kΩ 1% 0.125W 0805 VISHAY CRCW080510K0FKEA

R22 RES 1.4kΩ 1% 0.125W 0805 VISHAY CRCW08051K40FKEA

R24, R25 RES 10kΩ 1% 0.1W 0603 VISHAY CRCW060310K0FKEA

R26 120V RES 2.49kΩ 1% 0.125W 0805 VISHAY CRCW08052K49FKEA

230V RES 4.99kΩ 1% 0.125W 0805 VISHAY CRCW08054K99FKEA

R27, R28 120V RES 5Ω 10% 3W WIREWOUND VISHAY PAC300005008FAC000

230V RES 10Ω 10% 3W WIREWOUND VISHAY PAC300001009FAC000

R29, R30 RES 4.99kΩ 1% 0.1W 0603 VISHAY CRCW06034K99FKEA

R32 RES 909Ω 1% 0.1W 0603 VISHAY CRCW0603909RFKEA

OPTO1, OPTO2 OPTO-ISOLATOR SMD LITE ON CNY17F-3S

T1 120V XFORMER 120V 30W OUTPUT 50V WURTH 750813651

230V XFORMER 230V 30W OUTPUT 50V WURTH 750817651

Thermal Protect see Dynamic Hold section

www.national.com 28

LM3450 LM3450A

Physical Dimensions inches (millimeters) unless otherwise noted

TSSOP-16 Pin Package (MTC)

For Ordering, Refer to Ordering Information Table

NS Package Number MTC16

29 www.national.com

LM3450 LM3450A

Notes

LM3450 LM3450A LED Drivers with Active Power Factor Correction and Phase Dimming Decoder

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