Low Power, Low Noise
Precision FET Op Amp
AD795
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
FEATURES
Low power replacement for Burr-Brown
OPA111, OPA121 op amps
Low noise
3.3 μV p-p maximum, 0.1 Hz to 10 Hz
11 nV/√Hz maximum at 10 kHz
0.6 fA/√Hz at 1 kHz
High dc accuracy
500 μV maximum offset voltage
10 μV/°C maximum drift
2 pA maximum input bias current
Low power: 1.5 mA maximum supply current
APPLICATIONS
Low noise photodiode preamps
CT scanners
Precision l-to-V converters
CONNECTION DIAGRAM
NC
1
–IN
2
+IN
3
–V
S4
NC
8
+V
S
7
OUTPUT
6
NC
5
NC = NO CONNECT
AD795
00845-001
Figure 1. 8-Lead SOIC (R) Package
GENERAL DESCRIPTION
The AD795 is a low noise, precision, FET input operational
amplifier. It offers both the low voltage noise and low offset drift
of a bipolar input op amp and the very low bias current of a FET-
input device. The 1014 Ω common-mode impedance insures
that input bias current is essentially independent of common-
mode voltage and supply voltage variations.
The AD795 has both excellent dc performance and a guaranteed
and tested maximum input voltage noise. It features 2 pA
maximum input bias current and 500 μV maximum offset
voltage, along with low supply current of 1.5 mA maximum.
1k
100
10
1
10 100 1k 10k
FREQUENCY (Hz)
VOLTAGE NOISE SPECTRAL DENSITY (nV/ Hz)
00845-002
Figure 2. Voltage Noise Spectral Density
Furthermore, the AD795 features a guaranteed low input noise
of 3.3 μV p-p (0.1 Hz to 10 Hz) and a 11 nV/√Hz maximum
noise level at 10 kHz. The AD795 has a fully specified and
tested input offset voltage drift of only 10 μV/°C maximum.
The AD795 is useful for many high input impedance, low noise
applications. The AD795 is rated over the commercial tempera-
ture range of 0°C to +70°C.
The AD795 is available in an 8-lead SOIC package.
50
40
30
20
10
0
–5 –4 –3 –2 –1 0 1 2 3 4 5
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
PERCENTAGE OF UNITS
00845-003
SAMPLE SIZE = 570
Figure 3. Typical Distribution of Average Input Offset Voltage Drift
AD795
Rev. C | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Minimizing Input Current ............................................................ 11
Circuit Board Notes ........................................................................ 12
Offset Nulling ............................................................................. 13
AC Response with High Value Source and Feedback Resistance
........................................................................................................... 14
Overload Issues ............................................................................... 15
Input Protection ......................................................................... 15
Preamplifier Applications.......................................................... 16
Minimizing Noise Contributions ............................................. 16
Using a T Network ..................................................................... 17
A pH Probe Buffer Amplifier ................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
12/09—Rev. B to Rev. C
Changes to Features Section and General Description Section . 1
Changes to Input Bias Current Parameter, Table 1 ...................... 3
Changes to Table 2 ............................................................................ 5
Added Thermal Resistance Section ............................................... 5
Added Table 3; Renumbered Sequentially .................................... 5
Changes to Minimizing Input Current Section .......................... 11
Changes to Circuit Board Notes Section and Figure 33 ............ 12
Changes to Input Protection Section ........................................... 15
Changes to Ordering Guide .......................................................... 18
10/02—Rev. A to Rev. B
Deleted Plastic Mini-DIP (N) Package ............................ Universal
Edits to Features ................................................................................ 1
Edits to Specifications ...................................................................... 2
Edits to Absolute Maximum Ratings ............................................. 3
Edits to Ordering Guide .................................................................. 3
Edits to Circuit Board Notes ........................................................... 9
Edits to Figure 31 .............................................................................. 9
Edits to Offset Nulling ................................................................... 10
Deleted Figure 34 ............................................................................ 10
Deleted Low Noise Op Amp Selection Tree ............................... 15
Updated Outline Dimensions ....................................................... 15
AD795
Rev. C | Page 3 of 20
SPECIFICATIONS
At +25°C and ±15 V dc, unless otherwise noted.
Table 1.
AD795JR
Parameter Test Conditions/Comments Min Typ Max Unit
INPUT OFFSET VOLTAGE1
Initial Offset 100 500 μV
Offset TMIN − TMAX 300 1000 μV
vs. Temperature 3 10 μV/°C
vs. Supply (PSRR) 86 110 dB
vs. Supply (PSRR) TMIN − TMAX 84 100 dB
INPUT BIAS CURRENT2
Either Input VCM = 0 V 1 2 pA
Either Input at TMAX = 70°C VCM = 0 V 23 nA
Either Input VCM = +10 V 1 nA
Offset Current VCM = 0 V 0.1 1.0 pA
Offset Current at TMAX = 70°C VCM = 0 V 2 nA
OPEN-LOOP GAIN VO = ±10 V
R
L ≥ 10 kΩ 110 120 dB
R
L ≥ 10 kΩ 100 108 dB
INPUT VOLTAGE NOISE 0.1 Hz to 10 Hz 1.0 3.3 μV p-p
f = 10 Hz 20 50 nV/√Hz
f = 100 Hz 12 40 nV/√Hz
f = 1 kHz 11 17 nV/√Hz
f = 10 kHz 9 11 nV/√Hz
INPUT CURRENT NOISE f = 0.1 Hz to 10 Hz 13 fA p-p
f = 1 kHz 0.6 fA/√Hz
FREQUENCY RESPONSE
Unity Gain, Small Signal G = −1 1.6 MHz
Full Power Response VO = 20 V p-p, RL = 2 kΩ 16 kHz
Slew Rate, Unity Gain VO = 20 V p-p, RL = 2 kΩ 1 V/μs
SETTLING TIME3
To 0.1% 10 V step 10 μs
To 0.01% 10 V step 11 μs
Overload Recovery4 50% overdrive 2 μs
Total Harmonic f = 1 kHz
Distortion R1 ≥ 10 kΩ, VO = 3 V rms −108 dB
INPUT IMPEDANCE
Differential VDIFF = ±1 V 1012||2 Ω||pF
Common Mode 1014||2.2 Ω||pF
INPUT VOLTAGE RANGE
Differential5 ±20 V
Common-Mode Voltage ±10 ±11 V
Over Maximum Operating Temperature ±10 V
Common-Mode Rejection Ratio VCM = ±10 V 90 110 dB
T
MIN − TMAX 86 100 dB
OUTPUT CHARACTERISTICS
Voltage RL ≥ 2 kΩ VS − 4 VS − 2.5 V
T
MIN − TMAX V
S − 4 V
Current VOUT = ±10 V ±5 ±10 mA
Short circuit ±15 mA
AD795
Rev. C | Page 4 of 20
AD795JR
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Rated Performance ±15 V
Operating Range ±4 ±18 V
Quiescent Current 1.3 1.5 mA
1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
3 Gain = −1, R1 = 10 kΩ.
4 Defined as the time required for the amplifier’s output to return to normal operation after removal of a 50% overload from the amplifier input.
5 Defined as the maximum continuous voltage between the inputs such that neither input exceeds ±10 V from ground.
AD795
Rev. C | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation (at TA = +25°C)
SOIC Package 500 mW
Input Voltage ±VS
Input Current1 ±10 mA
Output Short-Circuit Duration Indefinite
Differential Input Voltage +VS and −VS
Storage Temperature Range (R) −65°C to +125°C
Operating Temperature Range
AD795J 0°C to +70°C
1 Limit input current to 10 mA or less whenever the input signal exceeds the
power supply rail by 0.1 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered on a 4-layer circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
8-Lead SOIC 155 °C/W
ESD CAUTION
AD795
Rev. C | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
20
R
L
= 10kΩ
+V
IN
–V
IN
15
10
5
0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
INPUT COMMON-MODE RANGE (±V)
00845-004
Figure 4. Common-Mode Voltage Range vs. Supply Voltage
20
R
L
= 10kΩ
+V
OUT
–V
OUT
15
10
5
0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE RANGE (±V)
00845-005
Figure 5. Output Voltage Range vs. Supply Voltage
30
25
20
15
10
5
0
10 100 1k 10k
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE SWING (V p-p)
00845-006
V
S
= ±15V
Figure 6. Output Voltage Swing vs. Load Resistance
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0 5 10 15 20
SUPPLY VOLTAGE (±V)
INPUT BIAS CURRENT (pA)
00845-007
Figure 7. Input Bias Current vs. Supply Voltage
50
40
30
20
10
0
0 0.5 1.0 1.5 2.0
INPUT BIAS CURRENT (pA)
PERCENTAGE OF UNITS
00845-008
SAMPLE SIZE = 1058
Figure 8. Typical Distribution of Input Bias Current
10
–9
10
–10
10
–11
10
–12
10
–13
10
–14
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
INPUT BIAS CURRENT (A)
00845-009
Figure 9. Input Bias Current vs. Temperature
AD795
Rev. C | Page 7 of 20
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
–15 –10 –5 0 5 10 15
COMMON-MODE VOLTAGE (V)
INPUT BIAS CURRENT (pA)
00845-010
Figure 10. Input Bias Current vs. Common-Mode Voltage
10
–4
10
–5
10
–6
10
–7
10
–8
10
–9
10
–10
10
–11
10
–12
10
–13
10
–14
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
DIFFERENTIAL INPUT VOLTAGE (±V)
INPUT BIAS CURRENT (A)
00845-011
+I
IN
–I
IN
Figure 11. Input Bias Current vs. Differential Input Voltage
15.0 100
10
1
0.1
0.01
12.5
10.0
7.5
5.0
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
VOLTAGE NOISE (nV/ Hz)
CURRENT NOISE (fA/ Hz)
00845-012
f = 1kHz
VOLTAGE NOISE
CURRENT NOISE
Figure 12. Voltage and Current Noise Spectral Density vs. Temperature
1k
100
10
1
1k 10
k
100k 1M 10M 100M 1G
SOURCE RESISTANCE (Ω)
VOLTAGE NOISE (µV p-p)
00845-013
NOISE BANDWIDTH: 0.1Hz TO 10Hz
Figure 13. Input Voltage Noise vs. Source Resistance
50
40
30
20
10
0
0123
INPUT VOLTAGE NOISE (µV p-p)
PERCENTAGE OF UNITS
00845-014
SAMPLE SIZE = 344
f = 0.1Hz TO 10Hz
Figure 14. Typical Distribution of Input Voltage Noise
1k
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
VOLTAGE NOISE (REFERRED TO INPUT) (nV/ Hz)
00845-015
Figure 15. Input Voltage Noise Spectral Density
AD795
Rev. C | Page 8 of 20
30
25
20
15
10
5
–60 –40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
SHORT-CIRCUIT CURRENT (mA)
00845-016
–OUTPUT CURRENT
+OUTPUT CURRENT
Figure 16. Short-Circuit Current Limit vs. Temperature
10
8
6
4
2
0
–2
–4
–6
–8
–10
34567891011
SETTLING TIME (µs)
OUTPUT SWING FROM 0 TO ±V
00845-017
ERROR
0.1%
0.01%
0.1%
0.01%
Figure 17. Output Swing and Error vs. Settling Time
1000
900
800
700
600
500
400
300
200
100
0
–15 –10 –5 0 5 10 15
INPUT COMMON-MODE VOLTAGE (V)
ABSOLUTE INPUT ERROR VOLTAGE (µV)
00845-018
Figure 18. Absolute Input Error Voltage vs. Input Common-Mode Voltage
120
100
80
60
40
20
0
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
00845-019
–PSRR
+PSRR
Figure 19. Power Supply Rejection vs. Frequency
120
100
80
60
40
20
0
1 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
COMMON-MODE REJECTION (dB)
00845-020
Figure 20. Common-Mode Rejection vs. Frequency
120
100
80
60
40
20
0
–20
120
100
80
60
40
20
0
–20
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
PHASE MARGIN (Degrees)
00845-021
PHASE
GAIN
Figure 21. Open-Loop Gain and Phase Margin vs. Frequency
AD795
Rev. C | Page 9 of 20
30
25
20
15
10
5
0
1k 10k 100k 1M
FREQUENCY (Hz)
OUTPUT VOLTAGE (V p-p)
00845-022
R
L
= 10kΩ
Figure 22. Large Signal Frequency Response
1000
100
10
1
0.1
1k 10k 100k
FREQUENCY (Hz)
1M 10M
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
00845-023
Figure 23. Closed-Loop Output Impedance vs. Frequency
–
60
–70
–80
–90
–100
–110
–120
100 1k 10k 100k
FREQUENCY (Hz)
THD (dB)
00845-024
V
IN
= 3V rms
R
L
= 10kΩ
Figure 24. Total Harmonic Distortion vs. Frequency
2.0
1.5
1.0
0.5
0
0 5 10 15 20
SUPPLY VOLTAGE (±V)
QUIESCENT SUPPLY CURRENT (mA)
00845-025
Figure 25. Quiescent Supply Current vs. Supply Voltage
50
40
30
20
10
0
–500 –400 –300 –200 –100 0 100 200 300 400 500
INPUT OFFSET VOLTAGE (µV)
PERCENTAGE OF UNITS
00824-026
SAMPLE SIZE = 1419
Figure 26. Typical Distribution of Input Offset Voltage
7
4
3
6
2
10k
Ω
10kΩ
+V
S
V
IN
V
OUT
–V
S
0.1µF
0.1µF
C
L
100pF
R
L
10kΩ
AD795
00845-027
Figure 27. Unity Gain Inverter
AD795
Rev. C | Page 10 of 20
0
0845-028
100
90
10
0%
20V 5µs
5V
Figure 28. Unity Gain Inverter Large Signal Pulse Response
0
0845-029
100
90
10
0%
10mV 500ns
Figure 29. Unity Gain Inverter Small Signal Pulse Response
7
4
3
6
2
+V
S
V
IN
V
OUT
–V
S
0.1µF
0.1µF
C
L
100pF
R
L
10kΩ
AD795
00845-030
Figure 30. Unity Gain Follower
0
0845-031
100
90
10
0%
20V 5µs
5V
Figure 31. Unity Gain Follower Large Signal Pulse Response
0
0845-032
100
90
10
0%
20mV 500ns
Figure 32. Unity Gain Follower Small Signal Pulse Response
AD795
Rev. C | Page 11 of 20
MINIMIZING INPUT CURRENT
The AD795 is guaranteed to 1 pA maximum input current
with ±15 V supply voltage at room temperature. Careful atten-
tion to how the amplifier is used is necessary to maintain this
performance.
The amplifier’s operating temperature should be kept as low as
possible. Like other JFET input amplifiers, the AD795’s input
current doubles for every 10°C rise in junction temperature
(illustrated in Figure 9). On-chip power dissipation raises the
device operating temperature, causing an increase in input
current. Reducing supply voltage to cut power dissipation
reduces the AD795’s input current (see Figure 7). Heavy output
loads can also increase junction temperature; maintaining a
minimum load resistance of 10 kΩ is recommended.
AD795
Rev. C | Page 12 of 20
CIRCUIT BOARD NOTES
The AD795 is designed for mounting on printed circuit boards
(PCBs). Maintaining picoampere resolution in those environ-
ments requires a lot of care. Both the board and the amplifier’s
package have finite resistance. Voltage differences between the
input pins and other pins as well as PCB metal traces causes
parasitic currents (see Figure 33) larger than the AD795’s input
current unless special precautions are taken. Two methods of
minimizing parasitic leakages include guarding of the input lines
and maintaining adequate insulation resistance.
Figure 34 and Figure 35 show the recommended guarding
schemes for noninverting and inverting topologies. Pin 1 is not
connected, and can be safely connected to the guard. The high
impedance input trace should be guarded on both edges for its
entire length.
00845-033
3
6
2
AD795
+
–
V
OUT
C
F
V
E
V
S
I
P
I
S
R
F
C
P
R
P
V
S
I
P
= V
S
R
P
dC
P
dT
dV
dT C
P
++
Figure 33. Sources of Parasitic Leakage Currents
00845-034
NOTES
1. ON THE “R” PACKAGE PIN 1, PIN 5, AND PIN 8 ARE OPEN
AND CAN BE CONNECTED TO ANALOG COMMON OR TO
THE DRIVEN GUARD TO REDUCE LEAKAGE.
3
6
2
AD795
+
–
V
OUT
C
F
I
S
R
F
GUARD
1
2
3
4
8
7
6
5
TOP VIEW
(“R” PACKAGE)
8
7
6
5
Figure 34. Guarding Scheme—lnverter
00845-035
GUARD TRACES
INPUT
T
RACE
1
2
3
4
8
7
6
5
AD795
TOP VIEW
8
7
6
5
CONNECT TO JUNCTION OF
R
F
AND R
I
OR TO PIN 6 FOR
UNITY GAIN.
2
6
3
AD795
+
V
OUT
V
S
R
F
GUARD
R
I
–
Figure 35. Guard Scheme—Follower
AD795
Rev. C | Page 13 of 20
Leakage through the bulk of the circuit board can still occur
with the guarding schemes shown in Figure 34 and Figure 35.
Standard G10 type PCB material may not have high enough
volume resistivity to hold leakages at the sub-picoampere level
particularly under high humidity conditions. One option that
eliminates all effects of board resistance is shown in Figure 36.
The AD795’s sensitive input pin (either Pin 2 when connected
as an inverter, or Pin 3 when connected as a follower) is bent up
and soldered directly to a Teflon® insulated standoff. Both the
signal input and feedback component leads must also be
insulated from the circuit board by Teflon standoffs or low
leakage shielded cable.
00845-036
AD795
1
2
3
4
8
7
6
5
AD795
8
7
6
5
INPUT SIGNAL
LED
PC
BOARD
INPUT PIN:
PIN 2 FOR INVERTER
OR PIN 3 FOR FOLLOWER.
TEFLON INSULATED STANDOFF
Figure 36. Input Pin to Insulating Standoff
Contaminants such as solder flux on the board’s surface and on
the amplifier’s package can greatly reduce the insulation resistance
between the input pin and those traces with supply or signal
voltages. Both the package and the board must be kept clean
and dry. An effective cleaning procedure is to first swab the
surface with high grade isopropyl alcohol, then rinse it with
deionized water and, finally, bake it at 100°C for 1 hour. Poly-
propylene and polystyrene capacitors should not be subjected to
the 100°C bake because they can be damaged at temperatures
greater than 80°C.
Other guidelines include making the circuit layout as compact
as possible and reducing the length of input lines. Keeping
circuit board components rigid and minimizing vibration
reduce triboelectric and piezoelectric effects. All precision high
impedance circuitry requires shielding from electrical noise and
interference. For example, a ground plane should be used under
all high value (that is, greater than 1 MΩ) feedback resistors. In
some cases, a shield placed over the resistors, or even the entire
amplifier, may be needed to minimize electrical interference
originating from other circuits. Referring to the equation in
Figure 33, this coupling can take place in either, or both, of two
different forms via time varying fields:
P
C
d
T
dV
or by injection of parasitic currents by changes in capacitance
due to mechanical vibration:
V
d
T
dCp
Both proper shielding and rigid mechanical mounting of
components help minimize error currents from both of these
sources.
OFFSET NULLING
The circuit in Figure 37 can be used when the amplifier is used
as an inverter. This method introduces a small voltage in series
with the amplifier’s positive input terminal. The amplifier’s input
offset voltage drift with temperature is not affected. However,
variation of the power supply voltages causes offset shifts.
00845-037
3
6
2
AD795
+
–
V
OUT
+V
S
–V
S
V
I
R
I
R
F
499kΩ499kΩ
0.1µF
200Ω
100kΩ
Figure 37. Alternate Offset Null Circuit for Inverter
AD795
Rev. C | Page 14 of 20
AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE
Source and feedback resistances greater than 100 kΩ magnifies
the effect of input capacitances (stray and inherent to the
AD795) on the ac behavior of the circuit. The effects of
common-mode and differential input capacitances should be
taken into account because the circuit’s bandwidth and stability
can be adversely affected.
In a follower, the source resistance, RS, and input common-
mode capacitance, CS (including capacitance due to board and
capacitance inherent to the AD795), form a pole that limits
circuit bandwidth to 1/2 π RSCS. Figure 38 shows the follower
pulse response from a 1 MΩ source resistance with the
amplifier’s input pin isolated from the board; only the effect of
the AD795’s input common-mode capacitance is seen.
0
0845-038
100
90
10
0%
10mV 5µs
Figure 38. Follower Pulse Response from 1 MΩ Source Resistance
In an inverting configuration, the differential input capacitance
forms a pole in the circuit’s loop transmission. This can create
peaking in the ac response and possible instability. A feedback
capacitance can be used to stabilize the circuit. The inverter
pulse response with RF and RS equal to 1 MΩ and the input pin
isolated from the board appears in Figure 39. Figure 40 shows
the response of the same circuit with a 1 pF feedback
capacitance. Typical differential input capacitance for the
AD795 is 2 pF.
0
0845-039
100
90
10
0%
10mV 5µs
Figure 39. Inverter Pulse Response with 1 MΩ Source and Feedback
Resistance
0
0845-040
100
90
10
0%
10mV 5µs
Figure 40. Inverter Pulse Response with 1 MΩ Source and Feedback
Resistance, 1 pF Feedback Capacitance
AD795
Rev. C | Page 15 of 20
OVERLOAD ISSUES
Driving the amplifier output beyond its linear region causes
some sticking; recovery to normal operation is within 2 μs of
the input voltage returning within the linear range.
If either input is driven below the negative supply, the amplifier’s
output is driven high, causing a phenomenon called phase
reversal. Normal operation is resumed within 30 μs of the input
voltage returning within the linear range.
Figure 41 shows the AD795’s input bias currents vs. differential
input voltage. Picoamp level input current is maintained for
differential voltages up to several hundred millivolts. This
behavior is only important if the AD795 is in an open-loop
application where substantial differential voltages are produced.
10
–4
10
–5
10
–6
10
–7
10
–8
10
–9
10
–10
10
–11
10
–12
10
–13
10
–14
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6
DIFFERENTIAL INPUT VOLTAGE (±V)
INPUT BIAS CURRENT (A)
00845-041
+I
IN
–I
IN
Figure 41. Input Bias Current vs. Differential Input Voltage
INPUT PROTECTION
The AD795 safely handles any input voltage within the supply
voltage range. Some applications may subject the input terminals
to voltages beyond the supply voltages. In these cases, the
following guidelines should be used to maintain the AD795’s
functionality and performance.
If the inputs are driven more than a 0.5 V below the minus
supply, milliamp level currents can be produced through the
input terminals. That current should be limited to 10 mA for
transient overloads (less than 1 second) and 1 mA for continuous
overloads. This can be accomplished with a protection resistor
in the input terminal (as shown in Figure 42 and Figure 43).
The protection resistor’s Johnson noise adds to the amplifier’s
input voltage noise and impacts the frequency response.
Driving the input terminals above the positive supply causes the
input current to increase and limit at 40 μA. This condition is
maintained until 15 V above the positive supply—any input
voltage within this range does not harm the amplifier. Input
voltage above this range causes destructive breakdown and
should be avoided.
00845-042
3
6
2
AD795
C
F
R
P
R
F
SOURCE
Figure 42. Inverter with Input Current Limit
00845-043
2
6
3
AD795
R
P
SOURCE
Figure 43. Follower with Input Current Limit
Figure 44 is a schematic of the AD795 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Low leakage diodes
(less than 1 pA), such as the FD333s should be used, and should
be shielded from light to keep photocurrents from being
generated. Even with these precautions, the diodes measurably
increase the input current and capacitance.
To achieve the low input bias currents of the AD795, it is not
possible to use the same on-chip protection as used in other
Analog Devices, Inc., op amps. This makes the AD795 sensitive
to handling and precautions should be taken to minimize ESD
exposure whenever possible.
00845-044
3
6
2
AD795
R
F
PROTECTED DIODES
(LOW LEAKAGE)
SOURCE
Figure 44. Input Voltage Clamp with Diodes
00845-045
38
6
2
AD795
10p
F
OUTPUT
1GΩ
GUARD
PHOTODIODE
FILTERED
OUTPUT
OPTIONAL 26Hz
FILTER
Figure 45. AD795 Used as a Photodiode Preamplifier
AD795
Rev. C | Page 16 of 20
PREAMPLIFIER APPLICATIONS
The low input current and offset voltage levels of the AD795
together with its low voltage noise make this amplifier an
excellent choice for preamplifiers used in sensitive photodiode
applications. In a typical preamp circuit, shown in Figure 45,
the output of the amplifier is equal to:
VOUT = ID (Rf) = Rp (P) Rf
where:
ID is the photodiode signal current, in amps (A).
Rp is the photodiode sensitivity, in amps/watt (A/W).
Rf is the value of the feedback resistor, in ohms (Ω).
P is the light power incident to photodiode surface, in watts (W).
An equivalent model for a photodiode and its dc error sources
is shown in Figure 46. The amplifier’s input current, IB, contri-
butes an output voltage error, which is proportional to the value
of the feedback resistor. The offset voltage error, VOS, causes a
dark current error due to the photodiode’s finite shunt resistance,
Rd. The resulting output voltage error, VE, is equal to:
VE = (1 + Rf/Rd) VOS + Rf IB
A shunt resistance on the order of 109 Ω is typical for a small
photodiode. Resistance Rd is a junction resistance, which
typically drops by a factor of two for every 10°C rise in
temperature. In the AD795, both the offset voltage and drift are
low, which helps minimize these errors.
RDIDIB
CD
50pF
CF
10pF
VOS
RF
1GΩ
PHOTODIODE
OUTPUT
00845-046
Figure 46. A Photodiode Model Showing DC Error Sources
MINIMIZING NOISE CONTRIBUTIONS
The noise level limits the resolution obtainable from any
preamplifier. The total output voltage noise divided by the
feedback resistance of the op amp defines the minimum
detectable signal current. The minimum detectable current
divided by the photodiode sensitivity is the minimum
detectable light power.
Sources of noise in a typical preamp are shown in Figure 47.
The total noise contribution is defined as:





2
2
2
2
2
2
1
1
1
1
RfCfs
RdCds
Rd
Rf
en
RfCfs
Rf
isifinV
OUT
R
D
I
S
C
D
50pF
C
F
10pF
R
F
1GΩ
PHOTODIODE
OUTPUT
00845-047
en
I
N
I
F
I
S
Figure 47. Noise Contributions of Various Sources
Figure 48, a spectral density vs. frequency plot of each source’s
noise contribution, shows that the bandwidth of the amplifier’s
input voltage noise contribution is much greater than its signal
bandwidth. In addition, capacitance at the summing junction
results in a peaking of noise gain in this configuration. This
effect can be substantial when large photodiodes with large shunt
capacitances are used. Capacitor Cf sets the signal bandwidth
and limits the peak in the noise gain. Each source’s rms or root-
sum-square contribution to noise is obtained by integrating the
sum of the squares of all the noise sources and then by
obtaining the square root of this sum. Minimizing the total area
under these curves optimizes the preamplifier’s overall noise
performance.
An output filter with a passband close to that of the signal can
greatly improve the preamplifier’s signal to noise ratio. The
photodiode preamplifier shown in Figure 47, without a bandpass
filter, has a total output noise of 50 μV rms. Using a 26 Hz
single-pole output filter, the total output noise drops to 23 μV
rms, a factor of 2 improvement with no loss in signal bandwidth.
10µ
1µV
100nV
10nV
1 10 100 1k 10k 100k
FREQUENCY (Hz)
OUTPUT VOLTAGE NOISE (V/ Hz)
00845-048
SIGNAL BANDWIDTH
WITH FILTER
NO FILTER
en
I
N
I
Q
AND I
F
Figure 48. Voltage Noise Spectral Density of the Circuit of Figure 47 With and
Without an Output Filter
AD795
Rev. C | Page 17 of 20
USING A T NETWORK
A T network, shown in Figure 49, can be used to boost the
effective transimpedance of an I-to-V converter, for a given
feedback resistor value. However, amplifier noise and offset
voltage contributions are also amplified by the T network gain.
A low noise, low offset voltage amplifier, such as the AD795,
is needed for this type of application.
00845-049
10pF
V
OUT
R
F
100MΩ
R
I
1.1kΩ
R
G
10kΩ
PHOTODIODE
AD795
V
OUT
= I
D
R
F
(1 + )
R
G
R
I
Figure 49. Photodiode Preamp Employing a T Network for Added Gain
A QH PROBE BUFFER AMPLIFIER
A typical pH probe requires a buffer amplifier, shown in Figure 50,
to isolate its 106 Ω to 109 Ω source resistance from external
circuitry. The low input current of the AD795 allows the voltage
error produced by the bias current and electrode resistance to
be minimal. The use of guarding, shielding, high insulation
resistance standoffs, and other such standard methods used to
minimize leakage are all needed to maintain the accuracy of this
circuit.
The slope of the pH probe transfer function, 50 mV per pH
unit at room temperature, has a 3300 ppm/°C temperature
coefficient. The buffer of Figure 50 provides an output voltage
equal to 1 V/pH unit. Temperature compensation is provided
by resistor RT, which is a special temperature compensation
resistor, Part Number Q81, 1 kΩ, 1%, 3500 ppm/°C, available
from Tel Labs, Inc.
00845-050
2
8
7
1
4
5
6
3
AD795
OUTPUT
1V/pH UNIT
19.6kΩ
RT
1kΩ
3500ppm/°C
V
OS
ADJUST
100kΩ
GUARD
–V
S
+V
S
0.1µF
0.1µF
+V
S
–V
S
+15V
COM
–15V
PH
PROBE
Figure 50. pH Probe Amplifier
AD795
Rev. C | Page 18 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 51. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD795JR 0°C to +70°C 8-Lead SOIC_N R-8
AD795JR-REEL 0°C to +70°C 8-Lead SOIC_N R-8
AD795JR-REEL7 0°C to +70°C 8-Lead SOIC_N R-8
AD795JRZ 0°C to +70°C 8-Lead SOIC_N R-8
AD795JRZ-REEL 0°C to +70°C 8-Lead SOIC_N R-8
AD795JRZ-REEL7 0°C to +70°C 8-Lead SOIC_N R-8
1 Z= RoHS Compliant Part.
AD795
Rev. C | Page 19 of 20
NOTES
AD795
Rev. C | Page 20 of 20
NOTES
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00845-0-12/09(C)