NS TES es FUJITSU Ba LUes I ieee MOS 262144 BIT UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY MBM 27256-17 MBM 27256-20 MBM 27256-25 February 1986 Edition 3.0 The Fujitsu MBM 27256 is a high speed 262,144-bit static NMOS erasable and electrically reprogrammable read only memory (EPROM). It is especially weil suited for applications where rapid turn-around and/or bit pattern experimen- tation are important. A 28-pin Dual In-Line package and a 32-pad Leadless Chip Carrier with a trans- parent lid is used to package the MBM 27256. The transparent lid allows the user to expose the device to ultraviolet light in order to erase the memory bit pattern previously programmed. At the completion of erasure, a new pattern can then be written into the memory. The MBM 27256 is fabricated using NMOS double polysilicon gate tech- nology with single transistor stacked gate cells. !t is organized as 32,768 words by 8 bits for use in microprocessor apptications. Single +5V operation greatly facilitates its use in systems. CERAMIC PACKAGE DIP-28C-C01 @ 32,768 words x 8 bits organiza- @ Fast access time: tion, fully decoded @ Single location programming @ Programmable utilizing the Quick Pro algorithm @ Program voltage: 12.5V Low power requirement Active: 525mW Standby: 210mW @ No clocks required (fully static operation) Output Enable {OE) pin for simple memory expansion 170ns max. (MBM 27256-17) 200ns max. (MBM 27256-20) 250ns max. (MBM 27256-25) @ TTL compatible inputs/outputs @ Three-state output with OR-tie capability @ Single +5V supply, 5% tolerance @ Standard 28-pin Ceramic (Cerdip) DIP: Suffix-Z Standard 32-pad Ceramic LCC: Suffix-CV ABSOLUTE MAXIMUM RATINGS (see NOTE) Rating Symbol Value Unit Supply Voltage with Respect to GND Vee ~0.6 to +7 Vv Veep Voltage with Respect to GND Vep -0.6 to +14 Vv Voltage on Ag with Respect to GND Vag -0.6 to +13.5 Vv with Rewect GND Vin, Vout ~0.6 to +7 v Temperature under Bias Teas ~25 to +85 c Storage Temperature Tsts -65 to +125 c NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Quick ProT jis a trade mark of FUJITSU LIMITED CERAMIC PACKAGE LCC-32C-A01 PIN ASSIGNMENT This device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this high impedance circuit. 5-15IR BM 27256-17 FUJITSU 27256-20 MBM MIO MBM. 27256-25 Fig. 1 - MBM 27256 BLOCK DIAGRAM 0, 0g OE*|__ OUTPUT ENABLE & OUTPUT CHIP ENABLE & BUFFER CE PROGRAM LOGIC - Do DATA INPUT BUFFER & PROGRAMMING CONTROL : 0, Og ? oe Yo COLUMN > TING oT COLUMN : GA A : DECODER : 5-H Yes | 512x512 Xo CELL MATRIX Ag ____] * ROW A : DECODER 1.4 \} X54 Vep Vee GNO CAPACITANCE ta = 25c, = 1 MHz) Parameter Symbol Min Typ Max Unit Input Capacitance (Vj, = OV) Cin 4 6 pF Output Capacitance (Voy7 = OV) Court 8 12 pF 5-16FUNCTIONS AND PIN CONNECTIONS MBM 27256-17 ill HIM MBM 27256-20 MBM 27256-25. JiliililiN0Miiihih FUJITSU (rin) [Adsressimput |g, | Oat | ce | GE | ce | Upp | GND Mode 23, 25 ~ 27} (24) 15 ~ 19) (20) {22} (28) (1) (14) Read AIN Ain Dour Vin Vit +5V +5V GND Output Disable Ain An High-Z Vin Vin +5V +5V GND Standby Dont Care Don't Care High-Z Vin Dont Care +5V +5V GND Program Ain Ain Din Vin Vin +6V +12,.5V GND Program Verify Ain Ain Dout Don't Care Vin +6V 4+12,5V GND Program Inhibit Dont't Care | Dont Care High-2 Vin Vin t+6V +12,5V GND Electronic Signature Ain +12V Code Vin Vin +5V +5V GND RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Unit Voc Supply Voltate* Vec 4.75 5.0 5.25 Vv Vpp Supply Voltage Vpp Veco -0.6 Vec +0.6 Vv Input High Voltage Vin 2.0 Vee +1 Vv Input Low Valtage Vit -0.1 0.8 Vv Operating Temperature Ta 0 70 c Note:* Vcc must be applied either before or coincident with Vpp and removed either after or coincident with Vpp. DC CHA RACTERISTICS noted} Parameter Symbol Min Typ Max Unit Input Load Current (Vj), = 5.25V) Hail 10 uA Output Leakage Current (Vgy7 = 5.25V} ItLol 10 LA Vee Standby Current (CE = V,4) leer 40 mA Voc Supply Current (CE = Vj.) lece 100 mA Vpp Supply Current (Vpp = Vec + 0.6V) lppa 5 mA Output Low Voltage (lo. = 2.1mA) Vou 0.45 Vv Output High Voltage (lou = ~400uA} Vou 2.4 Vv 5-17AOS BMA 27256-17 FUJITSU MBM 27256-20 HAHA! MBM 27256-25 Input Pulse Levels: Input Rise and Fall Times: Output Load: Timing Measurement Reference Levels: 0.45V to 2.4V <20ns 0.8V and 2.0V for inputs 0.8V and 2.0V for outputs, T TTL gate and C, = 100pF Fig.2 AC TEST CONDITIONS (INCLUDING PROGRAMMING) Tb L AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted) MBM 27256-17 MBM 27256-20 MBM 27256-25 Parameter Symbol Unit Min | Typ | Max | Min | Typ | Max | Min | Typ | Max Address Access Time*1(CE = OE = Vi.) tacc 170 200 250 | ns CE to Output Delay (OE = Vj) tce 170 200 250 | ns OE to Output Delay? (CE = Vi_) tor 75 75 100 | ns Address to Output Hold ton 0 0 0 ns Output Enable High to Output Float"? | tore 0 60 0 60 0 105 | ns Notes: i OE may be delayed up to tacc tog after the falling edge of CE without impact on tacc. 2 tpg is specified from OE or CE, whichever occurs first. Output Float is defined as the point where data is no longer driven. ADDRESS vin Vit~ cE Vin- Vir~ _ View OE Vit~ Von output (OH You- OPERATION TIMING DIAGRAM ADDRESS VALID VALID OUTPUT 5-18MBM 27256-17 _ ili MBM 27256-20 FUJITSU 2 MBM 27256-25 ill iitiliitit CHARACTERISTICS CURVES Fig. 3 SUPPLY CURRENT (STANDBY) Fig. 4 SUPPLY CURRENT (SFANDBY} vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE 1.21-T, = 25C NORMALIZED SUPPLY CURRENT loci, NORMALIZED SUPPLY CURRENT lec. 4 0 sO 1 Vee, SUPPLY VOLTAGE (V) Ta, AMBIENT TEMPERATURE (C) Fig. 5 SUPPLY CURRENT {ACTIVE) Fig. G SUPPLY CURRENT (ACTIVE) vs. AMBIENT TEMPERATURE vs. SUPPLY VOLTAGE Ty = 28C 1.2--Vec= 5V 2 Q Icez. NORMALIZED SUPPLY CURRENT lec2, NORMALIZED SUPPLY CURRENT 4 5 6 700 Voc, SUPPLY VOLTAGE (V} Ta. AMBIENT TEMPERATURE (C) Fig. 7 - ADDRESS ACCESS TIME Fig. 8 - ADDRESS ACCESS TIME vs. SUPPLY VOLTAGE vs. AMBIENT TEMPERATURE 2 Ta = 25C 3 Vee =5V w 1 ut o oc a a Zw 15 Ow IS az a= aE we N Na 783 10 cw a W =o 2S ay oe S 2 5 1.0 51 2 5 4 5 6 0 50 100 Voc, SUPPLY VOLTAGE (V) Ta. AMBIENT TEMPERATURE (C) 5-19Kini! MBM 27256-17 FUJITSU 27256-20 i! MBM 27256-25 5-20 tog. NORMALIZED OF TO OUTPUT DELAY Fig. 9 CE TO OUTPUT DELAY vs. AMBIENT TEMPERATURE cc = 5V = w tce, NORMALIZED CE TO OUTPUT DELAY 100 Ta, AMBIENT TEMPERATURE (C} Fig. 11 OE TO OUTPUT DELAY OE HIGH TO OUTPUT FLOAT vs. AMBIENT TEMPERATURE cc on ----tpr, NORMALIZED OE HIGH TO OUTPUT FLOAT = Q 50 100 Ta, AMBIENT TEMPERATURE (C) Fig. 13 - OUTPUT SINK CURRENT vs. OUTPUT LOW VOLTAGE nN a Vee = 5V Ta = 25C lor, OUTPUT SINK CURRENT (mA) 3 0 1 Vor, OUTPUT LOW VOLTAGE (Vv) Fig. 10 CE TO OUTPUT DELAY vs. SUPPLY VOLTAGE Ta =25C _ a tce, NORMALIZED CE To OUTPUT DELAY o 4 5 6 Voc, SUPPLY VOLTAGE (Vv) Fig. 12 ~ OUTPUT SOURCE CURRENT vs. OUTPUT HIGH VOLTAGE cc Ta =28 4 do low, OUTPUT SOURCE CURRENT (mA) 3 3.5 4 Vou. OUTPUT HIGH VOLTAGE (Vv) Fig. 14 - ADDRESS ACCESS TIME vs. LOAD CAPACITANCE 2 Veo = 5V WwW 1.5'-T, = 25C & A Qa tw a2 We Na dw $9 20 ot 10 2 3 s 0 200 400 C_, LOAD CAPACITANCE ipF)MBM 27256-17 illite MBM 27256-20 FUJITSU MBM 27256-25,IIIIFlIhiiilil PROGRAMMING/ERASING INFORMATION PROGRAMMING Upon delivery from Fujitsu, or after each erasure (see Erasure section), the MBM 27256 has all 262,144 bits in the 1 or high state. O's are loaded into the MBM 27256 through the procedure of programming. The MBM 27256 is programmed with a fast programming algorithm designed by Fujitsu called Quick Pro. The pro- gramming mode is entered when +12.5V and +6V are applied to Vpp and Voc respectively, and CE and OE are Viy. A 0.1nF capacitor between Vpp and GND is needed to prevent excessive voltage transients which could damage the device. The address to be pro- grammed is applied to the proper address pins. The 8 bit data pattern to be written is placed on the respective data output pins. The voltage levels should be standard TTL levels. When both the address and data are stable, a tms programming pulse is applied to ERASURE In order to clear all locations of their programmed contents it is necessary to expose the MBM 27256 to an ultra violet light source. A dosage of 15 W- seconds/cm? is required to completely erase an MBM 27256. This dosage can be obtained by exposure to an ultra- violet lamp (wavelength of 2537 Ang- stroms (A)) with intensity of 12000uW/ cm? far 15 to 21 minutes. ELECTRONIC SIGNATURE The MBM 27256 has electronic sig- nature mode which is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its cor- ieee Fe ce Be CE and after that one additional pulse which is 3 times as wide as previous pulse is applied to CE to accomplish the programming. Procedure of Quick Pro (Refer to the attached flowchart.) 1) Set the start address (=G) at the address pins. __ 2) Set Vcc = 6V, Vpp = 12.5V and CE = Vin. 3) Clear the programming pulse coun- ter (X <Q}. Input data to respective pins. Apply ONE programming pulse (tpy = Ims Typ.) to CE. Increment the counter (X < X+1), Compare the number (=X) of applied programming pulse with 25 and then verify the programmed data. If programmed data is veri- fied, go to the next step regardless of X value. If X = 25 and pro grammed data is not verified, the 4) 5) 6) 7) The MBM 27256 should be about one inch from the source and all fitters should be removed from the UV fight source prior to erasure. It is important to note that the MBM 27256 and similar devices, wil! erase with light sources having wave- lengths shorter than 4000A. Although erasure time wil! be much longer than responding programming algorithm. The electronic signature is activated when +12V is applied to address line Ag (pin 24) of the MBM 27256. Two identifier bytes are readed out from the device fails. If X = 25 and pro- grammed data is not verified, go back to the step 5). Apply one additional wide pro- gramming pulse to CE (3X ms}. Compare the address with an end address (=N). Hf the programmed address is the end address, proceed to the next step. If not, increment the address {(G G+1) and then go to the step 3) for the next address. Set Vec = Vpp = SV. Verify the ail programmed data. If the verification succeeds, the pro- gramming completes. If any pro- grammed data is not the same as original data, the device fails. 8) 9 10) 11) A continuous TTL low level should not apply to CE input pin during the program mode (Vpp = 12.5V, Voc = 6V and OE = V\4) because it is required that one programming pulse width does not exceed 78.75 ms at each address. with UV source at 25374, nevertheless the exposure to fluorescent light and sunlight will eventually erase the MBM 27256, and exposure to them should be prevented to realize maxi- mum system reliability. If used in such an environment, the package windows should be covered by an opaque label or substance. outputs by toggling address line Ag (pin 10) from Vi, to Vjy4. The address lines from A, to Ay3 must be hold at Vii to keep the electronic signature mode. See the table below. Ao 0, 02 Og O4 Os Og 0; Og Definition Vin 0 0 1 0 0 0 i Manufacture Vin 0 1 0 0 0 0 0 Device Note: Ag = 12V+0.5V _ A, thru Ag = Ajo thru Ay = CE = OE = Vic Aig = Either Vy or Vin RMN a ae PT ta UE saa a mR TS at Quick Pro is a trademark of FUJITSU LIMITED 5-21IRA ASN 27256-17 FUJITSU 7256-20 MBM 2 hi MBM 27256-25 PROGRAMMING/ERASING INFORMATION (Cont'd) Fig AOMAEOBE, 88 tee ede BE Le 3 m appress V!H ViniVou pata IH/Vou Vir/Vou- Vpp Vpp Vec Vectt- Vee cc Vec tvcs Vina 5 J Vit- PROGRAMMING WAVEFORM Mr Program Verif Additional Program 4 J r tay tps toe tDF tos tou | ae (DH mt ra i { OUTPUT DATA IN STABLE) 4 & VALID DATA IN STABLE \ vps u tpw tc LE tces| tapw qh toes oO Don't Care 3 SWE ae A ata REUSE De ESTE A OES oc ge N NMBM 27256-17 ill MBM 27256-20 FUJITSU MBM 27256-25, ili DC CHARACTERISTICS (Ta = 255C, Voc *1=6VE0.25V, Vpp*2=12.5V40.3V} Parameter Symbol Min Typ input Leakage Current (Viy = 6.25V/0.45V) Hol Vpp Supply Current (CE = V\_, OE = Vin) Ipp2 Vpp Supply Current (OE = V,_) lpps 5 mA Vee Supply Current lees 100 mA input Low Level Vic -0.1 0.8 Vv Input High Level Vin 2.0 Vectl Vv Output Low Voltage During Verify (lo, = 2.1mA) VoL 0.45 Vv Output High Voltage During Verify (loy = -400uA) Vou 2.4 Vv Note: *1 Vcc must be applied either coincidently or before Vap and removed either concidently or after Vpp. *2 Vpp must not be greater than 14 volts including overshoot. Permanent device damage may occur if the device is taken out or put into socket remaining Vpp = 12.5 volts. Also, during CE = V,, OE = Vi, Vpp must not be switched from Vec to Vpp volts or vice versa. AC CHARACTERISTICS (Ta = 255C, Vee = 6V40.25V, Vpp = 12.5V40.3V) Parameter Symbol Min Typ Max Unit Address Setup Time tas 2 us Output Enable Setup Time toes 2 HS Chip Enable Setup Time tees 2 us Data Setup Time tos 2 us Vpp Setup Time typs 2 us Vee Setup Time tvcs 2 us Address Hold Time tay 2 us Data Hold Time toy 2 us Chip Enable Hold Time tceu 2 Bs Output Enable to Output Valid toe 120 ns Output Disable to Output Float Delay tor 105 ns Programming Pulse Width tpw 0.95 1 1.05 ms Programming Pulse Number 1 25 times Additional Programming Pulse width tapw 2.85 78.75 ms RRS Serene, * nN @AANA MAB 27256417 FUJITSU MBM 27: -20 256 HITE! MBM 27256-25 PROGRAMMING/ERASING INFORMATION (Cont'd) PROGRAMMING FLOW CHART Vee = 6V + 0.25 Vpp = 12.5V + 0.3V START ADORESS = G G: START ADDRESS N: STOP AOGRESS X : COUNTER VALUE MAXIMUM 105 ms/BYTE MINIMUM 3.8 ms/BYTE APPLY 1 PROG. PULSE (1ms) VERIFY ONE BYTE APPLY ADDITIONAL PROGRAMMING PULSE (3X ms) ADDRESS + 1 Veo = 5.0V Vpp = 5.0V VERIFY ALL BYTES OK 5-24MBM 27256-17 _ IIlllilililil MBM 27256-20 FUJITSU MBM 27256-25._ IllilINtihiNeiil PACKAGE DIMENSIONS Standerd 28-pin Ceramic DIP (Suffix : -Z) 28-LEAD CERAMIC (CERDIP WITH TRANSPARENT LID} DUAL IN-LINE PACKAGE (CASE No.: DiP-28C-C01) J en a ee a a eee I R .025(0.64) REF .570(14.48} .350(8.89) DIA 95(15.11) .600(15.24) REF TYP, .600(15.24) .625(15.88) Cw esrereertretrteor ts test ts te os or | | 1.435 (36.45) | me 1.500(38.10) ' .008(0.20) 014(0.361 =.100(2.54)MAX .23015.84)MAX .120(3.05) .150(3.81) .090(2.29) 042(1,06) .032(0.81) I .020(0.51) -110(2.793[ .062(7.58) TYP | 501 27) 1.300(33.02) REF ' |_..013(0.33) Dimensions in .023(0.58) inches and (millimeters) 5-25SINCE FUJITSU NNN MBM 27256-25 MBM 27256-17 MBM 27256-20 PACKAGE DIMENSIONS Standerd 32-pad Ceramic LCC (Suffix : -CV) 32-PAD CERAMIC (METAL SEAL) LEADLESS CHIP CARRIER (CASE No. ; LCC-32C-A01) -360(9.14)TYP PIN NO. 4 .01810.38)TYP | A 10002 b4}TP DUdOUG. ft FI = PIN 1 INDEX -400(10.1 28017.111 23811384) R.008(0.20)TYe fy OOP DIA TYP , (32PLCS) .025(0.64) TYP .460(1 1.68) 0501.27) i ee TYP TYP G1 01 1 1] 210) 0) 01 pF -t | | TH f\ 04011.02)TYP > [] fl DOoOnDS (3PLCS) _| rr an 4a L. oastrtaytye . : i 13013. 30)MAX .460(11.68) -300(7.62)TYP Dimensions in * ini . . inches (mitlimeters) Shape of Pin index: Subject to change without notice 5-26