486 Mercury Drive, Sunnyvale, California 94085 Tel: (408) 735-1118 Fax: (408) 735-1119 www.kendin.com
KS89 95E – 5 Port 10/100 Integrated Switch with PHY and Frame Buffers
Introduction
The KS8995E contains five 10/100 physical layer
transceivers, five MAC (Media Access Control) units
with an integrated layer 2 switch. The device runs in
two modes. The first mode is a five port integrated
switch and the second is as a five por t switch with the
fifth port decoupled from the physical port. In this
mode access to the fifth MAC is provided using a
MII (Media Independent Interface).
Useful configurations include a stand alone five port
switch as well as a four port switch with a routing
element connected to the extra MII port. The
additional port is also useful for public network
interfacing.
The KS8995E is designed to reside in an unmanaged
design not requiring processor intervention. This is
achieved through I/O strapping or EEPROM
programming at system reset time
On the media side, the KS8995E supports 10BaseT,
100BaseTX and 100BaseFX as specified by the IEEE
802.3 committee.
Physical signal transmission and reception are
enhanced through use of analog circuitry that makes
the design more efficient and allows for lower power
consumption and smaller chip die size.
The major enhancements from the KS8995 to the
KS8995E are support for VLAN, traffic priority
queuing, EEPROM programming for expanded
control and MDI / MDI-X auto crossover.
Highlights
• 5 port 10/100 Integrated Switch with Physical
Layer Transceivers
• SRAM on chip for frame buffering
• 1.4Gbps high performance memory bandwidth
• 10BaseT, 100BaseTX and 100BaseFX modes of
operation
• Superior analog technology for reduced power
and die size
• Single 2.5 V power supply
• 500 mA (1.25 W) including physical transmit
drivers
• 128 pin PQFP package
• Supports port based VLAN
• Supports DiffServ priority, 802.1p based priority
or port based priority
• Support for UTP or fiber installations
• Indicators for link, activity, full / half duplex and
speed
• Unmanaged operation via strapping or EEPROM
at system reset time
• Hardware based 10/100, full/half, flow control
and auto negotiation
• Individual port forced modes (full duplex,
100BaseTX) when auto negotiation is disabled
• Wire speed reception and transmission
• Integrated address Look-Up Engine, supports 1K
absolute MAC add resses
• Automatic address learning, address aging and
address migration
• Broadcast storm protection
• Full duplex IEEE 802.3x flow control
• Half duplex back pressure flow control
• Comprehensive LED support
• External MAC interface (MII or SNI) for router
applications
• Supports MDI / MDI-X auto crossover
Physical
Transceiver
1
MAC
1
Look Up
Engine
(1K Entries)
SRAM
Buffers
MII / SNI
(exclusive)
External
Interface
Physical
Transceiver
2
MAC
2
Physical
Transceiver
3
MAC
3
Physical
Transceiver
4
MAC
4
Physical
Transceiver
5
MAC
5
FIFO and Flow Control
Queue
Management Buffer
Management
LED
and
Programming
Interface
MRXD[3:0]
MRXDV
MCOL
MTXD[3:0]
MTXEN
MTXER
MII_CLK
RXP[1], RXM[1]
RXP[2], RXM[2]
RXP[3], RXM[3]
RXP[4], RXM[4]
RXP[5], RXM[5]
TXP[1], TXM[1]
TXP[2], TXM[2]
TXP[3], TXM[3]
TXP[4], TXM[4]
TXP[5], TXM[5]
LED[1][3:0]
LED[2][3:0]
LED[3][3:0]
LED[4][3:0]
LED[5][3:0]
MRXD[0]
MRXDV
MCOL
MTXD[0]
MTXEN
MII_CLK
S
N
I
M
I
I
EEPROM
Interface
SCL
SDA