PSoC(R) 4: PSoC 4200L Datasheet Programmable System-on-Chip (PSoC(R)) General Description PSoC(R) 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an ARM(R) Cortex(R)-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200L product family, based on this platform, is a combination of a microcontroller with digital programmable logic, programmable analog, programmable interconnect, secure expansion of memory off-chip, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200L products will be fully compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Features 32-bit MCU Subsystem Serial Communication 48 MHz ARM Cortex-M0 CPU with single-cycle multiply Up to 256 kB of flash with Read Accelerator Up to 32 kB of SRAM DMA engine with 32 channels Programmable Analog Four opamps that operate in Deep Sleep mode at very low current levels All opamps have reconfigurable high current pin-drive, high-bandwidth internal drive, ADC input buffering, and Comparator modes with flexible connectivity allowing input connections to any pin Four current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin Two low-power comparators that operate in Deep Sleep mode Four independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality USB Full-Speed device interface 12 Mbits/sec with Battery Charger Detect capability Two independent CAN blocks for industrial and automotive networking Timing and Pulse-Width Modulation Eight 16-bit timer/counter pulse-width modulator (TCPWM) blocks Center-aligned, Edge, and Pseudo-random modes Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 98 Programmable GPIOs Programmable Digital Eight programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs) 124-ball VFBGA, 64-pin TQFP, 48-pin TQFP, and 68-pin QFN packages Cypress-provided peripheral component library, user-defined state machines, and Verilog input Any of up to 94 GPIO pins can be CapSense, analog, or digital Drive modes, strengths, and slew rates are programmable Low Power 1.71 V to 5.5 V Operation PSoC Creator Design Environment 20-nA Stop Mode with GPIO pin wakeup Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs Capacitive Sensing Two Cypress Capacitive Sigma-Delta (CSD) blocks provide best-in-class SNR (>5:1) and water tolerance Cypress-supplied software component makes capacitive sensing design easy Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) Applications Programming Interface (API component) for all fixed-function and programmable peripherals Industry-Standard Tool Compatibility Automatic hardware tuning (SmartSenseTM) After schematic entry, development can be done with ARM-based industry-standard development tools Segment LCD Drive LCD drive supported on any pin with up to a maximum of 64 outputs (common or segment) Operates in Deep Sleep mode with 4 bits per pin memory Cypress Semiconductor Corporation Document Number: 001-91686 Rev. *I * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised June 8, 2018 PSoC(R) 4: PSoC 4200L Datasheet More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4: Overview: PSoC Portfolio, PSoC Roadmap Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP In addition, PSoC Creator includes a device selection tool. Application notes: Cypress offers a large number of PSoC application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 4 are: AN79953: Getting Started With PSoC 4 AN88619: PSoC 4 Hardware Design Considerations AN86439: Using PSoC 4 GPIO Pins AN57821: Mixed Signal Circuit Board Layout AN81623: Digital Design Best Practices AN73854: Introduction To Bootloaders AN89610: ARM Cortex Code Optimization Technical Reference Manual (TRM) is in two documents: Architecture TRM details each PSoC 4 functional block. Registers TRM describes each of the PSoC 4 registers. Development Kits: CY8CKIT-042, PSoC 4 Pioneer Kit, is an easy-to-use and inexpensive development platform. This kit includes connectors for ArduinoTM compatible shields and Digilent(R) PmodTM daughter cards. CY8CKIT-046, PSoC 4 L-Series Pioneer Kit, is an easy-to-use and inexpensive development platform. This kit includes connectors for ArduinoTM compatible shields. CY8CKIT-049 is a very low-cost prototyping platform. It is a low-cost alternative to sampling PSoC 4 devices. CY8CKIT-001 is a common development platform for any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families of devices. The MiniProg3 device provides an interface for flash programming and debug. PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100 pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can: 3. Configure components using the configuration tools 1. Drag and drop component icons to build your hardware system design in the main design workspace 4. Explore the library of 100+ components 2. Codesign your application firmware with the PSoC hardware, 5. Review component datasheets using the PSoC Creator IDE C compiler Figure 1. Multiple-Sensor Example Project in PSoC Creator Contents 1 2 3 4 5 Document Number: 001-91686 Rev. *I Page 2 of 45 PSoC(R) 4: PSoC 4200L Datasheet Contents PSoC 4200L Block Diagram............................................. 4 Functional Definition........................................................ 5 CPU and Memory Subsystem ..................................... 5 System Resources ...................................................... 5 Analog Blocks.............................................................. 6 Programmable Digital.................................................. 7 Fixed Function Digital.................................................. 8 GPIO ........................................................................... 9 SIO .............................................................................. 9 Special Function Peripherals....................................... 9 Pinouts ............................................................................ 10 Power............................................................................... 15 Unregulated External Supply..................................... 15 Regulated External Supply........................................ 15 Electrical Specifications ................................................ 16 Absolute Maximum Ratings....................................... 16 Device Level Specifications....................................... 16 Analog Peripherals .................................................... 20 Digital Peripherals ..................................................... 25 Document Number: 001-91686 Rev. *I Memory ..................................................................... System Resources .................................................... Ordering Information...................................................... Part Numbering Conventions .................................... Packaging........................................................................ Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Revision History ............................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC(R) Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 28 29 36 37 38 41 43 43 44 45 45 45 45 45 45 Page 3 of 45 PSoC(R) 4: PSoC 4200L Datasheet Figure 2. Block Diagram PSoC 4200L Architecture CPU Subsystem 32-bit AHB- Lite SWD/ TC SPCIF Cortex M0 48 MHz FLASH 256 KB FAST MUL NVIC, IRQMX Read Accelerator SRAM 32 KB ROM 8 KB DataWire/ DMA SRAM Controller ROM Controller Initiator / MMIO System Resources x8 CTBm 2 x OpAmp x2 High Speed I / O Matrix, 1x Programmable I/O Power Modes Active/ Sleep Deep Sleep Hibernate WCO 2x CAN Port Interface & Digital System Interconnect ( DSI) FS-PHY SMX UDB 512B USB-FS x1 ... 2x LP Comparator UDB LCD SAR ADC (12-bit) 4x SCB-I2C/SPI/UART Programmable Digital Programmable Analog CHG-DET Test DFT Logic DFT Analog Peripheral Interconnect (MMIO) PCLK 2x Capsense Reset Reset Control XRES Peripherals 8x TCPWM Clock Clock Control WDT IMO ILO ECO 2 x PLL System Interconnect (Multi Layer AHB ) IOSS GPIO (13x ports) Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches 80 x GPIO, 14 x GPIO_ OVT , 2 x SIO I/ O Subsystem PSoC 4200L Block Diagram The PSoC 4200L devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The ARM Serial_Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator Integrated Development Environment (IDE) provides fully integrated programming and debug support for PSoC 4200L devices. The SWD interface is fully compatible with industry-standard third-party tools. The PSoC 4200L family provides a level of security not possible with multi-chip application solutions or with microcontrollers. This is due to its ability Document Number: 001-91686 Rev. *I to disable debug features, robust flash protection, and because it allows customer-proprietary functionality to be implemented in on-chip programmable blocks. The debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled, PSoC 4200L with device security enabled may not be returned for failure analysis. This is a trade-off the PSoC 4200L allows the customer to make. Page 4 of 45 PSoC(R) 4: PSoC 4200L Datasheet Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in the PSoC 4200L is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. Most instructions are 16 bits in length and execute a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC), which can wake the processor up from the Deep Sleep mode allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a 2-wire form of JTAG; the debug configuration used for PSoC 4200L has four break-point (address) comparators and two watchpoint (data) comparators. Clock System The PSoC 4200L clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no meta-stable conditions occur. The clock system for the PSoC 4200L consists of a crystal oscillator (4 to 33 MHz), a watch crystal oscillator (32 kHz), a phase-locked loop (PLL), the IMO and the ILO internal oscillators, and provision for an external clock. Figure 3. PSoC 4200L MCU Clocking Architecture IMO clk_hf clk_ext PLL #1 ECO PLL #0 (optional ) dsi_in[0] dsi_in[1] dsi_in[2] dsi_in[3] dsi_out[3:0] ILO Flash The PSoC 4200L has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 2 wait-state (WS) access time at 48 MHz and with 1-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. SRAM SRAM memory is retained during Hibernate. SROM A supervisory ROM that contains boot and configuration routines is provided. clk_lf WCO The clk_hf signal can be divided down to generate synchronous clocks for the UDBs, and the analog and digital peripherals. There are a total of 16 clock dividers for the PSoC 4200L, each with 16-bit divide capability; this allows 12 to be used for the fixed-function blocks and four for the UDBs. The analog clock leads the digital clocks to allow analog events to occur before digital clock-related noise is generated. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully supported in PSoC Creator. IMO Clock Source System Resources The IMO is the primary source of internal clocking in the PSoC 4200L. It is trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. IMO tolerance with Cypress-provided calibration settings is 2%. Power System ILO Clock Source The power system is described in detail in the section Power on page 15. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) or interrupts (low voltage detect (LVD)). The PSoC 4200L operates with a single external supply over the range of 1.71 to 5.5 V and has five different power modes, transitions between which are managed by the power system. The PSoC 4200L provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. The ILO is a very low power oscillator, nominally 32 kHz, which is primarily used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Cypress provides a software component, which does the calibration. DMA A DMA engine is provided that can do 32-bit transfers and has chainable ping-pong descriptors. Document Number: 001-91686 Rev. *I Crystal Oscillators and PLL The PSoC 4200L clock subsystem also implements two oscillators: high-frequency (4 to 33 MHz) and low-frequency (32-kHz watch crystal) that can be used for precision timing applications. The PLL can generate a 48-MHz output from the high-frequency oscillator. Page 5 of 45 PSoC(R) 4: PSoC 4200L Datasheet external reference through a GPIO pin. The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. The system performance will be 65 dB for true 12-bit precision if appropriate references are used and system noise levels permit. To improve performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. Watchdog Timer A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. Reset The PSoC 4200L can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration. The SAR is connected to a fixed set of pins through an 8-input sequencer (expandable to 16 inputs). The sequencer cycles through selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, the aggregate sampling bandwidth is equal to 1 Msps, whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware-driven switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. In addition, the signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. Voltage Reference The PSoC 4200L reference system generates all internally required references. A 1% voltage reference spec is provided for the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and better absolute accuracy, it is possible to add an external bypass capacitor to the internal reference using a GPIO pin or to use an external reference for the SAR. Analog Blocks 12-bit SAR ADC The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperature-dependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V. The block functionality is augmented for the user by adding a reference buffer to it (trimmable to 1%) and by providing the choice (for the PSoC 4200L case) of three internal voltage references: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an Figure 4. SAR ADC System Diagram AHB System Bus and Programmable Logic Interconnect SARSEQ vminus vplus P7 Port 2 (8 inputs) SARMUX P0 Sequencing and Control Data and Status Flags POS SARADC NEG External Reference and Bypass (optional) Reference Selection VDD/2 VDDD VREF Inputs from other Ports Document Number: 001-91686 Rev. *I Page 6 of 45 PSoC(R) 4: PSoC 4200L Datasheet Analog Multiplex Bus The PSoC4200L has two concentric analog buses (Analog Mux Bus A and Analog Mux Bus B) that circumnavigate the periphery of the chip. These buses can transport analog signals from any pin to various analog blocks (including the opamps) and to the CapSense blocks allowing, for instance, the ADC to monitor any pin on the chip. These buses are independent and can also be split into three independent sections. This allows one section to be used for CapSense purposes, one for general analog signal processing, and the third for general-purpose digital peripherals and GPIO. Four Opamps (CTBm Blocks) The PSoC 4200L has four opamps with Comparator modes, which allow most common analog functions to be performed on-chip eliminating external components; PGAs, voltage buffers, filters, trans-impedance amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering. The opamps can operate in the Deep Sleep mode at very low power levels. The following diagram shows one of two identical opamp pairs of the opamp subsystem. Temperature Sensor The PSoC 4200L has one on-chip temperature sensor. This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using Cypress-supplied software that includes calibration and linearization. Low-power Comparators The PSoC 4200L has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid meta-stability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator switch event. To SAR ADC Universal Digital Blocks (UDBs) and Port Interfaces OA0 + P0 The opamps operate in Deep Sleep mode at very low currents allowing analog circuits to remain operational during Deep Sleep. Programmable Digital To SAR ADC Analog Mux Bus B Analog Mux Bus A Figure 5. Identical Opamp Pairs in Opamp Subsystem to any pin on the chip. Analog switch connectivity is controllable by user firmware as well as user-defined programmable digital state machines (implemented via UDBs). - The PSoC 4200L has eight UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control. The UDB array is shown in the following figure. 10x 1x Figure 6. UDB Array Internal Out0 AHB Bridge CPUSS Dig CLKS P1 8 to 32 P2 UDBIF OA1 - P6 + BUS IF 1x 10x Internal Out1 P7 The ovals in Figure 5 represent analog switches, which may be controlled via user firmware, the SAR sequencer, or user-defined programmable logic. The opamps (OA0 and OA1) are configurable via these switches to perform all standard opamp functions with appropriate feedback components. The opamps (OA0 and OA1) are programmable and reconfigurable to provide standard opamp functionality via switchable feedback components, unity gain functionality for driving pins directly, or for internal use (such as buffering SAR ADC inputs as indicated in the diagram), or as true comparators. The opamp inputs provide highly flexible connectivity and can connect directly to dedicated pins or, via the analog mux buses, Document Number: 001-91686 Rev. *I Other Digital Signals in Chip P5 DSI IRQ IF CLK IF Port IF IF Port Port IF DSI UDB UDB UDB UDB High -Speed I/O Matrix P3 P4 4 to 8 Scalable array of UDBs (max=16) Routing Channels DSI DSI Programmable Digital Subsystem Page 7 of 45 PSoC(R) 4: PSoC 4200L Datasheet UDBs can be clocked from a clock divider block, from a port interface (required for peripherals such as SPI), and from the DSI network directly or after synchronization. as SPI to operate at higher clock speeds by eliminating the delay for the port input to be routed over DSI and used to register other inputs. The port interface is shown in Figure 7. A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside the UDB array. This allows faster operation because the inputs and outputs can be registered at the port interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os from the same port. This allows interfaces such The UDBs can generate interrupts (one UDB at a time) to the interrupt controller. The UDBs retain the ability to connect to any pin on the chip through the DSI. Figure 7. Port Interface High Speed I/O Matrix To Clock Tree 8 Input Registers 7 Digital GlobalClocks 3 DSI Signals , 1 I/O Signal 6 Clock Selector Block from UDB 0 ... 2 Fixed Function Digital Timer/Counter/PWM (TCPWM) Block The TCPWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals, which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. The PSoC 4200L has eight TCPWM blocks. Serial Communication Blocks (SCB) The PSoC 4200L has four SCBs, which can each implement an I2C, UART, or SPI interface. I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EzI2C that creates a mailbox address range in the memory of the PSoC 4200L and effectively reduces I2C communication to reading from and writing to an array in memory. In 0 3 2 1 0 [1] 4 8 [1] [0] To DSI Document Number: 001-91686 Rev. *I 6 Enables [1] 8 Reset Selector Block from UDB 7 [0] 2 4 Output Registers ... 9 4 8 8 From DSI [1] From DSI addition, the block supports an 8-deep FIFO for receive and transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock stretching caused by the CPU not having read data on time. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO. USB Device A Full-speed USB 2.0 device interface is provided. It has a Control endpoint and eight other endpoints. The interface has a USB transceiver and can be operated from the IMO obviating the need for a crystal oscillator. Page 8 of 45 PSoC(R) 4: PSoC 4200L Datasheet CAN Blocks Special Function Peripherals There are two independent CAN 2.0B blocks, which are certified CAN conformant. LCD Segment Drive GPIO The PSoC 4200L has 96 GPIOs. The GPIO block implements the following: Eight drive strength modes including strong push-pull, resistive pull-up and pull-down, weak (resistive) pull-up and pull-down, open drain and open source, input only, and disabled Input threshold select (CMOS or LVTTL) Individual control of input and output disables Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes) Selectable slew rates for dV/dt related noise control to improve EMI The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multiplexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this and any pin may be routed to any UDB through the DSI network. Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (13 for PSoC 4200L). There are 14 GPIO pins that are overvoltage tolerant (VIN can exceed VDD). The overvoltage cells will not sink more than 10 A when their inputs exceed VDDIO in compliance with I2C specifications. Meeting the I2C minimum fall time requirement for FM and FM+ may require the slower slew rate setting depending on bus loading (also applies to all GPIO and SIO pins). The PSoC 4200L has an LCD controller, which can drive up to eight commons and up to 56 segments. Any pin can be either a common or a segment pin. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). CapSense CapSense is supported on all pins in the PSoC 4200L through two CapSense Sigma-Delta (CSD) blocks that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch. CapSense function can thus be provided on any pin or group of pins in a system under software control. A component is provided for the CapSense block to make it easy for the user. Shield voltage can be driven on another Mux Bus to provide water tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Each CapSense block has two IDACs which can be used for general purposes if CapSense is not being used.(both IDACs are available in that case) or if CapSense is used without water tolerance (one IDAC is available). The two CapSense blocks can be used independently. SIO The Special I/O (SIO) pins have the following features in addition to the GPIO features: Overvoltage protection and hot swap capability Programmable switching thresholds Programmable output pull-up voltage capability They allow interfacing to buses, such as I2C with full I2C compatibility and interfacing to devices operating at different voltage levels. There are two SIO pins on the PSoC4200L. Document Number: 001-91686 Rev. *I Page 9 of 45 PSoC(R) 4: PSoC 4200L Datasheet Pinouts The following is the pin list for the PSoC 4200L. 124-BGA 68-QFN 64-TQFP 48-TQFP 48-TQFP-USB Pin Name Pin Name Pin Name Pin Name Pin Name H13 P0.0 42 P0.0 39 P0.0 28 P0.0 28 P0.0 H12 P0.1 43 P0.1 40 P0.1 29 P0.1 29 P0.1 G13 P0.2 44 P0.2 41 P0.2 30 P0.2 30 P0.2 G12 P0.3 45 P0.3 42 P0.3 31 P0.3 31 P0.3 K10 VSSD G11 P0.4 46 P0.4 43 P0.4 32 P0.4 32 P0.4 F13 P0.5 47 P0.5 44 P0.5 33 P0.5 33 P0.5 F12 P0.6 48 P0.6 45 P0.6 34 P0.6 34 P0.6 F11 P0.7 49 P0.7 46 P0.7 35 P0.7 35 P0.7 E13 P8.0 E12 P8.1 E11 P8.2 D13 P8.3 D12 P8.4 C13 P8.5 C12 P8.6 B12 P8.7 C11 XRES 50 XRES 47 XRES 36 XRES 36 XRES A12 VCCD 51 VCCD 48 VCCD 37 VCCD 37 VCCD D10 VSSD 52 VSSD 49 VSSD 38 VSSD 38 VSSD B13 VDDD 53 VDDD 50 VDDD 39 VDDD 39 VDDD A13 VDDD 53 VDDD 50 VDDD 39 VDDD 39 VDDD A11 P9.0 B11 P9.1 A10 P9.2 B10 P9.3 C10 P9.4 A9 P9.5 B9 P9.6 C9 P9.7 40 VDDA 40 VDDA C8 P5.0 54 P5.0 51 P5.0 B8 P5.1 55 P5.1 52 P5.1 A8 P5.2 56 P5.2 53 P5.2 A7 P5.3 57 P5.3 54 P5.3 B7 P5.4 58 P5.4 C7 P5.5 59 P5.5 55 P5.5 A6 P5.6 B6 P5.7 A2 VDDA 60 VDDA 56 VDDA 40 VDDA 40 VDDA B2 VDDA 60 VDDA 56 VDDA 40 VDDA 40 VDDA Document Number: 001-91686 Rev. *I Page 10 of 45 PSoC(R) 4: PSoC 4200L Datasheet 124-BGA 68-QFN 64-TQFP 48-TQFP 48-TQFP-USB Pin Name Pin Name Pin Name Pin Name Pin Name C3 VSSA 61 VSSA 57 VSSA 41 VSSA 41 VSSA C5 P1.0 62 P1.0 58 P1.0 42 P1.0 42 P1.0 B5 P1.1 63 P1.1 59 P1.1 43 P1.1 43 P1.1 A5 P1.2 64 P1.2 60 P1.2 44 P1.2 44 P1.2 A4 P1.3 65 P1.3 61 P1.3 45 P1.3 45 P1.3 B4 P1.4 66 P1.4 62 P1.4 46 P1.4 46 P1.4 C4 P1.5 67 P1.5 63 P1.5 47 P1.5 47 P1.5 A3 P1.6 68 P1.6 64 P1.6 48 P1.6 48 P1.6 B3 P1.7 1 P1.7/VREF 1 P1.7/VREF 1 P1.7/VREF 1 P1.7/VREF B1 VREF 1 P1.7/VREF 1 P1.7/VREF 1 P1.7/VREF 1 P1.7/VREF C3 VSSA D4 VSSA B2 VDDA C1 P2.0 2 P2.0 2 P2.0 2 P2.0 2 P2.0 C2 P2.1 3 P2.1 3 P2.1 3 P2.1 3 P2.1 D1 P2.2 4 P2.2 4 P2.2 4 P2.2 4 P2.2 D2 P2.3 5 P2.3 5 P2.3 5 P2.3 5 P2.3 D3 P2.4 6 P2.4 6 P2.4 6 P2.4 6 P2.4 E1 P2.5 7 P2.5 7 P2.5 7 P2.5 7 P2.5 E2 P2.6 8 P2.6 8 P2.6 8 P2.6 8 P2.6 E3 P2.7 9 P2.7 9 P2.7 9 P2.7 9 P2.7 K4 VSSD 10 VSSA 10 VSSA 10 VSSD 10 VSSD A1 VDDA 11 VDDA 11 VDDA F1 P10.0 F2 P10.1 F3 P10.2 G1 P10.3 G2 P10.4 G3 P10.5 H1 P10.6 H2 P10.7 K4 VSSD J1 P6.0 12 P6.0 12 P6.0 J2 P6.1 13 P6.1 13 P6.1 J3 P6.2 14 P6.2 14 P6.2 K1 P6.3 15 P6.3 K2 P6.4 16 P6.4/P12.0 15 P6.4/P12.0 L1 P12.0 16 P6.4/P12.0 15 P6.4/P12.0 L2 P12.1 17 P6.5/P12.1 16 P6.5/P12.1 K3 P6.5 17 P6.5/P12.1 16 P6.5/P12.1 L3 VSSD 18 VSSIO 17 VSSIO 10 VSSD 10 VSSD N2 P3.0 19 P3.0 18 P3.0 12 P3.0 12 P3.0 M2 P3.1 20 P3.1 19 P3.1 13 P3.1 13 P3.1 N3 P3.2 21 P3.2 20 P3.2 14 P3.2 14 P3.2 Document Number: 001-91686 Rev. *I Page 11 of 45 PSoC(R) 4: PSoC 4200L Datasheet 124-BGA 68-QFN 64-TQFP 48-TQFP 48-TQFP-USB Pin Name Pin Name Pin Name Pin Name Pin Name M3 P3.3 22 P3.3 21 P3.3 16 P3.3 16 P3.3 N4 P3.4 23 P3.4 22 P3.4 17 P3.4 17 P3.4 M4 P3.5 24 P3.5 23 P3.5 18 P3.5 18 P3.5 N5 P3.6 25 P3.6 24 P3.6 19 P3.6 19 P3.6 M5 P3.7 26 P3.7 25 P3.7 20 P3.7 20 P3.7 M1 VDDIO 27 VDDIO 26 VDDIO 21 VDDIO 21 VDDIO N1 VDDIO 27 VDDIO 26 VDDIO 21 VDDIO 21 VDDIO N6 P11.0 M6 P11.1 L6 P11.2 N7 P11.3 M7 P11.4 L7 P11.5 N8 P11.6 M8 P11.7 N12 VDDIO 27 VDDIO 26 VDDIO 21 VDDIO 21 VDDIO N13 VDDIO 27 VDDIO 26 VDDIO 21 VDDIO 21 VDDIO L8 P4.0 28 P4.0 27 P4.0 22 P4.0 22 P4.0 N9 P4.1 29 P4.1 28 P4.1 23 P4.1 M9 P4.2 30 P4.2 29 P4.2 24 P4.2 N10 P4.3 31 P4.3 30 P4.3 25 P4.3 M10 P4.4 32 P4.4 31 P4.4 N11 P4.5 33 P4.5 32 P4.5 M11 P4.6 34 P4.6 33 P4.6 M12 P4.7 35 P4.7 L11 VSSD L12 D+/P13.0 36 D+/P13.0 34 D+/P13.0 23 D+/P13.0 L13 D-/P13.1 37 D-/P13.1 35 D-/P13.1 24 D-/P13.1 M13 VBUS/P13.2 38 VBUS/P13.2 36 VBUS/P13.2 25 VBUS/P13.2 L9 P7.0 39 P7.0 37 P7.0 26 P7.0 26 P7.0 38 P7.1 27 P7.1 27 P7.1 L10 P7.1 40 P7.1 K13 P7.2 41 P7.2 K12 P7.3 K11 P7.4 J13 P7.5 J12 P7.6 J11 P7.7 Port 12 (Port pins 12.0 and 12.1) are SIO pins. Ports 6 (Port pins P6.0..6.5) and 9 (Port pins 9.0..9.7) are overvoltage tolerant (GPIO_OVT) Balls C6, D11, H11, H3, L4, and L5 are No Connects (NC) on the 124-BGA package. Pins 11 and 15 are NC on the 48-TQFP packages. Document Number: 001-91686 Rev. *I Page 12 of 45 PSoC(R) 4: PSoC 4200L Datasheet Each of the pins shown in the previous table can have multiple programmable functions as shown in the following table. Port/Pin Analog P0.0 P0.1 P0.2 lpcomp.in_p[1] P0.3 lpcomp.in_n[1] PRGIO & USB Alt. Function 1 Alt. Function 2 Alt. Function 3 Alt. Function 4 Alt. Function 5 lpcomp.in_p[0] can[1].can_rx:0 usb.vbus_valid scb[0].spi_select1:3 lpcomp.in_n[0] can[1].can_tx:0 scb[0].spi_select2:3 scb[0].spi_select3:3 P0.4 wco_in scb[1].uart_rx:0 scb[1].i2c_scl:0 scb[1].spi_mosi:0 P0.5 wco_out scb[1].uart_tx:0 scb[1].i2c_sda:0 scb[1].spi_miso:0 srss.wakeup scb[1].spi_select0:0 srss.ext_clk:0 P0.6 scb[1].uart_cts:0 P0.7 scb[1].uart_rts:0 scb[1].spi_clk:0 can[1].can_tx_enb_ n:0 P8.0 scb[3].uart_rx:0 scb[3].i2c_scl:0 scb[3].spi_mosi:0 P8.1 scb[3].uart_tx:0 scb[3].i2c_sda:0 scb[3].spi_miso:0 P8.2 scb[3].uart_cts:0 lpcomp.comp[0]:0 scb[3].spi_clk:0 P8.3 scb[3].uart_rts:0 lpcomp.comp[1]:0 scb[3].spi_select0:0 P8.4 scb[3].spi_select1:0 P8.5 scb[3].spi_select2:0 P8.6 scb[3].spi_select3:0 P8.7 P9.0 tcpwm.line[0]:2 scb[0].uart_rx:0 scb[0].i2c_scl:0 scb[0].spi_mosi:0 P9.1 tcpwm.line_compl[0]:2 scb[0].uart_tx:0 scb[0].i2c_sda:0 scb[0].spi_miso:0 P9.2 tcpwm.line[1]:2 scb[0].uart_cts:0 scb[0].spi_clk:0 P9.3 tcpwm.line_compl[1]:2 scb[0].uart_rts:0 scb[0].spi_select0:0 P9.4 tcpwm.line[2]:2 P9.5 tcpwm.line_compl[2]:2 P9.6 tcpwm.line[3]:2 scb[3].i2c_scl:3 P9.7 tcpwm.line_compl[3]:2 scb[3].i2c_sda:3 scb[0].spi_select1:0 scb[0].spi_select2:0 scb[0].spi_select3:0 P5.0 ctb1_pads[0] csd[1].c_mod tcpwm.line[4]:2 scb[2].uart_rx:0 scb[2].i2c_scl:0 scb[2].spi_mosi:0 P5.1 ctb1_pads[1] csd[1].c_sh_tank tcpwm.line_compl[4]:2 scb[2].uart_tx:0 scb[2].i2c_sda:0 scb[2].spi_miso:0 P5.2 ctb1_pads[2] ctb1_oa0_out_10x tcpwm.line[5]:2 scb[2].uart_cts:0 lpcomp.comp[0]:1 scb[2].spi_clk:0 P5.3 ctb1_pads[3] ctb1_oa1_out_10x tcpwm.line_compl[5]:2 scb[2].uart_rts:0 lpcomp.comp[1]:1 scb[2].spi_select0:0 P5.4 ctb1_pads[4] tcpwm.line[6]:2 scb[2].spi_select1:0 P5.5 ctb1_pads[5] tcpwm.line_compl[6]:2 scb[2].spi_select2:0 P5.6 ctb1_pads[6] tcpwm.line[7]:2 scb[2].spi_select3:0 P5.7 ctb1_pads[7] tcpwm.line_compl[7]:2 P1.0 ctb0_pads[0] tcpwm.line[2]:1 scb[0].uart_rx:1 scb[0].i2c_scl:1 scb[0].spi_mosi:1 P1.1 ctb0_pads[1] tcpwm.line_compl[2]:1 scb[0].uart_tx:1 scb[0].i2c_sda:1 scb[0].spi_miso:1 P1.2 ctb0_pads[2] ctb0_oa0_out_10x tcpwm.line[3]:1 scb[0].uart_cts:1 scb[0].spi_clk:1 P1.3 ctb0_pads[3] ctb0_oa1_out_10x tcpwm.line_compl[3]:1 scb[0].uart_rts:1 scb[0].spi_select0:1 P1.4 ctb0_pads[4] tcpwm.line[6]:1 Document Number: 001-91686 Rev. *I scb[0].spi_select1:1 Page 13 of 45 PSoC(R) 4: PSoC 4200L Datasheet Port/Pin Analog P1.5 ctb0_pads[5] PRGIO & USB Alt. Function 1 Alt. Function 2 Alt. Function 3 Alt. Function 4 Alt. Function 5 tcpwm.line_compl[6]:1 scb[0].spi_select2:1 scb[0].spi_select3:1 P1.6 ctb0_pads[6] tcpwm.line[7]:1 P1.7 ctb0_pads[7], sar_ext_vref tcpwm.line_compl[7]:1 P2.0 sarmux_pads[0] tcpwm.line[4]:1 scb[1].uart_rx:1 scb[1].i2c_scl:1 scb[1].spi_mosi:1 P2.1 sarmux_pads[1] tcpwm.line_compl[4]:1 scb[1].uart_tx:1 scb[1].i2c_sda:1 scb[1].spi_miso:1 P2.2 sarmux_pads[2] tcpwm.line[5]:1 scb[1].uart_cts:1 scb[1].spi_clk:1 P2.3 sarmux_pads[3] tcpwm.line_compl[5]:1 scb[1].uart_rts:1 scb[1].spi_select0:1 P2.4 sarmux_pads[4] tcpwm.line[0]:1 scb[1].spi_select1:0 P2.5 sarmux_pads[5] tcpwm.line_compl[0]:1 scb[1].spi_select2:0 P2.6 sarmux_pads[6] tcpwm.line[1]:1 scb[1].spi_select3:0 P2.7 sarmux_pads[7] tcpwm.line_compl[1]:1 P10.0 scb[2].uart_rx:1 scb[2].i2c_scl:1 scb[2].spi_mosi:1 P10.1 scb[2].uart_tx:1 scb[2].i2c_sda:1 scb[2].spi_miso:1 P10.2 scb[2].uart_cts:1 scb[2].spi_clk:1 P10.3 scb[2].uart_rts:1 scb[2].spi_select0:1 P10.4 scb[2].spi_select1:1 P10.5 scb[2].spi_select2:1 P10.6 scb[2].spi_select3:1 P10.7 P6.0 tcpwm.line[4]:0 scb[3].uart_rx:1 can[0].can_tx_enb_ n:0 scb[3].i2c_scl:1 scb[3].spi_mosi:1 P6.1 P6.2 tcpwm.line_compl[4]:0 scb[3].uart_tx:1 can[0].can_rx:0 scb[3].i2c_sda:1 scb[3].spi_miso:1 tcpwm.line[5]:0 scb[3].uart_cts:1 can[0].can_tx:0 scb[2].i2c_scl:3 scb[3].spi_clk:1 P6.3 tcpwm.line_compl[5]:0 scb[3].uart_rts:1 scb[2].i2c_sda:3 scb[3].spi_select0:1 P6.4 tcpwm.line[6]:0 scb[0].i2c_scl:3 scb[3].spi_select1:1 P12.0 tcpwm.line[7]:0 scb[1].i2c_scl:3 scb[3].spi_select3:1 P12.1 tcpwm.line_compl[7]:0 scb[1].i2c_sda:3 P6.5 tcpwm.line_compl[6]:0 scb[0].i2c_sda:3 scb[3].spi_select2:1 P3.0 tcpwm.line[0]:0 scb[1].uart_rx:2 scb[1].i2c_scl:2 scb[1].spi_mosi:2 P3.1 tcpwm.line_compl[0]:0 scb[1].uart_tx:2 scb[1].i2c_sda:2 scb[1].spi_miso:2 P3.2 tcpwm.line[1]:0 scb[1].uart_cts:2 cpuss.swd_data:0 scb[1].spi_clk:2 P3.3 tcpwm.line_compl[1]:0 scb[1].uart_rts:2 cpuss.swd_clk:0 scb[1].spi_select0:2 P3.4 tcpwm.line[2]:0 scb[1].spi_select1:1 P3.5 tcpwm.line_compl[2]:0 scb[1].spi_select2:1 P3.6 tcpwm.line[3]:0 scb[1].spi_select3:1 P3.7 tcpwm.line_compl[3]:0 P11.0 prgio[0].io[0] tcpwm.line[4]:3 scb[2].uart_rx:2 scb[2].i2c_scl:2 scb[2].spi_mosi:2 P11.1 prgio[0].io[1] tcpwm.line_compl[4]:3 P11.2 prgio[0].io[2] tcpwm.line[5]:3 scb[2].uart_tx:2 scb[2].i2c_sda:2 scb[2].spi_miso:2 scb[2].uart_cts:2 cpuss.swd_data:1 P11.3 prgio[0].io[3] tcpwm.line_compl[5]:3 scb[2].uart_rts:2 scb[2].spi_clk:2 cpuss.swd_clk:1 scb[2].spi_select0:2 P11.4 prgio[0].io[4] tcpwm.line[6]:3 scb[2].spi_select1:2 P11.5 prgio[0].io[5] tcpwm.line_compl[6]:3 scb[2].spi_select2:2 P11.6 prgio[0].io[6] tcpwm.line[7]:3 scb[2].spi_select3:2 P11.7 prgio[0].io[7] tcpwm.line_compl[7]:3 P4.0 scb[0].uart_rx:2 can[0].can_rx:1 scb[0].i2c_scl:2 scb[0].spi_mosi:2 P4.1 scb[0].uart_tx:2 can[0].can_tx:1 scb[0].i2c_sda:2 scb[0].spi_miso:2 Document Number: 001-91686 Rev. *I Page 14 of 45 PSoC(R) 4: PSoC 4200L Datasheet Port/Pin Analog Alt. Function 2 Alt. Function 3 Alt. Function 4 Alt. Function 5 P4.2 csd[0].c_mod PRGIO & USB Alt. Function 1 scb[0].uart_cts:2 can[0].can_tx_enb_ n:1 lpcomp.comp[0]:2 scb[0].spi_clk:2 P4.3 csd[0].c_sh_tank scb[0].uart_rts:2 lpcomp.comp[1]:2 scb[0].spi_select0:2 P4.4 can[1].can_tx_enb_ n:1 scb[0].spi_select1:2 P4.5 can[1].can_rx:1 scb[0].spi_select2:2 P4.6 can[1].can_tx:1 scb[0].spi_select3:2 P4.7 P13.0 USBDP P13.1 USBDM P13.2 VBUS P7.0 srss.eco_in tcpwm.line[0]:3 scb[3].uart_rx:2 scb[3].i2c_scl:2 scb[3].spi_mosi:2 P7.1 srss.eco_out tcpwm.line_compl[0]:3 scb[3].uart_tx:2 scb[3].i2c_sda:2 scb[3].spi_miso:2 P7.2 tcpwm.line[1]:3 scb[3].uart_cts:2 scb[3].spi_clk:2 P7.3 tcpwm.line_compl[1]:3 scb[3].uart_rts:2 scb[3].spi_select0:2 P7.4 tcpwm.line[2]:3 scb[3].spi_select1:2 P7.5 tcpwm.line_compl[2]:3 scb[3].spi_select2:2 P7.6 tcpwm.line[3]:3 scb[3].spi_select3:2 P7.7 tcpwm.line_compl[3]:3 Descriptions of the power pin functions are as follows: VDDD: Power supply for both analog and digital sections (where there is no VDDA pin) VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise VDDIO: I/O pin power domain VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise VSS: Ground pin VCCD: Regulated digital supply (1.8 V 5%) GPIO and GPIO_OVT pins can be used as CSD sense and shield pins (a total of 94). Up to 64 of the pins can be used for LCD drive. The following packages are supported: 124-ball BGA, 64-pin TQFP, 68-pin QFN, and 48-pin TQFP. Power The supply voltage range is 1.71 V to 5.5 V with all functions and circuits operating over that range. The PSoC 4200L family allows two distinct modes of power supply operation: Unregulated External Supply and Regulated External Supply modes. Unregulated External Supply In this mode, the PSoC 4200L is powered by an External Power Supply that can be anywhere in the range of 1.8 V to 5.5 V. This range is also designed for battery-powered operation, for instance, the chip can be powered from a battery system that Document Number: 001-91686 Rev. *I starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the PSoC 4200L supplies the internal logic and the VCCD output of the PSoC 4200L must be bypassed to ground via an external Capacitor (in the range of 1 to 1.6 F; X5R ceramic or better). VDDA and VDDD must be shorted together on the PC board; the grounds, VSSA and VSS must also be shorted together. Bypass capacitors must be used from VDDD and VDDA to ground, typical practice for systems in this frequency range is to use a capacitor in the 1 F range in parallel with a smaller capacitor (0.1 F, for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. Power Supply VDDD-VSS and VDDIO-VSS VDDA-VSSA VCCD-VSS VREF-VSSA (optional) Bypass Capacitors 0.1 F ceramic at each pin plus bulk capacitor 1 to 10 F. 0.1 F ceramic at pin. Additional 1 F to 10 F bulk capacitor 1 F ceramic capacitor at the VCCD pin The internal bandgap may be bypassed with a 1 F to 10 F capacitor for better ADC performance. Regulated External Supply In this mode, the PSoC 4200L is powered by an external power supply that must be within the range of 1.71 V to 1.89 V (1.8 5%); note that this range needs to include power supply ripple. In this mode, the VCCD and VDDD pins are shorted together and bypassed. The internal regulator is disabled in firmware. Page 15 of 45 PSoC(R) 4: PSoC 4200L Datasheet Electrical Specifications Absolute Maximum Ratings Table 1. Absolute Maximum Ratings[1] Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID1 VDD_ABS Analog or digital supply relative to VSS (VSSD = VSSA) -0.5 - 6 V Absolute maximum SID2 VCCD_ABS Direct digital core voltage input relative to VSSD -0.5 - 1.95 V Absolute maximum SID3 VGPIO_ABS GPIO voltage; VDDD or VDDA -0.5 - VDD + 0.5 V Absolute maximum SID4 IGPIO_ABS Current per GPIO -25 - 25 mA Absolute maximum SID5 IG-PIO_injection GPIO injection current per pin -0.5 - 0.5 mA Absolute maximum BID44 ESD_HBM Electrostatic discharge human body model 2200 - - V BID45 ESD_CDM Electrostatic discharge charged device model 500 - - V BID46 LU Pin current for latch-up -140 - 140 mA Device Level Specifications All specifications are valid for -40 C TA 85 C and TJ 100 C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 2. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID53 VDDD Power Supply Input Voltage (VDDA = VDDD = VDD) 1.8 - 5.5 V With regulator enabled SID255 VDDD Power supply input voltage unregulated 1.71 1.8 1.89 V Internally unregulated Supply SID54 VCCD Output voltage (for core logic) - 1.8 - V SID55 CEFC External regulator voltage bypass 1 1.3 1.6 F X5R ceramic or better SID56 CEXC Power supply decoupling capacitor - 1 - F X5R ceramic or better Active Mode SID6 IDD1 Execute from flash; CPU at 6 MHz - 2.2 3.1 mA SID7 IDD2 Execute from flash; CPU at 12 MHz - 3.7 4.8 mA SID8 IDD3 Execute from flash; CPU at 24 MHz - 6.7 8.0 mA SID9 IDD4 Execute from flash; CPU at 48 MHz - 12.8 14.5 mA SID21 IDD16 I2C wakeup, WDT, and Comparators on. Regulator Off. - 1.8 2.2 mA VDD = 1.71 to 1.89, 6 MHz SID22 IDD17 I2C wakeup, WDT, and Comparators on. - 1.7 2.1 mA VDD = 1.8 to 5.5, 6 MHz Sleep Mode Note 1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Document Number: 001-91686 Rev. *I Page 16 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 2. DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID23 IDD18 I2C wakeup, WDT, and Comparators on. Regulator Off. - 2.4 2.9 mA VDD = 1.71 to 1.89, 12 MHz SID24 IDD19 I2C wakeup, WDT, and Comparators on. - 2.3 2.8 mA VDD = 1.8 to 5.5, 12 MHz Deep Sleep Mode, -40 C to + 60 C SID30 IDD25 I2C wakeup and WDT on. Regulator Off. - - 13.5 A VDD = 1.71 to 1.89 SID31 IDD26 I2C wakeup and WDT on. - 1.3 20.0 A VDD = 1.8 to 3.6 I C wakeup and WDT on. - - 20.0 A VDD = 3.6 to 5.5 IDD28 I2C wakeup and WDT on. Regulator Off. - - 45.0 A VDD = 1.71 to 1.89 SID34 IDD29 I2C wakeup and WDT on. - 15 60.0 A VDD = 1.8 to 3.6 SID35 IDD30 I2C wakeup and WDT on. - - 45.0 A VDD = 3.6 to 5.5 SID32 IDD27 2 Deep Sleep Mode, +85 C SID33 Hibernate Mode, -40 C to + 60 C SID39 IDD34 - - 1123 nA VDD = 1.71 to 1.89 SID40 IDD35 Regulator Off. - 150 1600 nA VDD = 1.8 to 3.6 SID41 IDD36 - - 1600 nA VDD = 3.6 to 5.5 - - 4142 nA VDD = 1.71 to 1.89 Hibernate Mode, +85 C SID42 IDD37 Regulator Off. SID43 IDD38 - - 9700 nA VDD = 1.8 to 3.6 SID44 IDD39 - - 10,400 nA VDD = 3.6 to 5.5 Stop Mode SID304 IDD43A Stop Mode current; VDD = 3.6 V - 20 659 nA T = -40 C to +60 C SID304A IDD43B Stop Mode current; VDD = 3.6 V - - 1810 nA T = +85 C Supply current while XRES (Active Low) asserted - 2 5 mA Description Min Typ Max Units Details/ Conditions DC - 48 MHz 1.71 VDD 5.5 XRES current SID307 IDD_XR Table 3. AC Specifications Spec ID# Parameter SID48 FCPU CPU frequency SID49 TSLEEP Wakeup from sleep mode - 0 - s Guaranteed by characterization SID50 TDEEPSLEEP Wakeup from Deep Sleep mode - - 25 s 24-MHz IMO. Guaranteed by characterization SID51 THIBERNATE Wakeup from Hibernate mode - - 0.7 ms Guaranteed by characterization SID51A TSTOP Wakeup from Stop mode - - 1.9 ms Guaranteed by characterization SID52 TRESETWIDTH External reset pulse width 1 - - s Guaranteed by characterization Document Number: 001-91686 Rev. *I Page 17 of 45 PSoC(R) 4: PSoC 4200L Datasheet GPIO Table 4. GPIO DC Specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID57 VIH[2] Input voltage high threshold 0.7 x VDDD - - V CMOS Input SID57A IIHS Input current when Pad > VDDIO for OVT inputs - - 10 A Per I2C Spec SID58 VIL Input voltage low threshold - - 0.3 x VDDD V CMOS Input SID241 VIH[2] LVTTL input, VDDD < 2.7 V 0.7 x VDDD - - V SID242 VIL LVTTL input, VDDD < 2.7 V - - 0.3 x VDDD V SID243 VIH[2] LVTTL input, VDDD 2.7 V 2.0 - - V SID244 VIL LVTTL input, VDDD 2.7 V - - 0.8 V SID59 VOH Output voltage high level VDDD - 0.6 - - V IOH = 4 mA at 3 V VDDD SID60 VOH Output voltage high level VDDD - 0.5 - - V IOH = 1 mA at 1.8 V VDDD SID61 VOL Output voltage low level - - 0.6 V IOL = 4 mA at 1.8 V VDDD SID62 VOL Output voltage low level - - 0.6 V IOL = 8 mA at 3 V VDDD SID62A VOL Output voltage low level - - 0.4 V IOL = 3 mA at 3 V VDDD SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 k SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k SID65 IIL Input leakage current (absolute value) - - 2 nA SID65A IIL_CTBM Input leakage current (absolute value) for CTBM pins - - 4 nA SID66 CIN Input capacitance - - 7 pF Not applicable for P6.4, P6.5, P12.0, P12.1, and for USB pins. SID67 VHYSTTL Input hysteresis LVTTL 25 40 - mV VDDD 2.7 V SID68 VHYSCMOS Input hysteresis CMOS 0.05 x VDDD - - mV SID69 IDIODE Current through protection diode to VDD/Vss - - 100 A Guaranteed by characterization SID69A ITOT_GPIO Maximum Total Source or Sink Chip Current - - 200 mA Guaranteed by characterization 25 C, VDDD = 3.0 V Note 2. VIH must not exceed VDDD + 0.2 V. Document Number: 001-91686 Rev. *I Page 18 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 5. GPIO AC Specifications (Guaranteed by Characterization)[3] Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID70 TRISEF Rise time in fast strong mode 2 - 12 ns 3.3 V VDDD, Cload = 25 pF SID71 TFALLF Fall time in fast strong mode 2 - 12 ns 3.3 V VDDD, Cload = 25 pF SID72 TRISES Rise time in slow strong mode 10 - 60 ns 3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 - 60 ns 3.3 V VDDD, Cload = 25 pF SID74 FGPIOUT1 GPIO Fout;3.3 V VDDD 5.5 V. Fast strong mode. - - 33 MHz 90/10%, 25 pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO Fout;1.7 VVDDD3.3 V. Fast strong mode. - - 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO Fout;3.3 V VDDD 5.5 V. Slow strong mode. - - 7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO Fout;1.7 V VDDD 3.3 V. Slow strong mode. - - 3.5 MHz 90/10%, 25 pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency; 1.71 V VDDD 5.5 V - - 48 MHz 90/10% VIO Min Typ Max Units XRES Table 6. XRES DC Specifications Spec ID# Parameter Description Details/ Conditions SID77 VIH Input voltage high threshold 0.7 x VDDD - - V CMOS Input SID78 VIL Input voltage low threshold - - 0.3 x VDDD V CMOS Input SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 k SID80 CIN Input capacitance - 3 - pF SID81 VHYSXRES Input voltage hysteresis - 100 - mV Guaranteed by characterization SID82 IDIODE Current through protection diode to VDDD/VSS - - 100 A Guaranteed by characterization Min 1 Typ - Max - Units s Table 7. XRES AC Specifications Spec ID# SID83 Parameter TRESETWIDTH Description Reset pulse width Details/ Conditions Guaranteed by characterization Note 3. Simultaneous switching transitions on many fully-loaded GPIO pins may cause ground perturbations depending on several factors including PCB and decoupling capacitor design. For applications that are very sensitive to ground perturbations, the slower GPIO slew rate setting may be used. Document Number: 001-91686 Rev. *I Page 19 of 45 PSoC(R) 4: PSoC 4200L Datasheet Analog Peripherals Opamp Table 8. Opamp Specifications (Guaranteed by Characterization) Spec ID# Min Typ Max Units IDD Parameter Opamp block current. No load. Description - - - - SID269 IDD_HI Power = high - 1100 1850 A SID270 IDD_MED Power = medium - 550 950 A SID271 IDD_LOW Power = low - 150 350 A GBW Load = 20 pF, 0.1 mA. VDDA = 2.7 V - - - - SID272 GBW_HI Power = high 6 - - MHz SID273 GBW_MED Power = medium 4 - - MHz SID274 GBW_LO Power = low - 1 - MHz IOUT_MAX VDDA 2.7 V, 500 mV from rail - - - - SID275 IOUT_MAX_HI Power = high 10 - - mA SID276 IOUT_MAX_MID Power = medium 10 - - mA SID277 IOUT_MAX_LO Power = low - 5 - mA IOUT VDDA = 1.71 V, 500 mV from rail - - - - Details/Conditions SID278 IOUT_MAX_HI Power = high 4 - - mA SID279 IOUT_MAX_MID Power = medium 4 - - mA SID280 IOUT_MAX_LO Power = low - 2 - mA SID281 VIN Input voltage range -0.05 - VDDA - 0.2 V Charge-pump on, VDDA 2.7 V SID282 VCM Input common mode voltage -0.05 - VDDA - 0.2 V Charge-pump on, VDDA 2.7 V VOUT VDDA 2.7 V - - - SID283 VOUT_1 Power = high, Iload=10 mA 0.5 - VDDA - 0.5 V SID284 VOUT_2 Power = high, Iload=1 mA 0.2 - VDDA - 0.2 V SID285 VOUT_3 Power = medium, Iload=1 mA 0.2 - VDDA - 0.2 V SID286 VOUT_4 Power = low, Iload=0.1mA 0.2 - VDDA - 0.2 V SID288 VOS_TR Offset voltage, trimmed 1 0.5 1 mV High mode SID288A VOS_TR Offset voltage, trimmed - 1 - mV Medium mode SID288B VOS_TR Offset voltage, trimmed - 2 - mV Low mode SID290 VOS_DR_TR Offset voltage drift, trimmed -10 3 10 V/C High mode SID290A VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Medium mode SID290B VOS_DR_TR Offset voltage drift, trimmed - 10 - V/C Low mode SID291 CMRR DC 60 70 - dB VDDD = 3.6 V SID292 PSRR At 1 kHz, 100 mV ripple 70 85 - dB VDDD = 3.6 V - - - - SID293 VN1 Input referred, 1 Hz - 1GHz, power = high - 94 - Vrms SID294 VN2 Input referred, 1 kHz, power = high - 72 - nV/rtHz Noise Document Number: 001-91686 Rev. *I Page 20 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 8. Opamp Specifications (Guaranteed by Characterization) (continued) Description Min Typ Max Units SID295 Spec ID# VN3 Parameter Input referred, 10kHz, power = high - 28 - nV/rtHz SID296 VN4 Input referred, 100kHz, power = high - 15 - nV/rtHz SID297 Cload Stable up to maximum load. Performance specs at 50 pF. - - 125 pF SID298 Slew_rate Cload = 50 pF, Power = High, VDDA 2.7 V 6 - - V/s SID299 T_op_wake From disable to enable, no external RC dominating - 25 - s SID299A OL_GAIN Open Loop Gain - 90 - dB Comp_mode Comparator mode; 50 mV drive, Trise = Tfall (approx.) - - - SID300 TPD1 Response time; power = high - 150 - ns SID301 TPD2 Response time; power = medium - 400 - ns SID302 TPD3 Response time; power = low - 2000 - ns SID303 Vhyst_op Hysteresis - 10 - mV Details/Conditions Deep Sleep mode VDDA 2.7 V. Deep Sleep Mode Mode 2 is lowest current range. Mode 1 has higher GBW. SID_DS_1 IDD_HI_M1 Mode 1, High current - 1400 - A 25 C SID_DS_2 IDD_MED_M1 Mode 1, Medium current - 700 - A 25 C SID_DS_3 IDD_LOW_M1 Mode 1, Low current - 200 - A 25 C SID_DS_4 IDD_HI_M2 Mode 2, High current - 120 - A 25 C SID_DS_5 IDD_MED_M2 Mode 2, Medium current - 60 - A 25 C SID_DS_6 IDD_LOW_M2 Mode 2, Low current - 15 - A 25 C SID_DS_7 GBW_HI_M1 Mode 1, High current - 4 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_8 GBW_MED_M1 Mode 1, Medium current - 2 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_9 GBW_LOW_M1 Mode 1, Low current - 0.5 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V - 0.5 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_11 GBW_MED_M2 Mode 2, Medium current - 0.2 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_12 GBW_LOW_M2 Mode 2, Low current - 0.1 - MHz 20-pF load, no DC load 0.2 V to VDDA - 1.5 V SID_DS_13 VOS_HI_M1 - 5 - mV With trim 25 C, 0.2 V to VDDA - 1.5 V SID_DS_14 VOS_MED_M1 Mode 1, Medium current - 5 - mV With trim 25 C, 0.2 V to VDDA - 1.5 V SID_DS_15 VOS_LOW_M2 Mode 1, Low current - 5 - mV With trim 25 C, 0.2 V to VDDA - 1.5 V SID_DS_16 VOS_HI_M2 - 5 - mV With trim 25 C, 0.2 V to VDDA - 1.5 V - 5 - mV With trim 25 C, 0.2 V to VDDA - 1.5 V SID_DS_10 GBW_HI_M2 Mode 2, High current Mode 1, High current Mode 2, High current SID_DS_17 VOS_MED_M2 Mode 2, Medium current Document Number: 001-91686 Rev. *I Page 21 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 8. Opamp Specifications (Guaranteed by Characterization) (continued) Min Typ Max Units SID_DS_18 VOS_LOW_M2 Mode 2, Low current Spec ID# Parameter Description - 5 - mV With trim 25 C, 0.2 V to VDDA-1.5 V SID_DS_19 IOUT_HI_M! - 10 - mA Output is 0.5 V to VDDA-0.5 V SID_DS_20 IOUT_MED_M1 Mode 1, Medium current - 10 - mA Output is 0.5 V to VDDA-0.5 V SID_DS_21 IOUT_LOW_M1 Mode 1, Low current - 4 - mA Output is 0.5 V to VDDA-0.5 V SID_DS_22 IOUT_HI_M2 Mode 2, High current - 1 - mA Output is 0.5 V to VDDA-0.5 V SID_DS_23 IOU_MED_M2 Mode 2, Medium current - 1 - mA Output is 0.5 V to VDDA-0.5 V SID_DS_24 IOU_LOW_M2 Mode 2, Low current - 0.5 - mA Output is 0.5 V to VDDA-0.5 V Mode 1, High current Details/Conditions Comparator Table 9. Comparator DC Specifications Spec ID# SID85 Parameter Description Input offset voltage. Custom trim. Common mode voltage range from 0 to VDD-1. Input offset voltage. Ultra low-power mode. Min - Typ - Max 4 Units mV Details/Conditions VOFFSET2 SID85A VOFFSET3 - 12 - mV Hysteresis when enabled. Common mode voltage range from 0 to VDD -1. Input common mode voltage in normal mode Input common mode voltage in low power mode Input common mode voltage in ultra low power mode - 10 35 mV 0 - V 0 - VDDD - 0.2 VDDD VDDD 2.2 V for Temp < 0 C, VDDD 1.8 V for Temp > 0 C Guaranteed by characterization Modes 1 and 2. SID86 VHYST SID87 VICM1 SID247 VICM2 SID247A VICM2 0 - VDDD - 1.15 V SID88 CMRR Common mode rejection ratio 50 - - dB SID88A CMRR Common mode rejection ratio 42 - - dB SID89 ICMP1 Block current, normal mode - 280 400 A SID248 ICMP2 Block current, low power mode - 50 100 A SID259 ICMP3 Block current, ultra low power mode - 6 28 A SID90 ZCMP DC input impedance of comparator 35 - - M Document Number: 001-91686 Rev. *I V VDDD 2.2 V for Temp < 0 C, VDDD 1.8 V for Temp > 0 C VDDD 2.7 V. Guaranteed by characterization VDDD 2.7 V. Guaranteed by characterization Guaranteed by characterization Guaranteed by characterization Guaranteed by characterization, VDDD 2.2 V for Temp < 0 C, VDDD 1.8 V for Temp > 0 Guaranteed by characterization Page 22 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 10. Comparator AC Specifications (Guaranteed by Characterization) Min Typ Max Units SID91 Spec ID# TRESP1 Parameter Response time, normal mode Description - 38 110 ns Details/Conditions SID258 TRESP2 Response time, low power mode - 70 200 ns 50-mV overdrive SID92 TRESP3 Response time, ultra low power mode - 2.3 15 s 200-mV overdrive. VDDD 2.2 V for Temp < 0 C, VDDD 1.8 V for Temp > 0 C Min Typ Max Units -5 1 +5 C Min Typ Max Units - - 12 bits 50-mV overdrive Temperature Sensor Table 11. Temperature Sensor Specifications Spec ID# SID93 Parameter TSENSACC Description Temperature sensor accuracy Details/Conditions -40 to +85 C SAR ADC Table 12. SAR ADC DC Specifications Spec ID# Parameter Description Resolution Details/Conditions SID94 A_RES SID95 A_CHNIS_S Number of channels - single ended - - 16 8 full speed SID96 A-CHNKS_D Number of channels - differential - - 8 Diff inputs use neighboring I/O SID97 A-MONO Monotonicity - - - Yes. Based on characterization SID98 A_GAINERR Gain error - - 0.1 % SID99 A_OFFSET Input offset voltage - - 2 mV SID100 A_ISAR Current consumption - - 1 mA SID101 A_VINS Input voltage range - single ended VSS - VDDA V Based on device characterization SID102 A_VIND Input voltage range - differential VSS - VDDA V Based on device characterization SID103 A_INRES Input resistance - - 2.2 k Based on device characterization SID104 A_INCAP Input capacitance - - 10 pF Based on device characterization Min 70 Typ - Max - Units dB With external reference. Measured with 1-V VREF. Table 13. SAR ADC AC Specifications (Guaranteed by Characterization) Spec ID# SID106 Parameter A_PSRR Description Power supply rejection ratio SID107 A_CMRR Common mode rejection ratio 66 - - dB SID108 A_SAMP_1 - - 1 Msps SID108A A_SAMP_2 Sample rate with external reference bypass cap Sample rate with no bypass cap. Reference = VDD - - 500 ksps Document Number: 001-91686 Rev. *I Details/Conditions Measured at 1 V Page 23 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 13. SAR ADC AC Specifications (Guaranteed by Characterization) (continued) Spec ID# SID108B Parameter A_SAMP_3 A_INL Description Sample rate with no bypass cap. Internal reference Signal-to-noise and distortion ratio (SINAD) Integral non linearity Min - Typ - Max 100 Units ksps SID109 A_SNDR SID111 SID111A A_INL SID111B Details/Conditions 65 - - dB -1.7 - +2 LSB Integral non linearity -1.5 - +1.7 LSB A_INL Integral non linearity -1.5 - +1.7 LSB SID112 A_DNL Differential non linearity -1 - +2.2 LSB SID112A A_DNL Differential non linearity -1 - +2 LSB SID112B A_DNL Differential non linearity -1 - +2.2 LSB SID113 A_THD Total harmonic distortion - - -65 dB VDD = 1.71 to 5.5, 1 Msps, VREF = 1 to 5.5. VDDD = 1.71 to 3.6, 1 Msps, VREF = 1.71 to VDDD. VDDD = 1.71 to 5.5, 500 ksps, VREF = 1 to 5.5. VDDD = 1.71 to 5.5, 1 Msps, VREF = 1 to 5.5. VDDD = 1.71 to 3.6, 1 Msps, VREF = 1.71 to VDDD. VDDD = 1.71 to 5.5, 500 ksps, VREF = 1 to 5.5. FIN = 10 kHz. Min Typ Max Units Details/Conditions 1.71 - 5.5 V FIN = 10 kHz CSD Table 14. CSD Block Specification Spec ID# Parameter Description CSD Specification SID308 VCSD Voltage range of operation SID309 IDAC1 DNL for 8-bit resolution -1 - 1 LSB SID310 IDAC1 INL for 8-bit resolution -3 - 3 LSB SID311 IDAC2 DNL for 7-bit resolution -1 - 1 LSB SID312 IDAC2 INL for 7-bit resolution -3 - 3 LSB SID313 SNR Ratio of counts of finger to noise. Guaranteed by characterization 5 - - Ratio SID314 IDAC1_CRT1 Output current of Idac1 (8-bits) in High range - 612 - A SID314A IDAC1_CRT2 Output current of Idac1(8-bits) in Low range - 306 - A SID315 IDAC2_CRT1 Output current of Idac2 (7-bits) in High range - 304.8 - A SID315A IDAC2_CRT2 Output current of Idac2 (7-bits) in Low range - 152.4 - A Document Number: 001-91686 Rev. *I Capacitance range of 9 to 35 pF, 0.1 pF sensitivity Page 24 of 45 PSoC(R) 4: PSoC 4200L Datasheet Digital Peripherals The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timer/Counter/PWM Table 15. TCPWM Specifications (Guaranteed by Characterization) Spec ID# Parameter SID.TCPWM.1 ITCPWM1 SID.TCPWM.2 ITCPWM2 SID.TCPWM.2A ITCPWM3 Description Min Typ Max Block current consumption at 3 MHz - - 45 Block current consumption at 12 MHz Block current consumption at 48 MHz - - 155 - - 650 - - Fc Units Details/Conditions All modes A (Timer/Counter/PWM) All modes A (Timer/Counter/PWM) All modes A (Timer/Counter/PWM) Fc max = Fcpu. MHz Maximum = 48 MHz Trigger Events can be Stop, Start, Reload, Count, Capture, or Kill ns depending on which mode of operation is selected. Minimum possible width of Overflow, Underflow, ns and CC (Counter equals Compare value) trigger outputs Minimum time between ns successive counts Minimum pulse width of ns PWM Output Minimum pulse width ns between Quadrature phase inputs. SID.TCPWM.3 TCPWMFREQ Operating frequency SID.TCPWM.4 Trigger Pulse Width for all TPWMENEXT Input Trigger Events 2/Fc - - SID.TCPWM.5 TPWMEXT Output Trigger Pulse widths 2/Fc - - SID.TCPWM.5A TCRES Resolution of Counter 1/Fc - - SID.TCPWM.5B PWMRES PWM Resolution 1/Fc - - SID.TCPWM.5C QRES Quadrature inputs resolution 1/Fc - - Min Typ Max Units I2C Table 16. Fixed I2C DC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description SID149 II2C1 Block current consumption at 100 kHz - 10.5 55 A SID150 II2C2 Block current consumption at 400 kHz - - 135 A SID151 II2C3 Block current consumption at 1 Mbps - - 310 A SID152 II2C4 I2C enabled in Deep Sleep mode - - 1.4 A Min - Typ - Max 1 Units Mbps Details/Conditions Table 17. Fixed I2C AC Specifications (Guaranteed by Characterization) Spec ID# SID153 Parameter FI2C1 Description Bit rate Document Number: 001-91686 Rev. *I Details/Conditions Page 25 of 45 PSoC(R) 4: PSoC 4200L Datasheet LCD Direct Drive Table 18. LCD Direct Drive DC Specifications (Guaranteed by Characterization) Spec ID# SID154 Parameter ILCDLOW SID155 CLCDCAP SID156 LCDOFFSET SID157 ILCDOP1 SID158 ILCDOP2 Description Operating current in low power mode Min - Typ 5 Max - Units Details/Conditions A 16 x 4 small segment disp. at 50 Hz pF Guaranteed by Design LCD capacitance per segment/common driver Long-term segment offset - 500 5000 - 20 - mV PWM Mode current. 5-V bias. 24-MHz IMO PWM Mode current. 3.3-V bias. 24-MHz IMO. - 0.6 - mA - 0.5 - mA Min 10 Typ 50 Max 150 Units Hz 32 x 4 segments. 50 Hz, 25 C 32 x 4 segments. 50 Hz, 25 C Table 19. LCD Direct Drive AC Specifications (Guaranteed by Characterization) Spec ID# SID159 Parameter FLCD Description LCD frame rate Details/Conditions Table 20. Fixed UART DC Specifications (Guaranteed by Characterization) Min Typ Max Units SID160 Spec ID# IUART1 Parameter Block current consumption at 100 Kbits/sec Description - 9 55 A SID161 IUART2 Block current consumption at 1000 Kbits/sec - - 312 A Min Typ Max Units - - 1 Mbps Details/Conditions Table 21. Fixed UART AC Specifications (Guaranteed by Characterization) Spec ID# SID162 Parameter FUART Description Bit rate Document Number: 001-91686 Rev. *I Details/Conditions Page 26 of 45 PSoC(R) 4: PSoC 4200L Datasheet SPI Specifications Table 22. Fixed SPI DC Specifications (Guaranteed by Characterization) Min Typ Max Units SID163 Spec ID# ISPI1 Parameter Block current consumption at 1 Mbits/sec Description - - 360 A SID164 ISPI2 Block current consumption at 4 Mbits/sec - - 560 A SID165 ISPI3 Block current consumption at 8 Mbits/sec - - 600 A Min Typ Max Units - - 8 MHz Min Typ Max Units Table 23. Fixed SPI AC Specifications (Guaranteed by Characterization) Spec ID# SID166 Parameter FSPI Description SPI operating frequency (master; 6X oversampling) Table 24. Fixed SPI Master Mode AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description SID167 TDMO MOSI valid after Sclock driving edge - - 15 ns SID168 TDSI MISO valid before Sclock capturing edge. Full clock, late MISO Sampling used 20 - - ns SID169 THMO Previous MOSI data hold time with respect to capturing edge at Slave 0 - - ns Min Typ Table 25. Fixed SPI Slave mode AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Max Units SID170 TDMI MOSI valid before Sclock capturing edge 40 - - ns SID171 TDSO MISO valid after Sclock driving edge - - 42 + 3 x TSCB ns SID171A TDSO_ext MISO valid after Sclock driving edge in Ext. Clock mode - - 48 ns SID172 THSO Previous MISO data hold time 0 - - ns SID172A TSSELSCK SSEL Valid to first SCK Valid edge 100 - - ns Document Number: 001-91686 Rev. *I Page 27 of 45 PSoC(R) 4: PSoC 4200L Datasheet Memory Table 26. Flash DC Specifications Spec ID# SID173 Parameter VPE Description Erase and program voltage Min Typ Max Units 1.71 - 5.5 V Details/Conditions Table 27. Flash AC Specifications Description Min Typ Max Units Details/Conditions SID174 Spec ID# TROWWRITE Parameter Row (block) write time (erase and program) - - 20 ms Row (block) = 256 bytes SID175 TROWERASE Row erase time - - 13 ms SID176 TROWPROGRAM Row program time after erase - - 7 ms SID178 TBULKERASE Bulk erase time (128 KB) - - 35 ms SID180 TDEVPROG Total device program time - - 15 SID181 FEND Flash endurance 100 k - - cycles Guaranteed by characterization SID182 FRET Flash retention. TA 55 C, 100 k P/E cycles 20 - - years Guaranteed by characterization Flash retention. TA 85 C, 10 k P/E cycles 10 - - years Guaranteed by characterization Flash retention. TA 105 C, 10 k P/E cycles, three years at TA 85 C 10 20 - years Guaranteed by characterization. SID182A SID182B FRETQ Document Number: 001-91686 Rev. *I seconds Guaranteed by characterization Page 28 of 45 PSoC(R) 4: PSoC 4200L Datasheet System Resources Power-on-Reset (POR) with Brown Out Table 28. Imprecise Power On Reset (PRES) Min Typ Max Units SID185 Spec ID# VRISEIPOR Parameter Rising trip voltage Description 0.80 - 1.45 V Guaranteed by characterization Details/Conditions SID186 VFALLIPOR Falling trip voltage 0.75 - 1.4 V Guaranteed by characterization SID187 VIPORHYST Hysteresis 15 - 200 mV Guaranteed by characterization Table 29. Precise Power On Reset (POR) Min Typ Max Units SID190 Spec ID# VFALLPPOR Parameter BOD trip voltage in active and sleep modes Description 1.64 - - V Guaranteed by characterization Details/Conditions SID192 VFALLDPSLP BOD trip voltage in Deep Sleep 1.4 - - V Guaranteed by characterization Voltage Monitors Table 30. Voltage Monitors DC Specifications Spec ID# SID195 Parameter VLVI1 Description LVI_A/D_SEL[3:0] = 0000b Min 1.71 Typ 1.75 Max 1.79 Units V Details/Conditions SID196 VLVI2 LVI_A/D_SEL[3:0] = 0001b 1.76 1.80 1.85 V SID197 VLVI3 LVI_A/D_SEL[3:0] = 0010b 1.85 1.90 1.95 V SID198 VLVI4 LVI_A/D_SEL[3:0] = 0011b 1.95 2.00 2.05 V SID199 VLVI5 LVI_A/D_SEL[3:0] = 0100b 2.05 2.10 2.15 V SID200 VLVI6 LVI_A/D_SEL[3:0] = 0101b 2.15 2.20 2.26 V SID201 VLVI7 LVI_A/D_SEL[3:0] = 0110b 2.24 2.30 2.36 V SID202 VLVI8 LVI_A/D_SEL[3:0] = 0111b 2.34 2.40 2.46 V SID203 VLVI9 LVI_A/D_SEL[3:0] = 1000b 2.44 2.50 2.56 V SID204 VLVI10 LVI_A/D_SEL[3:0] = 1001b 2.54 2.60 2.67 V SID205 VLVI11 LVI_A/D_SEL[3:0] = 1010b 2.63 2.70 2.77 V SID206 VLVI12 LVI_A/D_SEL[3:0] = 1011b 2.73 2.80 2.87 V SID207 VLVI13 LVI_A/D_SEL[3:0] = 1100b 2.83 2.90 2.97 V SID208 VLVI14 LVI_A/D_SEL[3:0] = 1101b 2.93 3.00 3.08 V SID209 VLVI15 LVI_A/D_SEL[3:0] = 1110b 3.12 3.20 3.28 V SID210 VLVI16 LVI_A/D_SEL[3:0] = 1111b 4.39 4.50 4.61 V SID211 LVI_IDD Block current - - 100 A Guaranteed by characterization Min Typ Max Units Details/Conditions - - 1 s Table 31. Voltage Monitors AC Specifications Spec ID# SID212 Parameter TMONTRIP Description Voltage monitor trip time Document Number: 001-91686 Rev. *I Guaranteed by characterization Page 29 of 45 PSoC(R) 4: PSoC 4200L Datasheet SWD Interface Table 32. SWD Interface Specifications Spec ID# Parameter Description Min Typ Max Units Details/Conditions SID213 F_SWDCLK1 3.3 V VDD 5.5 V - - 14 MHz SWDCLK 1/3 CPU clock frequency SID214 F_SWDCLK2 1.71 V VDD 3.3 V - - 7 MHz SWDCLK 1/3 CPU clock frequency SID215 T_SWDI_SETUP T = 1/f SWDCLK 0.25 * T - - ns Guaranteed by characterization SID216 T_SWDI_HOLD 0.25 * T - - ns Guaranteed by characterization SID217 T_SWDO_VALID T = 1/f SWDCLK - - 0.5 * T ns Guaranteed by characterization SID217A T_SWDO_HOLD T = 1/f SWDCLK 1 - - ns Guaranteed by characterization Min Typ Max Units T = 1/f SWDCLK Internal Main Oscillator Table 33. IMO DC Specifications (Guaranteed by Design) Spec ID# Parameter Description SID218 IIMO1 IMO operating current at 48 MHz - - 1000 A SID219 IIMO2 IMO operating current at 24 MHz - - 325 A SID220 IIMO3 IMO operating current at 12 MHz - - 225 A SID221 IIMO4 IMO operating current at 6 MHz - - 180 A SID222 IIMO5 IMO operating current at 3 MHz - - 150 A Details/Conditions Table 34. IMO AC Specifications Min Typ Max Units SID223 Spec ID# FIMOTOL1 Parameter Frequency variation from 3 to 48 MHz Description - - 2 % SID226 TSTARTIMO IMO startup time - - 12 s SID227 TJITRMSIMO1 RMS Jitter at 3 MHz - 156 - ps SID228 TJITRMSIMO2 RMS Jitter at 24 MHz - 145 - ps SID229 TJITRMSIMO3 RMS Jitter at 48 MHz - 139 - ps Min Typ Max Units Details/Conditions Internal Low-Speed Oscillator Table 35. ILO DC Specifications (Guaranteed by Design) Spec ID# Parameter Description Details/Conditions SID231 IILO1 ILO operating current at 32 kHz - 0.3 1.05 A Guaranteed by Characterization SID233 IILOLEAK ILO leakage current - 2 15 nA Guaranteed by Design Document Number: 001-91686 Rev. *I Page 30 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 36. ILO AC Specifications Spec ID# Parameter Description Min Typ Max Units Details/Conditions SID234 TSTARTILO1 ILO startup time - - 2 ms Guaranteed by characterization SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by characterization SID237 FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Min Typ Max Units 60% with trim. Table 37. PLL DC Specifications Spec ID# Parameter Description SID410 IDD_PLL_48 In = 3 MHz, Out = 48 MHz - 530 610 A SID411 IDD_PLL_24 In = 3 MHz, Out = 24 MHz - 300 405 A Min Typ Max Units Details/Conditions Table 38. PLL AC Specifications Spec ID# Parameter Description Details/Conditions SID412 FPLLIN PLL input frequency 1 - 48 MHz SID413 FPLLINT PLL intermediate frequency; prescaler out 1 - 3 MHz SID414 FPLLVCO VCO output frequency before post-divide 22.5 - 104 MHz SID415 DIVVCO VCO Output post-divider range; PLL output frequency is FPPLVCO/DIVVCO 1 - 8 - SID416 PLLlocktime Lock time at startup - - 250 us SID417 Jperiod_1 Period jitter for VCO 67 MHz - - 150 ps Guaranteed By Design SID416A Jperiod_2 Period jitter for VCO 67 MHz - - 200 ps Guaranteed By Design Min Typ Max Units Details/Conditions Table 39. External Clock Specifications Spec ID# Parameter Description SID305 ExtClkFreq External Clock input Frequency 0 - 48 MHz Guaranteed by characterization SID306 ExtClkDuty Duty cycle; Measured at VDD/2 45 - 55 % Guaranteed by characterization Table 40. Watch Crystal Oscillator (WCO) Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions IMO WCO-PLL calibrated mode SID330 IMOWCO1 Frequency variation with IMO set to 3 MHz -0.6 - 0.6 % Does not include WCO tolerance SID331 IMOWCO2 Frequency variation with IMO set to 5 MHZ -0.4 - 0.4 % Does not include WCO tolerance SID332 IMOWCO3 Frequency variation with IMO set to 7 or 9 MHZ -0.3 - 0.3 % Does not include WCO tolerance SID333 IMOWCO4 All other IMO frequency settings -0.2 - 0.2 % Does not include WCO tolerance Document Number: 001-91686 Rev. *I Page 31 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 40. Watch Crystal Oscillator (WCO) Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions WCO Specifications SID398 FWCO Crystal frequency - 32.768 - kHz SID399 FTOL Frequency tolerance - 50 250 ppm SID400 ESR Equivalent series resistance - 50 - k SID401 PD Drive Level - - 1 W SID402 TSTART Startup time - - 500 ms SID403 CL Crystal load capacitance 6 - 12.5 pF SID404 C0 Crystal shunt capacitance - 1.35 - pF SID405 IWCO1 Operating current (high power mode) - - 8 uA Min Typ Max Units With 20-ppm crystal. Table 41. External Crystal Oscillator (ECO) Specifications Spec ID# Parameter Description SID316 IECO1 Block operating current - - 1.5 mA SID317 FECO Crystal frequency range 4 - 33 MHz Details/Conditions Table 42. UDB AC Specifications (Guaranteed by Characterization) Spec ID# Parameter Description Min Typ Max Units Details/Conditions Datapath performance SID249 FMAX-TIMER Max frequency of 16-bit timer in a UDB pair - - 48 MHz SID250 FMAX-ADDER Max frequency of 16-bit adder in a UDB pair - - 48 MHz SID251 FMAX_CRC Max frequency of 16-bit CRC/PRS in a UDB pair - - 48 MHz Max frequency of 2-pass PLD function in a UDB pair - - 48 MHz PLD Performance in UDB SID252 FMAX_PLD Clock to Output Performance SID253 TCLK_OUT_UDB1 Prop. delay for clock in to data out at 25 C, Typ. - 15 - ns SID254 TCLK_OUT_UDB2 Prop. delay for clock in to data out, Worst case. - 25 - ns Document Number: 001-91686 Rev. *I Page 32 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 43. Block Specs Spec ID# Parameter SID256 TWS48 Description Number of wait states at 48 MHz Min 2 Typ - Max - SID257 TWS24 Number of wait states at 24 MHz 1 - - SID260 VREFSAR Trimmed internal reference to SAR -1 - +1 SID261 FSARINTREF SAR operating speed without external reference bypass - 500 - SID262 TCLKSWITCH Clock switching from clk1 to clk2 in clk1 periods 3 - 4 Units Details/Conditions CPU execution from Flash. Guaranteed by characterization CPU execution from Flash. Guaranteed by characterization % Percentage of Vbg (1.024 V). Guaranteed by characterization ksps 12-bit resolution. Guaranteed by characterization Periods Guaranteed by design * Tws48 and Tws24 are guaranteed by Design Table 44. UDB Port Adaptor Specifications (Based on LPC Component Specs; all specs except TLCLKDO are guaranteed by design -10-pF load, 3-V VDDIO and VDDD) Spec ID# Parameter Description Min Typ Max Units Details/Conditions SID263 TLCLKDO LCLK to output delay - - 18 ns SID264 TDINLCLK Input setup time to LCLCK rising edge - - 7 ns SID265 TDINLCLKHLD Input hold time from LCLK rising edge 0 - - ns SID266 TLCLKHIZ LCLK to output tristated - - 28 ns SID267 TFLCLK LCLK frequency - - 33 MHz SID268 TLCLKDUTY LCLK duty cycle (percentage high) 40 - 60 % Min Typ Max Units Details / Conditions Table 45. USB Device Block Specifications (USB only) Spec ID# Parameter Description SID321 Vusb_5 Device supply for USB operation 4.5 - 5.5 V SID322 Vusb_3.3 Device supply for USB operation 3.15 - 3.6 V SID323 Vusb_3.3 2.85 - 3.6 V SID324 Iusb_config - 10 - mA SID325 Iusb_config - 8 - mA VDDD = 3.3 V SID326 Isub_suspend Device supply for USB operation (Functional operation only) Device supply current in Active mode, IMO = 24 MHz Device supply current in Active mode, IMO = 24 MHz Device supply current in Sleep mode USB Configured, USB Reg. enabled USB Configured, USB Reg. bypassed USB Configured, USB Reg. bypassed VDDD = 5 V - 0.5 - mA SID327 Isub_suspend Device supply current in Sleep mode - 0.3 - mA SID328 Isub_suspend Device supply current in Sleep mode - 0.5 - mA SID329 Isub_suspend Device supply current in Sleep mode - 0.3 - mA VDDD = 5 V, PICU wakeup VDDD = 5 V, Device disconnected VDDD = 3.3 V, PICU wakeup VDDD = 3.3 V, Device disconnected Document Number: 001-91686 Rev. *I Page 33 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 46. SIO Specifications Spec ID# Parameter Description Min Typ Max Units Details / Conditions SIO DC Specifications SID330 VIH Input voltage high threshold 0.7 * VDD - - V CMOS input; with respect to VDDIO SID331 VIL Input voltage low threshold - - 0.3*VDD V CMOS input; with respect to VDDIO SID332 VIH Differential input mode high voltage; hysteresis disabled Vr + 0.2 - - V Vr is the SIO reference voltage SID333 VIL Differential input mode low voltage, hysteresis disabled - - Vr-0.2 V Vr is the SIO reference voltage SID334 VOH Output high voltage in unregulated mode VDDIO - 0.4 - - V IOH = 4 mA, VDD = 3.3 V SID335 VOH Output high voltage in regulated mode Vr - 0.65 - Vr + 0.2 V IOH = 1 mA SID336 VOH Output high voltage in regulated mode Vr - 0.3 - Vr + 0.2 V IOH = 0.1 mA SID337 VOL Output low voltage - - 0.8 V VDDIO = 3.3 V, IOL = 25 mA SID338 VOL Output low voltage VDDIO = 1.8 V, IOL = 4 mA SID339 Vinref Input voltage reference SID340 Voutref SID341 - - 0.4 V 0.48 - 0.52 * VDDIO V Output voltage reference (regulated mode) 1 - VDDIO - 1 V VDDIO > 3.3 Voutref Output voltage reference (regulated mode) 1 - VDDIO - 0.5 V VDDIO < 3.3 SID342 RPULLUP Pull-up resistor 3.5 5.6 8.5 k SID343 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 k SID344 IIL Input leakage current (absolute value) - - 14 nA VIH VDDSIO; 25 C SID345 IIL Input leakage current (absolute value) - - 10 nA VIH > VDDSIO; 25 C SID346 CIN Input capacitance - - 7 pF SID347 VHYST-Single Hysteresis in single-ended mode - 40 - mV SID348 VHYST_Diff Hysteresis in differential mode - 35 - mV SID349 IDIODE Current through protection diode to VDD/VSS - - 100 A SIO AC Specifications (Guaranteed By Design) SID350 TRISEF Rise time in Fast Strong mode - - 12 ns 3.3-V VDD, Cload = 25 pF SID351 TFALLF Fall time in Fast Strong mode - - 12 ns 3.3-V VDD, Cload = 25 pF SID352 TRISES Rise time in Slow Strong mode - - 75 ns 3.3-V VDD, Cload = 25 pF SID353 TFALLS Fall time in Slow Strong mode - - 70 ns 3.3-V VDD, Cload = 25 pF SID354 FSIOUT1 SIO Fout; Unregulated, Fast Strong mode - - 33 MHz 3.3-V VDD 5.5 V, 25 pF. Guaranteed by design. SID355 FSIOUT2 SIO Fout; Unregulated, Fast Strong mode - - 16 MHz 1.71-V VDD 3.3 V, 25 pF SID356 FSIOUT3 SIO Fout; Regulated, Fast Strong mode - - 20 MHz 3.3-V VDD 5.5 V, 25 pF SID357 FSIOUT4 SIO Fout; Regulated, Fast Strong mode - - 10 MHz 1.71 V VDD 3.3 V, 25 pF Document Number: 001-91686 Rev. *I Page 34 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 46. SIO Specifications (continued) Spec ID# Parameter Description Min Typ Max Units Details / Conditions SID358 FSIOUT3 SIO Fout; Unregulated, Slow Strong mode. - - 5 MHz 3.3 V VDD 5.5 V, 25 pF SID359 FSIOUT4 SIO Fout, Unregulated, Slow Strong mode. - - 3.5 MHz 1.71 V VDD 3.3 V, 25 pF SID360 FSIOUT5 SIO Fout, Regulated, Slow Strong mode. - - 2.5 MHz 1.7 V VDD 5.5 V, 25 pF SID361 FGPIOIN GPIO input operating frequency;1.71 V VDD 5.5 V - - 48 MHz 1.71 V VDD 5.5 V Table 47. CAN Specifications Min Typ Max Units SID420 Spec ID# IDD_CAN Parameter Block current consumption Description - - 200 uA SID421 CAN_bits CAN Bit rate (Min 8-MHz clock) - - 1 Mbps Document Number: 001-91686 Rev. *I Details / Conditions Page 35 of 45 PSoC(R) 4: PSoC 4200L Datasheet Ordering Information The PSoC 4200L family part numbers and features are listed in the following table. Table 48. PSoC 4200L Ordering Information 4247 4248 64-TQFP 68-QFN 124-VFBGA 1000 ksps 2 8 3 - - 38 - - - - - 1000 ksps 2 8 3 - 38 - - - CY8C4246AZI-L435 48 64 8 8 2 - - 1000 ksps 2 8 4 - 53 - - - CY8C4246AZI-L445 48 64 8 8 2 2 1000 ksps 2 8 4 - 53 - - - CY8C4246LTI-L445 48 64 8 8 2 2 1000 ksps 2 8 4 - 57 - - - CY8C4247AZI-L423 48 128 16 8 2 1 1000 ksps 2 8 3 - - 38 - - - CY8C4247AZI-L433 48 128 16 8 2 - - 1000 ksps 2 8 3 - 38 - - - CY8C4247AZI-L445 48 128 16 8 2 2 1000 ksps 2 8 4 - 53 - - - CY8C4247LTI-L445 48 128 16 8 2 2 1000 ksps 2 8 4 - 57 - - - CY8C4247AZI-L475 48 128 16 8 4 2 - 1000 ksps 2 8 4 - 53 - - - 48-TQFP 1 GPIO CAN 2 2 SCB Blocks 8 8 TCPWM Blocks 8 8 12-bit SAR ADC USB Full Speed LP Comparators Direct LCD Drive 64 64 UDB 48 48 SRAM (KB) CY8C4246AZI-L423 Flash (KB) CSD Max CPU Speed (MHz) Op-amp (CTBm) 4246 Package CY8C4246AZI-L433 MPN Category Features CY8C4247LTI-L475 48 128 16 8 4 2 - 1000 ksps 2 8 4 - 57 - - - CY8C4247BZI-L479 48 128 16 8 4 2 - 1000 ksps 2 8 4 - 98 - - - CY8C4247AZI-L485 48 128 16 8 4 2 1000 ksps 2 8 4 53 - - - CY8C4247LTI-L485 48 128 16 8 4 2 1000 ksps 2 8 4 57 - - - CY8C4247LTQ-L485 48 128 16 8 4 2 1000 ksps 2 8 4 57 - - - CY8C4247BZI-L489 48 128 16 8 4 2 1000 ksps 2 8 4 98 - - - CY8C4248BZI-L469 48 256 32 8 4 - - 1000 ksps 2 8 4 - - 96 - - - CY8C4248AZI-L475 48 256 32 8 4 2 - 1000 ksps 2 8 4 - 53 - - - CY8C4248LTI-L475 48 256 32 8 4 2 - 1000 ksps 2 8 4 - 57 - - - CY8C4248BZI-L479 48 256 32 8 4 2 - 1000 ksps 2 8 4 - 98 - - - CY8C4248AZI-L485 48 256 32 8 4 2 1000 ksps 2 8 4 53 - - - CY8C4248LTI-L485 48 256 32 8 4 2 1000 ksps 2 8 4 57 - - - CY8C4248LTQ-L485 48 256 32 8 4 2 1000 ksps 2 8 4 57 - - - CY8C4248BZI-L489 48 256 32 8 4 2 1000 ksps 2 8 4 98 - - - Document Number: 001-91686 Rev. *I Page 36 of 45 PSoC(R) 4: PSoC 4200L Datasheet The nomenclature used in Table 48 is based on the following part numbering convention: Field Description CY8C Cypress Prefix 4 Architecture 4 PSoC 4 A Family 2 4200 Family B CPU Speed 4 48 MHz C DE Values Meaning 6 64 KB 7 128 KB 8 256 KB AX, AZ TQFP LT QFN BZ BGA FD CSP Flash Capacity Package Code I Industrial Q Extended Industrial S PSoC 4 S-Series L PSoC 4 L-Series F Temperature Range S Series Designator M PSoC 4 M-Series XYZ Attributes Code 000-999 Code of feature set in the specific family Part Numbering Conventions The part number fields are defined as follows. CY8C 4 A B C D E F - S XY Z Cypress Prefix Architecture Family Group within Architecture Speed Grade Flash Capacity Package Code Temperature Range Series Designator Attributes Code Document Number: 001-91686 Rev. *I Page 37 of 45 PSoC(R) 4: PSoC 4200L Datasheet Packaging The description of the PSoC4200L package dimensions follows. SPEC ID# PKG_1 Package Description Package DWG # 124-ball VFBGA 124-ball, 9 mm x 9 mm x 1.0 mm height with 0.65 mm ball pitch 001-97718 PKG_2 64-pin TQFP 64-pin TQFP, 10 mm x10 mm x 1,4 mm height with 0.5 mm pitch 51-85051 PKG_3 68-pin QFN 68-pin QFN, 8 mm x 8 mm x 1.0 mm height with 0.4 mm pitch 001-09618 PKG_4 48-pin TQFP 48-pin TQFP, 7 mm x 7 mm x 1.4 mm height with 0.5 mm pitch 51-85135 Table 49. Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature -40 25.00 85 C TJ Operating junction temperature -40 - 100 C TJA Package JA (124-ball VFBGA) - 35 - C/Watt TJA Package JA (64-pin TQFP) - 54 - C/Watt TJA Package JA (68-pin QFN) - 17 - C/Watt TJA Package JA (48-pin TQFP) - 67 - C/Watt Table 50. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature All packages 260 C 30 seconds Table 51. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package All packages Document Number: 001-91686 Rev. *I MSL MSL 3 Page 38 of 45 PSoC(R) 4: PSoC 4200L Datasheet Figure 8. 124-Ball VFBGA Package Outline E PIN A1 CORNER B C A A 5. 124 x Ob (datum B) A1 BALL CORNER A1 7. 6 eD D SD D1 (datum A) SIDE VIEW TOP VIEW eE SE 6 E1 BOTTOM VIEW SYMBOL NOTES: DIMENSIONS MIN. NOM. MAX. A - - 1.00 A1 0.16 0.21 0.26 D 8.90 9.00 9.10 E 8.90 9.00 9.10 D1 7.80 BSC E1 7.80 BSC MD 13 ME 13 N 124 b 0.25 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020. 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH. 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND 0.30 eD 0.65 BSC eE 0.65 BSC SD 0 SE 0 0.35 DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW "SD" OR "SE" = 0. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND "SE" = eE/2. 7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK METALIZED MARK, INDENTATION OR OTHER MEANS. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER BALLS. 9. JEDEC SPECIFICATION NO. REF. : MO-280. 001-97718 *A Figure 9. 64-Pin TQFP Package Outline 51-85051 *D Document Number: 001-91686 Rev. *I Page 39 of 45 PSoC(R) 4: PSoC 4200L Datasheet Figure 10. 68-Pin QFN Package Outline 001-09618 *E Figure 11. 48-Pin TQFP Package Outline 51-85135 *C Document Number: 001-91686 Rev. *I Page 40 of 45 PSoC(R) 4: PSoC 4200L Datasheet Acronyms Table 52. Acronyms Used in this Document Acronym Description Table 52. Acronyms Used in this Document (continued) Acronym Description ETM embedded trace macrocell FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin arithmetic logic unit HVI high-voltage interrupt, see also LVI, LVD analog multiplexer bus IC integrated circuit API application programming interface IDAC current DAC, see also DAC, VDAC APSR application program status register IDE integrated development environment ARM(R) advanced RISC machine, a CPU architecture I ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus ALU AMUXBUS 2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO integral nonlinearity, see also DNL CMRR common-mode rejection ratio INL CPU central processing unit I/O input/output, see also GPIO, DIO, SIO, USBIO CRC cyclic redundancy check, an error-checking protocol IPOR initial power-on reset IPSR interrupt program status register DAC digital-to-analog converter, see also IDAC, VDAC IRQ interrupt request DFB digital filter block ITM instrumentation trace macrocell DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. LCD liquid crystal display DMIPS Dhrystone million instructions per second LIN Local Interconnect Network, a communications protocol. DMA direct memory access, see also TD LR link register DNL differential nonlinearity, see also INL LUT lookup table DNU do not use LVD low-voltage detect, see also LVI DR port write data registers LVI low-voltage interrupt, see also HVI DSI digital system interconnect LVTTL low-voltage transistor-transistor logic DWT data watchpoint and trace MAC multiply-accumulate ECC error correcting code MCU microcontroller unit ECO external crystal oscillator MISO master-in slave-out EEPROM electrically erasable programmable read-only memory NC no connect EMI electromagnetic interference NMI nonmaskable interrupt EMIF external memory interface NRZ non-return-to-zero EOC end of conversion NVIC nested vectored interrupt controller EOF end of frame NVL nonvolatile latch, see also WOL EPSR execution program status register ESD electrostatic discharge Document Number: 001-91686 Rev. *I opamp operational amplifier PAL programmable array logic, see also PLD Page 41 of 45 PSoC(R) 4: PSoC 4200L Datasheet Table 52. Acronyms Used in this Document (continued) Acronym Description Table 52. Acronyms Used in this Document (continued) Acronym Description PC program counter SWV single-wire viewer PCB printed circuit board TD transaction descriptor, see also DMA PGA programmable gain amplifier THD total harmonic distortion PHUB peripheral hub TIA transimpedance amplifier PHY physical layer TRM technical reference manual PICU port interrupt control unit TTL transistor-transistor logic PLA programmable logic array TX transmit PLD programmable logic device, see also PAL UART PLL phase-locked loop Universal Asynchronous Transmitter Receiver, a communications protocol PMDD package material declaration data sheet UDB universal digital block POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register PSoC(R) Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL I2C serial clock SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol Document Number: 001-91686 Rev. *I USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Page 42 of 45 PSoC(R) 4: PSoC 4200L Datasheet Document Conventions Units of Measure Table 53. Units of Measure Symbol Unit of Measure C degrees Celsius dB decibel fF femto farad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz k kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M mega-ohm Msps megasamples per second A microampere F microfarad H microhenry s microsecond V microvolt W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt ohm pF picofarad ppm parts per million ps picosecond s second sps samples per second sqrtHz square root of hertz V volt Document Number: 001-91686 Rev. *I Page 43 of 45 PSoC(R) 4: PSoC 4200L Datasheet Revision History Description Title: PSoC(R) 4: PSoC 4200L Datasheet Programmable System-on-Chip (PSoC(R)) Document Number: 001-91686 Orig. of Submission Revision ECN Description of Change Change Date ** 4414601 WKA 02/06/2015 New datasheet for new device family. *A 4774497 WKA 05/22/2015 Updated Pin List. Added a footnote explaining ground perturbations in GPIO AC Specifications. Updated values for SID269, SID270, SID271, and SID291. Added Conditions for Deep Sleep Mode in Opamp Specifications. Updated Conditions for SID_DS_10 through SID_DS_18. Added Conditions for SID_DS_22 through SID_DS_24. Updated description for SID85 and SID85A. Updated values for SID89, SID248, SID259, SID91, SID258, and SID92. Updated max value for SID.TCPWM.2A. Updated typ and max values for SID149. Added PLL DC Specifications and PLL AC Specifications. Updated Watch Crystal Oscillator (WCO) Specifications. Added CAN Specifications. Changed FBGA package to VFBGA package. *B 4867142 WKA 08/03/2015 Changed datasheet status to Preliminary. Updated Pinouts. Removed typ value for SID43. Updated Conditions for SID_DS_7, SID_DS_8, and SID_DS_9. Updated max value for SID87. Removed SID179. Added External Crystal Oscillator (ECO) Specifications. Updated max value for SID321, SID353, and SID359. Added "Guaranteed by Design" note for SID354. Updated Ordering Information. *C 5034067 WKA 12/03/2015 Updated Conditions for SID85A, SID247A, SID259, SID92, SID417, SID416A Updated typ and max values for SID410. Updated description for SID323. Added "Guaranteed by Characterization" note for SIO AC Specs. Updated Ordering Information. *D 5170871 WKA 03/11/2016 Removed VDDA and VDDIO pins in Regulated External Supply section. Updated values for Deep Sleep Mode, Hibernate Mode and Stop Mode in DC Specifications. Added SID299A. Added a note in UDB Port Adaptor Specifications that all specs except TLCLKDO are guaranteed by design. Updated TJA value for the 124-VFBGA package. *E 5281150 WKA 05/23/2016 Changed datasheet status to Final. Updated max values for SID6, SID7, SID8, SID9, SID31, SID32, SID34, SID35, SID40, SID41, SID43, and SID44. Updated the template. *F 5516529 WKA 11/15/2016 Added CY8C4248BZI-L469 in Ordering Information. *G 5559970 WKA 11/20/2016 Updated max values for SID33, SID34, and SID35. Updated SID171. *H 5713202 GNKK 04/27/2017 Updated the Cypress logo and copyright information. Updated 124-ball VFBGA package diagram. Corrected typo in the part numbering convention table. *I 6201292 WKA 06/08/2018 Updated title to "PSoC(R) 4: PSoC 4200L Datasheet". Corrected links in More Information. Added SID182B in Flash AC Specifications. Added CY8C4247LTQ-L485 and CY8C4248LTQ-L485 in Ordering Information. Added Extended Industrial temperature range in the part numbering convention table. Document Number: 001-91686 Rev. *I Page 44 of 45 PSoC(R) 4: PSoC 4200L Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. 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Document Number: 001-91686 Rev. *I Revised June 8, 2018 Page 45 of 45