Advanced Diff. Speed Sensor TLE4941plusC Data Sheet Revision 1.2 Edition May 2017 Published by Infineon Technologies AG 81726 Munchen, Germany (c) 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE4941plusC Confidential Revision History: May 2017, Revision 1.2 Previous Version: February 2011, Revision 1.1 Page Subjects (major changes since revision 1.0) 28, 29 Updated package drawings May 2017, Revision 1.2 February 2011, Revision 1.1 13, 14 Footnote at "junction temperature" changed Final Data Sheet Rev.1.0 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com Data Sheet 3 Revision 1.2, May 2017 TLE4941plusC Confidential Revision History, Revision 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 1.1 1.2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 2.1 2.2 2.3 2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration and sensitive area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking and data matrix code description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magnetical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Magnetic Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Diagrams (measured performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electro Magnetic Compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 17 18 20 21 22 25 4 4.1 4.2 4.3 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lead Pull Out Force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing and Package Dimensions of PG-SSO-2-53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 28 30 Data Sheet 4 6 6 6 7 8 Revision 1.2, May 2017 Confidential Advanced Differential Two-Wire Hall Effect Sensor IC 1 Product Description 1.1 Overview TLE4941plusC The Hall Effect sensor IC TLE4941plusC is designed to provide information about rotational speed to modern vehicle dynamics control systems and Anti-Lock Braking Systems (ABS). The output has been designed as a two wire current interface. The sensor operates without external components and combines a fast power-up time with a low cutoff frequency. Designed specifically to meet harsh automotive requirements, excellent accuracy and sensitivity is specified over a wide temperature range and robustness to ESD and EMC has been maximized. State-of-the art BiCMOS technology is used for monolithic integration of the active sensor areas and the signal conditioning circuitry. Finally, the optimized piezo compensation and the integrated dynamic offset compensation enables ease of manufacturing and the elimination of magnetic offsets. The TLE4941plusC is additionally provided with an overmolded 1.8 nF capacitor for improved EMC performance. 1.2 * * * * * * * * * * * Features Two-wire current interface Dynamic self-calibration principle Single chip solution No external components needed High sensitivity South and north pole pre-induction possible High resistive to piezo effects Large operating air-gaps Wide operating temperature range TLE4941plusC: 1.8 nF overmolded capacitor Applicable for small pitches (2mm Hall element distance) Product Name Product Type Ordering Code Packing Advanced Diff. Speed Sensor TLE4941plusC SP000478508 PG-SSO-2-53 Data Sheet 5 Revision 1.2, May 2017 TLE4941plusC Confidential 2 Functional Description 2.1 General Functional Description The differential Hall sensor IC detects the motion of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect the motion of ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet. Either south or north pole of the magnet can be attached to the back side of the IC package. Magnetic offsets of up to 30mT and device offsets are cancelled by a self-calibration algorithm. Only a few magnetic edges are necessary for self-calibration. After the offset calibration sequence, switching occurs when the input signal crosses the arithmetic mean of its max. and min. value (e.g. zero-crossing for sinusoidal signals). The ON and OFF state of the IC are indicated by High and Low current consumption. 2.2 Pin Configuration and sensitive area description Figure 1 Pin Description and sensitive area (view on front side marking of component) Data Sheet 6 Revision 1.2, May 2017 TLE4941plusC Confidential 2.3 Functional Description Marking and data matrix code description VDD GND VDD GND G: YY: WW: green package production year production week 123456: 41CPA AE TLE4941plusC Figure 2 Data Sheet Front side and Backside Marking of PG-SSO-2-53 7 Revision 1.2, May 2017 TLE4941plusC Confidential 2.4 Functional Description Block Diagram PMU hys.-ctrl TrackingADC Offset-DAC D-Core Hall Probes VDD ESD async logic Preamplifier Tracking-ADC Algorithm BandgapBiasing Current Modulator MainComparator LPFilter GND Oscillator Fuses Figure 3 Block Diagram The circuit is supplied internally by a 3V voltage regulator. An on-chip oscillator serves as clock generator for the digital part of the circuit. TLE4941plusC signal path is comprised of a Hall probe pair, spaced at 2.0 mm, a differential amplifier, including a noise-limiting low-pass filter, and a comparator feeding a switched current output stage. In addition an offset cancellation feedback loop is provided by a tracking AD-converter, a digital core and an offset cancellation D/A converter. The differential input signal is digitized in the tracking A/D converter and fed into the digital core. The minimum and maximum values of the input signal are extracted and their corresponding arithmetic mean value is calculated. The offset of this mean value is determined and fed back into the offset cancellation DAC. In running mode (calibrated mode) the offset correction algorithm of the DSP is switched into a low-jitter mode, avoiding oscillation of the offset DAC LSB. Switching occurs at zero-crossing. It is only affected by the (small) remaining offset of the comparator and by the remaining propagation delay time. Signals below a defined threshold BLimit (see description Figure 8) are not detected to avoid unwanted parasitic switching. 2.4.1 Uncalibrated Mode The short initial offset settling time td,input may delay the detection of the input signal (the sensor is not yet "awake"). The magnetic input signal is tracked by the tracking ADC and monitored within the digital core. For detection the signal transient needs to exceed a threshold DNC (digital noise constant d1). When the signal slope is identified as a rising edge (or falling edge), a trigger pulse is issued to current modulator. A second trigger pulse is issued as soon as a falling edge (or rising edge respectively) is detected (and vice versa). Data Sheet 8 Revision 1.2, May 2017 TLE4941plusC Confidential Functional Description The digital noise constant value changes (d1 d2) with the magnetic field amplitude, leading to a phase shift between the magnetic input signal and output signal. This value of the digital noise constant is determined by the signal amplitude and initial offset value. The smallest DNC, indicated as d1 in figure 4, represents parameter "dB_startup". After calibration, consecutive output edges should have a nominal delay of about 180. dB dBmax d2 = (dBmax-dBStart)/4 d1 dBStart Offsetcorrection t1 d3 = ( dBmax-dBmin)/4 dBmin Phase shift change Uncalibrated Mode Calibrated Mode d1=dBstartup t 1=initial calibration delay time Offset correction=(dBmax +dBmin)/2 Figure 4 Data Sheet Example for Start-up Behavior 9 Revision 1.2, May 2017 TLE4941plusC Confidential 2.4.2 Functional Description Transition to Calibrated Mode In the calibrated mode the output will switch at zero-crossing of the input signal. The phase shift between input and output signal is no longer determined by the ratio between digital noise constant and signal amplitude. Therefore a sudden change in the phase shift may occur during the transition from uncalibrated to calibrated mode. 2.4.3 Additional Notes The summed up change in phase shift from the first output edge issued to the output edges in calibrated mode will not exceed 90. 2.4.4 Output Description Under ideal conditions, the output shows a duty cycle of 50%. Under real conditions, the duty cycle is determined by the mechanical dimensions of the target wheel and its tolerances (40% to 60% might be exceeded for pitch >> 4mm due to the zero-crossing principle). Speed Signal Sensor Internal Transferred Speed Signal AET03202 Figure 5 Data Sheet Speed Signal (half a period = 0.5 x 1/fspeed) 10 Revision 1.2, May 2017 TLE4941plusC Confidential Functional Description Figure 6 Definition of Rise and Fall Time; Duty Cycle = t1/T x 100% 2.4.5 Behavior at Magnetic Input Signals Slower than fmag < 1Hz Magnetic changes exceeding Bstartup can cause output switching of the TLE4941plusC, even at fmag significantly lower than 1 Hz. Depending on their amplitude edges slower than tstartup might be detected. If the digital noise constant ( Bstartup) is not exceeded before tstartup a new initial self-calibration is started. In other words Bstartup needs to be exceeded before tstartup. Output switching strongly depends on signal amplitude and initial phase. Data Sheet 11 Revision 1.2, May 2017 TLE4941plusC Confidential 2.4.6 Functional Description Undervoltage Behavior The voltage supply comparator has an integrated hysteresis Vhys with the maximum value of the release level Vrel < 4.5V. This determines the minimum required supply voltage VDD of the chip. A minimum hysteresis Vhys of 0.7V is implemented thus avoiding a toggling of the output when the supply voltage VDD is modulated due to the additional voltage drop at RM when switching from low to high current level and VDD = 4.5V (designed for use with RM==75). Ihigh Ilow VDD * V rel Vhys V res Vhys = V rel - Vres *direct on pins Figure 7 Data Sheet Start-up and undervoltage behavior 12 Revision 1.2, May 2017 TLE4941plusC Confidential Specification 3 Specification 3.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings Tj = - 40C to 150C, 4.5 V VDD 20 V if not indicated otherwise Parameter Supply voltage Symbol VDD Limit Values Unit Remarks V Tj < 80C min. max. -0.3 - - 20 Tj = 150C - 22 t = 10 x 5 min. - 24 t = 10 x 5 min. RM 75 included in VDD - 27 t = 400 ms, RM 75 included in VDD Reverse polarity voltage Urev -22 Reverse polarity current Irev - Junction temperature1) RM 75 included in VDD, t<1 h 200 mA External current limitation required, t < 4 h 300 mA External current limitation required, t<1 h Tj EITHER 125 10.000h OR 150 5000 h OR 160 2500 h, OR 170 500 h Additional 190 4 h, VDD < 16.5 V Number of power on cycles -40 500.000 Immunity to external fields Thermal resistance PG-SSO-2-53 V RthJA - times 1 Tesla is equivalent to 800kA/m; Tj=-40..175C2) 190 K/W 3) 1) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. 2) Conversion: B=0*H (0=4**10-7); 3) Can be significantly improved by further processing like overmolding Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Data Sheet 13 Revision 1.2, May 2017 TLE4941plusC Confidential Specification 3.1.1 ESD Robustness Table 2 ESD Protection Characterized according to Human Body Model (HBM) tests in compliance with Standard EIA/JESD22-A114-B HBM (covers MIL STD 883D) Parameter Symbol VESD ESD-Protection Test Result Unit 12 Notes R = 1.5 k, C = 100 pF kV or >8000V for TLE4941plusC (H3B according AEC Q100) Note: Tested at room temperature 3.2 Operating Range Table 3 Operating Range Parameter Symbol Limit Values min. Supply voltage Supply voltage modulation Junction temperature3) Unit Remarks max. VDD Extended Range 4.5 20 20 241) V Directly on IC leads; includes not the voltage drop at RM VAC - 6 Vpp VDD = 13 V 0 < fmod < 150 kHz2) C Tj EITHER -40 OR 125 10.000h 150 5000 h OR 160 2500 h OR 170 500 h B0 Bstat., l/r -500 +500 mT -30 +30 mT Differential Induction B -120 +120 mT Magnetic signal frequency fmag 1 10000 Hz Pre-induction Pre-induction offset between outer probes 1) Extended range of 20..24V is not recommended. Latch-up test with factor 1.5 is not covered. Please see max ratings also. 2) sin wave 3) This lifetime statement is an anticipation based on an extrapolation of Infineon's qualification test results. The actual lifetime of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime statement shall in no event extend the agreed warranty period. Data Sheet 14 Revision 1.2, May 2017 TLE4941plusC Confidential Specification 3.3 Electrical Characteristics Table 4 1) All values specified at constant amplitude and offset of input signal, over operating range, unless otherwise specified. Typical values correspond to VDD = 12 V and TA = 25C Parameter Symbol Limit Values min. Supply current Supply current Supply current ratio Output rise/fall slew rate TLE4941plusC Line regulation Initial calibration delay time Unit typ. ILow 5.9 IHigh IHigh / ILow 8.4 mA 11.8 14 16.8 mA 1.9 2.1 2.3 tr , tf - - dIx/dVDD td,input - 120 Power up time Magnetic edges required for offset calibration Number of edges in uncalibrated mode max. 7 8 8 mA/s 90 A/V quasi static7) 300 s Additional to nstart2)7) 100 us 3)7) - - 4 magn. edges nDZ-Startup - - 4 edges Magnetic edges required for first output pulse 1 RM = 75 +/-5% Tj < 125C Tj < 170C See Figure 6 22 26 nstart Number of edges suppressed Remarks 5th edge correct 4)7) 7) 0 after power on or reset 2 after power on or reset DC 40 50 60 % @B 2 mT sine wave see Figure 6 5) f 1 2500 - - 2500 10000 Hz 6) Jitter, Tj < 150C Tj < 170C 1 Hz < fmag < 2500 Hz SJit-close - - - - 2 3 % 1 value VDD = 12 V B 2 mT 7) Jitter, Tj < 150C Tj < 170C 2500 Hz < fmag < 10000 Hz SJit-close - - - - 3 4.5 % 1 value VDD = 12 V B 2 mT 7) Jitter, Tj < 150C Tj < 170C 1 Hz < fmag < 2500 Hz SJit-far - - - - 4 6 % 1 value VDD = 12 V 2 mT B > BLimit 7) Jitter, Tj < 150C Tj < 170C 2500 Hz < fmag < 10000 Hz SJit-far - - - - 6 9 % 1 value VDD = 12 V 2 mT B > BLimit 7) Jitter at board net ripple fmag<10kHz SJit-AC 0.5 % VDD = 13 V 6 Vpp 0 < fmod < 150 kHz B = 15 mT 7)8) Duty cycle Signal frequency Permitted time for edge to exceed Bstartup tstartup - - 590 ms 7) Time before chip reset9) tReset 590 - 848 ms 7) Data Sheet 15 Revision 1.2, May 2017 TLE4941plusC Confidential Table 4 Specification 1) All values specified at constant amplitude and offset of input signal, over operating range, unless otherwise specified. Typical values correspond to VDD = 12 V and TA = 25C Parameter Symbol Limit Values min. Signal behavior after undervoltage or standstill > tReset Number of magnetic edges where the first switching occur nDZ-Start Systematic phase error of output edges during start-up and uncalibrated mode Phase shift change during transition from uncalibrated to calibrated mode Unit typ. Remarks max. 1 - 2 edge Magnetic edge amplitude according to Bstartup. td,input has to be taken into account7)10) -90 - +90 Systematical phase error of "uncal" edge; nth vs. n + 1th edge (does not include random phase error)7) 7) switch -45 -90 - +45 +90 dBpp>4*dBstartup dBpp<4*dBstartup 1) All parameters refer to described test circuit in this document. See chapter 3.6 test circuit 2) Occurrence of "Initial calibration delay time td,input " If there is no input signal (standstill), a new initial calibration is triggered each tReset. This calibration has a duration td,input of max. 300 s. No input signal change is detected during that initial calibration time. In normal operation (signal startup) the probability of td,input to come into effect is: td,input / time frame for new calibration 300 s/700 ms = 0.05%. After IC resets (e.g. after a significant undervoltage) td,input will always come into effect. 3) VDD>=4.5V 4) One magnetic edge is defined as a monotonic signal change of more than 3.3 mT 5) During fast offset alterations, due to the calibration algorithm, exceeding the specified duty cycle is permitted for short time periods 6) Frequency behavior not subject to production test - verified by design/characterization. Frequency above 2500 Hz may have influence on jitter performance and magnetic thresholds. 7) Not subject to production test, verified by design/characterization 8) Disturbances are sine-wave shaped: 1sigma value 9) When no output switching occurs for t > tReset the sensor is internally reset after each tReset time frame. See also chapter "2.4.5 Behavior at Magnetic Input Signals Slower than fmag < 1Hz" 10) A loss of edges may occur at high frequencies Data Sheet 16 Revision 1.2, May 2017 TLE4941plusC Confidential Specification 3.4 Magnetic Characteristics Table 5 1) All values specified at constant amplitude and offset of input signal, over operating range, unless otherwise specified. Typical values correspond to VDD = 12 V and TA = 25C Parameter Symbol Limit Values min. Limit threshold 1 Hz < fmag < 2500 Hz 2500 Hz < fmag < 10000 Hz Magnetic differential field change necessary for startup 1 Hz < f < 2500 Hz 2500 Hz < f < 10000 Hz Unit typ. max. BLimit Bstartup Remarks 0.35 0.7 - 1.5 1.7 - - - 0.7 - 1.4 - 3.3 3.9 mT 2) 3) mT Magnetic field change for startup with the first edge (see "Uncalibrated Mode" on 2.4.1) 1) All parameters refer to described test circuit in this document. See chapter 3.6 test circuit. 2) Magnetic amplitude values, sine magnetic field, limits refer to the 50% criteria. 50% of edges are missing 3) BLimit is calculated out of measured sensitivity Data Sheet 17 Revision 1.2, May 2017 TLE4941plusC Confidential 3.5 Specification Description of Magnetic Field 14mA dB dB_limit 7mA dB_limit Figure 8 Description of differential field dB and switching threshold dBlimit (calibrated mode) Note: dB is the resulting signal of difference between signal of right and left Hall element (right - left). dB = B2 (right) - B1 (left) Data Sheet 18 Revision 1.2, May 2017 TLE4941plusC Confidential Specification B / [mT] Right Hall Element Left Hall Element I / [mA] 14 7 Sensor Top View Left (VDD) North South Top View Gyyww i 41CPA Right (GND) left Hall Elements right Branded Side (front side) Definition of magnetic field for this example Positive is considered when South pole shows to rear side of IC housing or when North pole shows to front side (=branded) of IC housing (Gaussmeter: positive at north pole. Dot towards viewer) Figure 9 Definition of field direction and sensor switching Note: "If a positive field is applied to the right Hall probe (located over GND pin) and a negative field (or a weaker field) is applied to the left Hall probe, the resulting output current state is high Data Sheet 19 Revision 1.2, May 2017 TLE4941plusC Confidential 3.6 Specification Test Circuit VDD GND 75ohm Gyyww i TLE4941+C 41CPA VDD Integrated cap on leads Vout Figure 10 Data Sheet Test Circuit for TLE4941plusC 20 Revision 1.2, May 2017 TLE4941plusC Confidential 3.7 Specification Application Circuit Circuit below shows the recommended application circuit with reverse bias and overvoltage protection. D1 R1 TLE4941plusC VS VDD Components D1: 1N4007 D2: Z-Diode, 27V 10F, 35V C1: R1: 10 RM : 75 Figure 11 D2 C1 GND RM Uout Application Circuit An implementation of 10 in VDD path reduces minimum power supply direct on leads of the sensor, but decreases max current at D2 and makes PCB more robust. This PCB represents a compromise of minimum power supply and current flow on D2. With higher values than 10 a higher minimum supply voltage and higher robustness is reached. Data Sheet 21 Revision 1.2, May 2017 TLE4941plusC Confidential 3.8 Specification Typical Diagrams (measured performance) Note: Temperatures above 170C are not guaranteed by this data sheet even if shown below I High / I Low I Low, I High [mA] 18 2,4 16 2,3 14 2,2 12 2,1 10 2 8 1,9 6 1,8 -40 0 40 80 120 160 200 -40 0 40 Tj [C] Figure 12 80 120 160 200 20 25 30 Tj [C] Supply Current = f(T) (left), Supply Current Ratio Ihigh / I Low= f(T) (right) I Low, I High [mA] I High / I Low 18 2,3 16 2,2 14 12 2,1 10 2 8 6 1,9 0 5 10 15 20 25 30 0 VDD [V] Figure 13 Data Sheet 5 10 15 VDD [V] Supply Current =f(VDD) (left), Supply Current Ratio Ihigh / I Low=f(VDD) (right) 22 Revision 1.2, May 2017 TLE4941plusC Confidential Specification Slewrate [mA/s] Slewrate [mA/s] 26 26 24 24 22 20 22 18 20 16 18 14 12 16 10 14 8 6 12 4 10 2 8 0 -40 0 40 80 120 160 200 0 200 Figure 14 1,5 1,3 1,3 1,1 1,1 0,9 0,9 0,7 0,7 0,5 0,5 0,3 0 40 80 120 160 1000 0,3 200 1 Tj [C] Data Sheet 800 dBlimit [mT] 1,5 Figure 15 600 Slew Rate = f(T) , RM = 75 (left), Slew Rate = f(RM) (right) dBlimit [mT] -40 400 Rm [] T j [C] 10 100 1000 10000 f [Hz] Magnetic Threshold BLimit = f(T) at f = 200Hz (left), Magnetic Threshold BLimit = f(f) (right) 23 Revision 1.2, May 2017 TLE4941plusC Confidential Specification Jitter [%] Duty Cycle [%] 2,0 60 1,5 55 1,0 50 0,5 45 0,0 40 -40 0 40 80 120 160 -40 200 Data Sheet 40 80 120 160 200 T j [C] Tj [C] Figure 16 0 Jitter 1 at B = 2 mT at 1 kHz (left), Duty Cycle [%] B = 2 mT at 1 kHz (right) 24 Revision 1.2, May 2017 TLE4941plusC Confidential 3.9 Specification Electro Magnetic Compatibility (EMC) Additional Information: Characterization of Electro Magnetic Compatibility are carried out on sample base of one qualification lot. Not all specification parameters have been monitored during EMC exposure. Only key parameters e.g. switching current and duty cycle have been monitored. Corresponds to Test Circuit of TLE4941/TLE4941C Table 6 Electro Magnetic Compatibility (values depend on RM!) Ref. ISO 7637-1; 2000; EMC test circuit (figure 17) B = 2 mT (amplitude of sinus signal); VDD = 13.5 V; fB = 100 Hz; T = 25C, RM 75 Parameter Symbol Level/Typ Status Testpulse 1 Testpulse 21) Testpulse 3a Testpulse 3b Testpulse 4 Testpulse 5 VEMC IV / -100 V IV / 100 V IV / -150 V IV / 100 V IV / -7 V IV / 86.5 V C C A A B C According to 7637-1 for test pulse 4 the test voltage shall be 12 V 0.2 V. Measured with RM = 75 only. Mainly the current consumption will decrease. Status C with test circuit 1. Ref. ISO 7637-3 Release 1995 2); EMC test circuit (figure 17) B = 2 mT (amplitude of sinus signal); VDD = 13.5 V; fB = 100 Hz; T = 25C; RM 75 Parameter Symbol Level/Typ Status Testpulse 1 Testpulse 2 Testpulse 3a Testpulse 3b VEMC IV / -30 V IV / 30 V IV / -60 V IV / 40 V A A A A Ref. ISO 11452-33); EMC test circuit (figure 17), measured in TEM-cell B = 2 mT; VDD = 13.5 V, fB = 100 Hz; T = 25C Parameter Symbol Level/Typ Remarks EMC field strength ETEM-Cell IV / 250 V/m AM = 80%,f = 1 kHz 1) According to 7637-1 the supply switched "OFF" for t = 200 ms 2) Testpulse 1 and 2 are carried out with capacitive coupling even if ISO 7637-3 Testpulse 1 and 2 is not requesting for capacitive coupling clamp 3) Second edition 2001-03-01 Data Sheet 25 Revision 1.2, May 2017 TLE4941plusC Confidential EMC Generator Specification Mainframe D1 TLE4941plusC VDD VEMC D2 C1 GND RM C2 Uout Components 1N4007 D1: 5Z27, 27V, 1J D2: 10F, 35V C1: C2: 1nF, 1000V 75, 5W RM : Figure 17 Data Sheet EMC Test Circuit 26 Revision 1.2, May 2017 TLE4941plusC Confidential 4 Package Information Package Information Pure tin covering (green lead plating) is used. Lead frame material is K62 (UNS: C18090) and contains CuSn1CrNiTi. Product is RoHS (restriction of hazardous substances) compliant when marked with letter G in front or after the data code marking and contains a data matrix code on the back side of the package (see also information note 136/03). Please refer to your key account team or regional sales if you need further information. d=0.30.08mm Distance chip to front side (date code) of IC Figure 18 Distance Chip to Upper Side of IC 4.1 Lead Pull Out Force The lead pull out force according IEC 60068-2-21 (fifth edition 1999-1) is 10N for each lead. Data Sheet 27 Revision 1.2, May 2017 TLE4941plusC Confidential Package Information 4.2 Packing and Package Dimensions of PG-SSO-2-53 Figure 19 Packing Dimensions in mm of PG-SSO-2-53 (Plastic Single Small Outline Package) Data Sheet 28 Revision 1.2, May 2017 TLE4941plusC Confidential Figure 20 Data Sheet Package Information Package Dimensions in mm of PG-SSO-2-53 (Plastic Single Small Outline Package) 29 Revision 1.2, May 2017 TLE4941plusC Confidential 4.3 Package Information Packing You can find all of our packages, type of packing and others in our Infineon Internet Page "Products": http://www.infineon.com/products . Data Sheet 30 Revision 1.2, May 2017 www.infineon.com Published by Infineon Technologies AG