Data Sheet
Revision 1.2
Advanced Diff. Speed Sensor
TLE4941plusC
Edition May 2017
Published by
Infineon Technologies AG
81726 München, Germany
© 2007 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
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information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
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For further information on technology, delivery terms and conditions and prices, please contact the nearest
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be endangered.
Data Sheet 3 Revision 1.2, May 2017
Confidential
TLE4941plusC
Revision History: May 2017, Revision 1.2
Previous Version: February 2011, Revision 1.1
Page Subjects (major changes since revision 1.0)
May 2017, Revision 1.2
28, 29 Updated package drawings
February 2011, Revision 1.1
13, 14 Footnote at “junction temperature” changed
Final Data Sheet Rev.1.0
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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Data Sheet 4 Revision 1.2, May 2017
Confidential
TLE4941plusC
Revision History, Revision 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Pin Configuration and sensitive area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Marking and data matrix code description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Magnetical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Description of Magnetic Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Typical Diagrams (measured performance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9 Electro Magnetic Compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1 Lead Pull Out Force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 Packing and Package Dimensions of PG-SSO-2-53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Product Name Product Type Ordering Code Packing
Advanced Diff. Speed Sensor TLE4941plusC SP000478508 PG-SSO-2-53
Data Sheet 5 Revision 1.2, May 2017
Advanced Differential Two-Wire Hall Effect Sensor IC
TLE4941plusC
Confidential
1 Product Description
1.1 Overview
The Hall Effect sensor IC TLE4941plusC is designed to provide
information about rotational speed to modern vehicle dynamics control
systems and Anti-Lock Braking Systems (ABS). The output has been
designed as a two wire current interface. The sensor operates without
external components and combines a fast power-up time with a low cut-
off frequency. Designed specifically to meet harsh automotive
requirements, excellent accuracy and sensitivity is specified over a wide
temperature range and robustness to ESD and EMC has been
maximized. State-of-the art BiCMOS technology is used for monolithic
integration of the active sensor areas and the signal conditioning circuitry.
Finally, the optimized piezo compensation and the integrated dynamic
offset compensation enables ease of manufacturing and the elimination of
magnetic offsets.
The TLE4941plusC is additionally provided with an overmolded 1.8 nF
capacitor for improved EMC performance.
1.2 Features
• Two-wire current interface
• Dynamic self-calibration principle
• Single chip solution
• No external components needed
• High sensitivity
• South and north pole pre-induction possible
• High resistive to piezo effects
• Large operating air-gaps
• Wide operating temperature range
• TLE4941plusC: 1.8 nF overmolded capacitor
• Applicable for small pitches (2mm Hall element distance)
Data Sheet 6 Revision 1.2, May 2017
Confidential
TLE4941plusC
Functional Description
2 Functional Description
2.1 General
The differential Hall sensor IC detects the motion of ferromagnetic and permanent magnet structures by
measuring the differential flux density of the magnetic field. To detect the motion of ferromagnetic objects the
magnetic field must be provided by a back biasing permanent magnet. Either south or north pole of the magnet
can be attached to the back side of the IC package.
Magnetic offsets of up to ± 30mT and device offsets are cancelled by a self-calibration algorithm. Only a few
magnetic edges are necessary for self-calibration. After the offset calibration sequence, switching occurs when
the input signal crosses the arithmetic mean of its max. and min. value (e.g. zero-crossing for sinusoidal signals).
The ON and OFF state of the IC are indicated by High and Low current consumption.
2.2 Pin Configuration and sensitive area description
Figure 1 Pin Description and sensitive area (view on front side marking of component)
Data Sheet 7 Revision 1.2, May 2017
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TLE4941plusC
Functional Description
2.3 Marking and data matrix code description
Figure 2 Front side and Backside Marking of PG-SSO-2-53
G: green package
YY: production year
WW: production week
123456:
41CPA ÆTLE4941plusC
GND
GND
V
DD
V
DD
Data Sheet 8 Revision 1.2, May 2017
Confidential
TLE4941plusC
Functional Description
2.4 Block Diagram
Figure 3 Block Diagram
The circuit is supplied internally by a 3V voltage regulator. An on-chip oscillator serves as clock generator for the
digital part of the circuit.
TLE4941plusC signal path is comprised of a Hall probe pair, spaced at 2.0 mm, a differential amplifier, including
a noise-limiting low-pass filter, and a comparator feeding a switched current output stage. In addition an offset
cancellation feedback loop is provided by a tracking AD-converter, a digital core and an offset cancellation D/A
converter.
The differential input signal is digitized in the tracking A/D converter and fed into the digital core. The minimum
and maximum values of the input signal are extracted and their corresponding arithmetic mean value is calculated.
The offset of this mean value is determined and fed back into the offset cancellation DAC.
In running mode (calibrated mode) the offset correction algorithm of the DSP is switched into a low-jitter mode,
avoiding oscillation of the offset DAC LSB. Switching occurs at zero-crossing. It is only affected by the (small)
remaining offset of the comparator and by the remaining propagation delay time. Signals below a defined
threshold ΔBLimit (see description Figure 8) are not detected to avoid unwanted parasitic switching.
2.4.1 Uncalibrated Mode
The short initial offset settling time td,input may delay the detection of the input signal (the sensor is not yet “awake“).
The magnetic input signal is tracked by the tracking ADC and monitored within the digital core. For detection the
signal transient needs to exceed a threshold DNC (digital noise constant d1). When the signal slope is identified
as a rising edge (or falling edge), a trigger pulse is issued to current modulator. A second trigger pulse is issued
as soon as a falling edge (or rising edge respectively) is detected (and vice versa).
Hall
Probes
ESD
hys.-ctrl
Fuses
PMU
Oscillator
Bandgap-
Biasing
Pre-
amplifier
GND
LP-
Filter
Tracking-
ADC
Tracking-ADC
Algorithm
Offset-DAC
Main-
Comparator
Current
Modulator
VDD
async logic
D-Core
Data Sheet 9 Revision 1.2, May 2017
Confidential
TLE4941plusC
Functional Description
The digital noise constant value changes (d1 → d2) with the magnetic field amplitude, leading to a phase shift
between the magnetic input signal and output signal. This value of the digital noise constant is determined by the
signal amplitude and initial offset value. The smallest DNC, indicated as d1 in figure 4, represents parameter
“dB_startup”. After calibration, consecutive output edges should have a nominal delay of about 180°.
Figure 4 Example for Start-up Behavior
dB
t
1
dB
max
dB
Start
d
1
d
2
= (dB
max
–dB
Start
)/4
dB
min
Phase shift change
Uncalibrated Mode Calibrated Mode
d
1
=dB
startup
t
1
=initial calibration delay time
Offset correction=(dBmax +dBmin)/2
Offset-
correction
d
3
= (dB
max
–dB
min
)/4
Data Sheet 10 Revision 1.2, May 2017
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TLE4941plusC
Functional Description
2.4.2 Transition to Calibrated Mode
In the calibrated mode the output will switch at zero-crossing of the input signal. The phase shift between input
and output signal is no longer determined by the ratio between digital noise constant and signal amplitude.
Therefore a sudden change in the phase shift may occur during the transition from uncalibrated to calibrated
mode.
2.4.3 Additional Notes
The summed up change in phase shift from the first output edge issued to the output edges in calibrated mode
will not exceed ± 90°.
2.4.4 Output Description
Under ideal conditions, the output shows a duty cycle of 50%. Under real conditions, the duty cycle is determined
by the mechanical dimensions of the target wheel and its tolerances (40% to 60% might be exceeded for pitch >>
4mm due to the zero-crossing principle).
Figure 5 Speed Signal (half a period = 0.5 x 1/fspeed)
Data Sheet 11 Revision 1.2, May 2017
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TLE4941plusC
Functional Description
Figure 6 Definition of Rise and Fall Time; Duty Cycle = t1/T x 100%
2.4.5 Behavior at Magnetic Input Signals Slower than fmag < 1Hz
Magnetic changes exceeding Δˆ
Bstartup can cause output switching of the TLE4941plusC, even at fmag significantly
lower than 1 Hz. Depending on their amplitude edges slower than Δtstartup might be detected. If the digital noise
constant (Δˆ
Bstartup) is not exceeded before Δtstartup a new initial self-calibration is started. In other words Δˆ
Bstartup
needs to be exceeded before Δtstartup. Output switching strongly depends on signal amplitude and initial phase.
Data Sheet 12 Revision 1.2, May 2017
Confidential
TLE4941plusC
Functional Description
2.4.6 Undervoltage Behavior
The voltage supply comparator has an integrated hysteresis Vhys with the maximum value of the release level Vrel
< 4.5V. This determines the minimum required supply voltage VDD of the chip. A minimum hysteresis Vhys of 0.7V
is implemented thus avoiding a toggling of the output when the supply voltage VDD is modulated due to the
additional voltage drop at RM when switching from low to high current level and VDD = 4.5V (designed for use with
RM==75Ω).
Figure 7 Start-up and undervoltage behavior
V
DD
*
*direct on pins
V
rel
V
res
V
hys
= V
rel
-V
res
V
hys
I
low
I
high
Data Sheet 13 Revision 1.2, May 2017
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TLE4941plusC
Specification
3 Specification
3.1 Absolute Maximum Ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
Table 1 Absolute Maximum Ratings
Tj = – 40°C to 150°C, 4.5 V ≤ VDD ≤ 20 V if not indicated otherwise
Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage VDD -0.3 – V Tj < 80°C
–20 Tj = 150°C
–22 t = 10 × 5 min.
–24 t = 10 × 5 min.
RM ≥ 75 Ω included in VDD
–27 t = 400 ms, RM ≥ 75 Ω
included in VDD
Reverse polarity voltage Urev -22 V RM ≥ 75 Ω included in VDD,
t<1 h
Reverse polarity current Irev – 200 mA External current limitation
required, t<4 h
300 mA External current limitation
required, t<1 h
Junction temperature1)
1) This lifetime statement is an anticipation based on an extrapolation of Infineon’s qualification test results. The actual lifetime
of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime
statement shall in no event extend the agreed warranty period.
Tj
EITHER -40 125 10.000h
OR 150 5000 h
OR 160 2500 h,
OR 170 500 h
Additional 190 4 h, VDD < 16.5 V
Number of power on cycles 500.000 times
Immunity to external fields 1 Tesla is equivalent to 800kA/m;
Tj=-40..175°C2)
2) Conversion: B=μ0*H (μ0=4*π*10-7);
Thermal resistance
PG-SSO-2-53
RthJA – 190 K/W 3)
3) Can be significantly improved by further processing like overmolding
Data Sheet 14 Revision 1.2, May 2017
Confidential
TLE4941plusC
Specification
3.1.1 ESD Robustness
or >8000V for TLE4941plusC (H3B according AEC Q100)
Note: Tested at room temperature
3.2 Operating Range
Table 2 ESD Protection
Characterized according to Human Body Model (HBM) tests in compliance with Standard
EIA/JESD22-A114-B HBM (covers MIL STD 883D)
Parameter Symbol Test Result Unit Notes
ESD-Protection VESD ±12 kV R = 1.5 k
Ω
,
C = 100 pF
Table 3 Operating Range
Parameter Symbol Limit Values Unit Remarks
min. max.
Supply voltage VDD
Extended
Range
4.5
20
20
241)
1) Extended range of 20..24V is not recommended. Latch-up test with factor 1.5 is not covered. Please see max ratings also.
V Directly on IC leads;
includes not the
voltage drop at RM
Supply voltage modulation VAC –6VppVDD = 13 V
0 < fmod < 150 kHz2)
2) sin wave
Junction temperature3)
3) This lifetime statement is an anticipation based on an extrapolation of Infineon’s qualification test results. The actual lifetime
of a component depends on its form of application and type of use etc. and may deviate from such statement. The lifetime
statement shall in no event extend the agreed warranty period.
Tj°C
EITHER -40 125 10.000h
OR 150 5000 h
OR 160 2500 h
OR 170 500 h
Pre-induction B0-500 +500 mT
Pre-induction offset between
outer probes
Δ
Bstat., l/r -30 +30 mT
Differential Induction ΔB-120 +120 mT
Magnetic signal frequency fmag 1 10000 Hz
Data Sheet 15 Revision 1.2, May 2017
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TLE4941plusC
Specification
3.3 Electrical Characteristics
Table 4 1)All values specified at constant amplitude and offset of input signal, over operating range,
unless otherwise specified. Typical values correspond to VDD = 12 V and TA= 25°C
Parameter Symbol Limit Values Unit Remarks
min. typ. max.
Supply current ILow 5.9 7 8.4 mA
Supply current IHigh 11.8 14 16.8 mA
Supply current ratio IHigh / ILow 1.9 2.1 2.3
Output rise/fall slew rate
TLE4941plusC
tr, tf
8
8
–
–
22
26
mA/µs
RM = 75 Ω +/-5%
Tj < 125°C
Tj < 170°C
See Figure 6
Line regulation dIx/dVDD 90 µA/V quasi static7)
Initial calibration
delay time
td,input – 120 300 µs Additional to nstart2)7)
Power up time 100 us 3)7)
Magnetic edges required for
offset calibration
nstart – - 4 magn.
edges
5th edge correct 4)7)
Number of edges in uncalibrated
mode
nDZ-Startup – – 4 edges 7)
Number of edges suppressed 0 after power on or
reset
Magnetic edges required for first
output pulse
1 2 after power on or
reset
Duty cycle DC 40 50 60 % @ΔB ≥2 mT sine
wave see Figure 6 5)
Signal frequency f1
2500
–
–
2500
10000
Hz 6)
Jitter, Tj < 150°C
Tj < 170°C
1 Hz < fmag < 2500 Hz
SJit-close –
–
–
–
± 2
± 3
%1σ value
VDD = 12 V
ΔB ≥ 2 mT 7)
Jitter, Tj < 150°C
Tj < 170°C
2500 Hz < fmag < 10000 Hz
SJit-close –
–
–
–
± 3
± 4.5
%1σ value
VDD = 12 V
ΔB ≥ 2 mT 7)
Jitter, Tj < 150°C
Tj < 170°C
1 Hz < fmag < 2500 Hz
SJit-far –
–
–
–
± 4
± 6
%1σ value
VDD = 12 V
2mT≥Δ
B>ΔBLimit 7)
Jitter, Tj < 150°C
Tj < 170°C
2500 Hz < fmag < 10000 Hz
SJit-far –
–
–
–
± 6
± 9
%1σ value
VDD = 12 V
2mT≥Δ
B>ΔBLimit 7)
Jitter at board net ripple
fmag<10kHz
SJit-AC ± 0.5 %
V
DD
=13V±6V
pp
0 < fmod < 150 kHz
ΔB = 15 mT
7)
8)
Permitted time for edge to exceed
Δˆ
Bstartup
Δtstartup ––590ms 7)
Time before chip reset9) ΔtReset 590–848ms 7)
Data Sheet 16 Revision 1.2, May 2017
Confidential
TLE4941plusC
Specification
Signal behavior after
undervoltage or standstill > tReset
Number of magnetic edges where
the first switching occur
nDZ-Start 1 – 2 edge Magnetic edge
amplitude according
to Δˆ
Bstartup.
td,input has to be taken
into account7)10)
Systematic phase error of output
edges during start-up and
uncalibrated mode
-90 – +90 °
Systematical phase
error of “uncal”
edge;
n
th
vs. n + 1
th
edge
(does not include
random phase
error)7)
Phase shift change during
transition from uncalibrated to
calibrated mode
ΔΦswitch
-45
-90
–+45
+90
°7)
dBpp>4*dBstartup
dBpp<4*dBstartup
1) All parameters refer to described test circuit in this document. See chapter 3.6 test circuit
2) Occurrence of “Initial calibration delay time td,input “
If there is no input signal (standstill), a new initial calibration is triggered each ΔtReset. This calibration has a duration td,input
of max. 300 µs. No input signal change is detected during that initial calibration time. In normal operation (signal startup)
the probability of td,input to come into effect is: td,input / time frame for new calibration 300 µs/700 ms = 0.05%. After IC resets
(e.g. after a significant undervoltage) td,input will always come into effect.
3) VDD>=4.5V
4) One magnetic edge is defined as a monotonic signal change of more than 3.3 mT
5) During fast offset alterations, due to the calibration algorithm, exceeding the specified duty cycle is permitted for short time
periods
6) Frequency behavior not subject to production test - verified by design/characterization. Frequency above 2500 Hz may
have influence on jitter performance and magnetic thresholds.
7) Not subject to production test, verified by design/characterization
8) Disturbances are sine-wave shaped: 1sigma value
9) When no output switching occurs for t > ΔtReset the sensor is internally reset after each ΔtReset time frame. See also chapter
“2.4.5 Behavior at Magnetic Input Signals Slower than fmag < 1Hz”
10) A loss of edges may occur at high frequencies
Table 4 1)All values specified at constant amplitude and offset of input signal, over operating range,
unless otherwise specified. Typical values correspond to VDD = 12 V and TA= 25°C
Parameter Symbol Limit Values Unit Remarks
min. typ. max.
Data Sheet 17 Revision 1.2, May 2017
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TLE4941plusC
Specification
3.4 Magnetic Characteristics
Table 5 1)All values specified at constant amplitude and offset of input signal, over operating range,
unless otherwise specified. Typical values correspond to VDD = 12 V and TA= 25°C
1) All parameters refer to described test circuit in this document. See chapter 3.6 test circuit.
Parameter Symbol Limit Values Unit Remarks
min. typ. max.
Limit threshold
1 Hz < fmag < 2500 Hz
2500 Hz < fmag < 10000 Hz
ΔBLimit
0.35 0.7
–
1.5
1.7
mT 2) 3)
2) Magnetic amplitude values, sine magnetic field, limits refer to the 50% criteria. 50% of edges are missing
3) ΔBLimit is calculated out of measured sensitivity
Magnetic differential field change
necessary for startup
Δˆ
Bstartup – – – Magnetic field
change for startup
with the first edge
(see “Uncalibrated
Mode” on 2.4.1)
1 Hz < f < 2500 Hz
2500 Hz < f < 10000 Hz
0.7
–
1.4
–
3.3
3.9
mT
Data Sheet 18 Revision 1.2, May 2017
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TLE4941plusC
Specification
3.5 Description of Magnetic Field
Figure 8 Description of differential field dB and switching threshold dBlimit (calibrated mode)
Note: dB is the resulting signal of difference between signal of right and left Hall element (right - left).
dB = B2 (right) - B1 (left)
dB_limit
dB_limit
14mA
7mA
dB
Data Sheet 19 Revision 1.2, May 2017
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TLE4941plusC
Specification
Figure 9 Definition of field direction and sensor switching
Note: "If a positive field is applied to the right Hall probe (located over GND pin) and a negative field (or a weaker
field) is applied to the left Hall probe, the resulting output current state is high
North
South
right
left
Hall
Elements
Branded Side
(front side)
Sensor Top View
Definition of magnetic field for this example
Positive is considered when
South pole shows to rear side of IC housing or when
North pole shows to front side (=branded) of IC housing
(Gaussmeter: positive at north pole. Dot towards viewer)
Left
(V
DD
)
Right
(GND)
Top View
7
I / [mA]
14
B / [mT]
Right Hall Element
Left Hall Element
Gyyww i
41CPA
Data Sheet 20 Revision 1.2, May 2017
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TLE4941plusC
Specification
3.6 Test Circuit
Figure 10 Test Circuit for TLE4941plusC
Integrated cap on leads
V
DD
GND
75ohm
Vout
TLE4941+C
V
DD
Gyyww i
41CPA
Integrated cap on leads
V
DD
GND
75ohm
Vout
TLE4941+C
V
DD
Gyyww i
41CPA
Data Sheet 21 Revision 1.2, May 2017
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TLE4941plusC
Specification
3.7 Application Circuit
Circuit below shows the recommended application circuit with reverse bias and overvoltage protection.
Figure 11 Application Circuit
An implementation of 10Ω in VDD path reduces minimum power supply direct on leads of the sensor, but
decreases max current at D2 and makes PCB more robust. This PCB represents a compromise of minimum power
supply and current flow on D2. With higher values than 10Ω a higher minimum supply voltage and higher
robustness is reached.
D
1
R
1
D
2
C
1
VDD
GND
TLE4941plusC
R
M
V
S
U
out
Components
D1:1N4007
D2: Z-Diode, 27V
C1:10µF, 35V
R1:10Ω
RM:75Ω
Data Sheet 22 Revision 1.2, May 2017
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TLE4941plusC
Specification
3.8 Typical Diagrams (measured performance)
Note: Temperatures above 170°C are not guaranteed by this data sheet even if shown below
Figure 12 Supply Current = f(T) (left), Supply Current Ratio Ihigh / I Low= f(T) (right)
Figure 13 Supply Current =f(VDD) (left), Supply Current Ratio Ihigh / I Low=f(VDD) (right)
6
8
10
12
14
16
18
-40 0 40 80 120 160 200
T
j
[°C]
I
Low
, I
High
[mA]
1,8
1,9
2
2,1
2,2
2,3
2,4
-40 0 40 80 120 160 200
T
j
[°C]
I
High
/ I
Low
6
8
10
12
14
16
18
0 5 10 15 20 25 30
V
DD
[V]
I
Low
, I
High
[mA]
1,9
2
2,1
2,2
2,3
0 5 10 15 20 25 30
V
DD
[V]
I
High
/ I
Low
Data Sheet 23 Revision 1.2, May 2017
Confidential
TLE4941plusC
Specification
Figure 14 Slew Rate = f(T) , RM= 75 Ω (left), Slew Rate = f(RM) (right)
Figure 15 Magnetic Threshold ΔBLimit = f(T) at f = 200Hz (left), Magnetic Threshold ΔBLimit = f(f) (right)
8
10
12
14
16
18
20
22
24
26
-40 0 40 80 120 160 200
T
j
[°C]
Slewrate [mA/µs]
0
2
4
6
8
10
12
14
16
18
20
22
24
26
0 200 400 600 800 1000
Slewrate [mA/µs]
Rm [Ω]
0,3
0,5
0,7
0,9
1,1
1,3
1,5
-40 0 40 80 120 160 200
T
j
[°C]
dB
limit
[mT]
0,3
0,5
0,7
0,9
1,1
1,3
1,5
1 10 100 1000 10000
f [Hz]
dB
limit
[mT]
Data Sheet 24 Revision 1.2, May 2017
Confidential
TLE4941plusC
Specification
Figure 16 Jitter 1σ at ΔB = 2 mT at 1 kHz (left), Duty Cycle [%] ΔB=2mT at 1kHz (right)
0,0
0,5
1,0
1,5
2,0
-40 0 40 80 120 160 200
T
j
[°C]
Jitter [%]
40
45
50
55
60
-40 0 40 80 120 160 200
T
j
[°C]
Duty Cycle [%]
Data Sheet 25 Revision 1.2, May 2017
Confidential
TLE4941plusC
Specification
3.9 Electro Magnetic Compatibility (EMC)
Additional Information:
Characterization of Electro Magnetic Compatibility are carried out on sample base of one qualification lot. Not all
specification parameters have been monitored during EMC exposure. Only key parameters e.g. switching current
and duty cycle have been monitored.
Corresponds to Test Circuit of TLE4941/TLE4941C
Table 6 Electro Magnetic Compatibility (values depend on RM!)
Ref. ISO 7637-1; 2000; EMC test circuit (figure 17)
ΔB = 2 mT (amplitude of sinus signal); VDD = 13.5 V; fB = 100 Hz; T = 25°C, RM ≥ 75 Ω
Parameter Symbol Level/Typ Status
Testpulse 1
Testpulse 21)
Testpulse 3a
Testpulse 3b
Testpulse 4
Testpulse 5
1) According to 7637-1 the supply switched “OFF” for t = 200 ms
VEMC IV / -100 V
IV / 100 V
IV / -150 V
IV / 100 V
IV / -7 V
IV / 86.5 V
C
C
A
A
B
C
According to 7637-1 for test pulse 4 the test voltage shall be 12 V ± 0.2 V. Measured with RM = 75 Ω only. Mainly the current
consumption will decrease. Status C with test circuit 1.
Ref. ISO 7637-3 Release 1995 2); EMC test circuit (figure 17)
ΔB = 2 mT (amplitude of sinus signal); VDD = 13.5 V; fB = 100 Hz; T = 25°C; RM ≥ 75 Ω
2) Testpulse 1 and 2 are carried out with capacitive coupling even if ISO 7637-3 Testpulse 1 and 2 is not requesting for
capacitive coupling clamp
Parameter Symbol Level/Typ Status
Testpulse 1
Testpulse 2
Testpulse 3a
Testpulse 3b
VEMC IV / -30 V
IV / 30 V
IV / -60 V
IV / 40 V
A
A
A
A
Ref. ISO 11452-33); EMC test circuit (figure 17), measured in TEM-cell
ΔB = 2 mT; VDD = 13.5 V, fB = 100 Hz; T = 25°C
3) Second edition 2001-03-01
Parameter Symbol Level/Typ Remarks
EMC field strength ETEM-Cell IV / 250 V/m AM = 80%,f = 1 kHz
Data Sheet 26 Revision 1.2, May 2017
Confidential
TLE4941plusC
Specification
Figure 17 EMC Test Circuit
D
1
D
2
C
1
V
DD
GND
TLE4941plusC
R
M
U
out
Components
D
1
: 1N4007
D
2
: 5Z27, 27V, 1J
C
1
: 10µF, 35V
C
2
: 1nF, 1000V
R
M
:75Ω, 5W
V
EMC
EMC Generator Mainframe
C
2
Data Sheet 27 Revision 1.2, May 2017
Confidential
TLE4941plusC
Package Information
4 Package Information
Pure tin covering (green lead plating) is used. Lead frame material is K62 (UNS: C18090) and contains
CuSn1CrNiTi. Product is RoHS (restriction of hazardous substances) compliant when marked with letter G in front
or after the data code marking and contains a data matrix code on the back side of the package (see also
information note 136/03). Please refer to your key account team or regional sales if you need further information.
Figure 18 Distance Chip to Upper Side of IC
4.1 Lead Pull Out Force
The lead pull out force according IEC 60068-2-21 (fifth edition 1999-1) is 10N for each lead.
d=0.3±0.08mm
Distance chip to front side
(date code) of IC
Data Sheet 28 Revision 1.2, May 2017
Confidential
TLE4941plusC
Package Information
4.2 Packing and Package Dimensions of PG-SSO-2-53
Figure 19 Packing Dimensions in mm of PG-SSO-2-53 (Plastic Single Small Outline Package)
Data Sheet 29 Revision 1.2, May 2017
Confidential
TLE4941plusC
Package Information
Figure 20 Package Dimensions in mm of PG-SSO-2-53 (Plastic Single Small Outline Package)
Data Sheet 30 Revision 1.2, May 2017
Confidential
TLE4941plusC
Package Information
4.3 Packing
You can find all of our packages, type of packing and others in our Infineon Internet Page
“Products”: http://www.infineon.com/products
.
Published by Infineon Technologies AG
www.infineon.com