Lead (Pb) Free Product - RoHS Compliant
Red PDSP1880
Yellow PDSP1881
High Efficiency Red PDSP1882
Green PDSP1883
High Efficiency Green PDSP1884
4.70 mm (0.180’’) 8-Character 5x7 Dot Matrix
Alphanumeric Programmable Display™
2006-03-30 1
DESCRIPTION
The PDSP1880 (Red), PDSP1881 (Yellow), PDSP1882
(High Efficiency Red), PDSP1883 (Green), and
PDSP1884 (High Efficiency Green) are eight digit,
5 x 7 dot matrix, alphanumeric Programmable Displays.
The 4.70 mm (0.180’’) high digits are packaged in a rug-
ged, high quality, optically transparent, 7.62 mm (0.300’’)
lead spacing, 30 pin plastic DIP.
The on-board CMOS has a built-in 128 character ROM.
The PDSP188X also has a user definable character
(UDC) fea ture, which uses a RAM that permits storage of
16 arbitrary characters, symbols or icons that are soft-
ware-defi nable b y the user. The character ROM itself is
mask programmab le and easily modified by the man uf a c-
turer to provide specif ied custom characters.
The PDSP188X is design ed f or standard micro processor
interf ace techniques, and is fully TTL compatible. The
Clock I/O and Clock Select pins allow the user to cas-
cade multiple display modules.
ESD Warning: Standard precautions for
CMOS handling should be
observed.
FEATURES
• Eight 4.70 mm (0.180") Dot Matrix Characters in Red,
Yellow, High Efficiency Red, Green, or
High Efficiency Green
• Built-in 128 Chara cter ROM,
Mask Programmable for Custom Fonts
• Readab le from 2.5 meters (8 Feet)
• Built-in Decoders, Multiplexers and Drivers
• Wide Viewing Angle, X Axis ± 55°, Y Axis 65°
• Programmable Features:
– Individual Flashing Character
– Full Display Blinking
– Multi-Level Dimming and Blanking
– Clear Function
– Self Test
• Internal or External Clock
• End Stackable Dual-In-Line Plastic Package
• Read/Write Capability
• 16 User D efinable Characters
2006-03-30 2
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Package Outlines Dimensions in mm (inch)
Ordering Information
Type Color of Emission Character Height
mm (inch) Ordering Code
PDSP1880 red
4.70 (0.180)
Q68000A9105
PDSP1881 yellow Q68000A9106
PDSP1882 high efficiency red Q68000A9107
PDSP1883 green Q68000A9108
PDSP1884 high efficiency green Q68000A9109
IDOD5014
0213
5467
2.54 (0.100)
L
11.43 (0.450) max.
C
2.68 (0.105)
C
L
5.36 (0.211)
42.93 (1.690) max.
4.57 (0.180)
2.29 (0.090)
Identifier
Pin 1
4.01 (0.158) typ.
Pin 15
0.25 (0.010)
5.71 (0.225)
0.3 (0.012) typ.
5.33 (0.210)
7.62 (0.300)
1.52 (0.060) ref.
(Tol. non cum.)
±0.13 (0.005)
2.54 (0.100) typ.
Identifier
0.51 (0.020)
Pin 1
5.08 (0.200)
10.16 (0.400)
C
L
0.46 (0.018) typ.
Pin 15
L
C
Pin 16
Date Code
YYWW
OSRAM
PDSP188X Z
LI Code
V
Indicator
Pin 1
Color Code
Y
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 3
Maximum Ratings (TA=25°C)
Parameter Symbol Value Unit
Operating temperatur e range Top – 40 … + 85 °C
Storage temperature range Tstg – 55 … + 100 °C
DC Supply Voltage, VCC to GND
(max. voltage with no LEDs on) VCC -0.3 to + 7.0 V
Operating Voltage, VCC to GND
(max. voltage with 20 dots/digits on) 5.5 V
Input Voltage Levels,
all inputs -0.3 to VCC + 0.3 V
Solder Temperature
1.59 mm (0.063“) below seating plane, t < 5.0 s TS260 °C
Relative Humidity (non-condensing) 85 %
ESD (100 pF, 1.5 kΩ)
(each pin) VZ4.0 kV
Optical Characteristics at 25°C
(VCC=5.0 V at 100% brightness level)
Description Symbol Values Unit
Red
PDSP1880
Yellow
PDSP1881
High Efficiency Red
PDSP1882
Green
PDSP1883
High Efficiency Green
PDSP1884
Peak Luminous Intensity (min.)
(typ.) IVpeak 70
125 125
205 125
350 125
275 125
500 µcd/dot
µcd/dot
Peak Wavelength (typ.) λpeak 660 583 630 565 568 nm
Dominant Wavelength (typ.) λdom 639 585 626 570 574 nm
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 4
Enlarged Character Format Dimensions in mm (inch)
Write Cycle Timing Diagram
IDOD5015
C3C0 C1 C2 C4
2.49 (0.098)
0.254 (0.010) typ. 0.71 (0.028) typ.
0.56 (0.022) typ.
R7
4.52 (0.178)
R4
R6
R5
R1
R2
R3
Switching Specifications
(over operating temperature range and VCC=4.5 V)
Symbol Description Min. Units
Tacc Display Access Time—Write 210 ns
Tacc Display Access Time—Read 230 ns
Tacs Address Setup Time to CE 10 ns
Tce Chip Enable Active Time—Write 140 ns
Tce Chip Enable Active Time—Read 160 ns
Tach Address Hold Time to CE 20 ns
Tcer Chip Enable Recovery Time 60 ns
Tces Chip Enable Active Prior to
Rising Edge—Write 140 ns
Tces Chip Enable Active Prior to
Rising Edge—Read 160 ns
Tceh Chip Enable Hold to Rising Edge
of Read/Write Signal 0ns
TwWrite Active Time 100 ns
Twd Data Valid Prior to
Rising Edge of Write Signal 50 ns
Tdh Data Write Time 20 ns
TrChip Enable Active Prior to Valid
Data 160 ns
Trd Read Active Prior to Valid Data 95 ns
Tdf Read Data Float Delay 10 ns
Trc Reset Active Time 300 ns
Tacc
Twd Tdh
Tw
Tces
Tcer
Tceh
Tacs Tach Tacs
A0-A3
FL
Tce
CE
WR
D0-D7
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 5
Read Cycle Timing Diagram
Character Set
Notes:
1. Upon power up, the device will initialize in a random state.
2. X=don’t care.
Tacc
Trd Tdf
TrTces
Tcer
Tceh
Tacs Tach Tacs
A0-A3
FL
Tce
CE
RD
D0-D7
IDCS5086
ASCII
CODE
D0
D1
D2
D3
HEX
D4D5D7
LLL
0
1
HLL
2
LHL
3
LHH
4
LLL
5
LLH
6
LHL
7
LHH
L
L
L
L
01
L
L
H
L
2
L
L
L
H
3
L
L
H
H
4
L
H
L
L
5
L
H
H
L
6
L
H
L
H
7
L
H
H
H
8
H
L
L
L
9
H
L
H
L
A
H
L
L
H
B
H
L
H
H
C
H
H
L
L
D
H
H
H
L
E
H
H
L
H
F
H
H
H
H
D6
L
L
L
L
H
H
H
H
HXXX
8UDC
0UDC
1UDC
2UDC
3UDC
4UDC
5UDC
6UDC
7UDC
8UDC
9UDC
10 UDC
11 UDC
12 UDC
14 UDC
1513
UDC
2006-03-30 6
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
DC Electrical Characteristics at 25°C
Parameters Limits Conditions
Min. Typ. Max. Units
VCC 4.5 5.0 5.5 V —
ICC Blank —0.65 1.0 mA VCC=5.0 V, VIN=5.0 V
ICC 12 dots/digit on1) 2) —200 255 mA VCC=5.0 V, “V” in all 8 digits
ICC 20 dots/digit on1) 2) —300 370 mA VCC=5.0 V, “#” in all 8 digits
IILP (with pull-up)
Input Leakage –18 –11 –5.0 µAVCC=5.0 V, VIN=0 V to VCC
(WR, CE, FL, RST, RD, CLKSEL)
IIL (no pull-up)
Input Leakage –1.0 —+1.0 µAVCC=5.0 V, VIN=5.0 V
(CLK, A0–A3, D0–D7)
VIH Input Voltage High 2.0 —VCC
+0.3 VVCC=4.5 V to 5.5 V
VIL Input Voltage Low GND
–0.3 — — V VCC=4.5 V to 5.5 V
VOL (D0–D7), Output Voltage Low — — 0.4 VVCC=4.5 V, IOL=1.6 mA
VOL (CLK), Output Voltage Low — — 0.4 VVCC=4.5 V, IOL=40 µA
VOH Output Voltage High 2.4 — — V VCC=4.5 V, IOH=40 µA
θJC Thermal Resistance,
Junction to Case —25 —°C/W —
Clock I/O Frequency 28 57.34 81.14 kHz VCC=4.5 to 5.5 V
FM, Digit Multiplex Frequency 125 256 362.5 Hz VCC=4.5 to 5.5 V
Blinking Rate 0.98 2.0 2.83 Hz —
Clock I/O Buss Loading — — 2.40 pF —
Clock Out Rise Time — — 500 nsec VCC=4.5 V, VOH=2.4 V
Clock Out Fall Time — — 500 nsec VCC=4.5 V, VOH=0.4 V
Notes:
1)ICC is an average value.
2)ICC is measured with the display at full brightness. Peak ICC= 28/15 ICC average (#displayed).
Recommended Operating Conditions (TA = – 40°C to + 85°C)
Parameter Symbol Min. Max. Units
Supply Voltage VCC 4.5 5.5 V
Input Voltage Low VIL —0.8 V
Input Voltage High VIH 2.0 — V
Output Voltage Low VOL —0.4 V
Output Voltage High VOH 2.4 — V
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 7
Top View
Cascading Displays
The PDSP188X is designed to drive up to 16 other
PDSP188Xs with input loading of 15 pF each.
General requirements for cascadi ng 16 di sp l ays
together:
• Determine the correct address for each display.
• Use CE from an address decoder to select the correct
display.
• Use CE from an address decoder to select the correct
display.
• Select one of the Displays to provid e the Clock for the
other displays. Connect CLKSEL to VCC for this dis-
play.
• Tie CLKSEL to ground on other displays.
• Use RST to synchronize the blinking betw een the dis-
plays.
Pin Assignments
Pin # Name Symbol Definition
1Reset RST Initializes display; clears Character
RAM (20H), Flash RAM (00H),
control word (00H), an d resets
internal counters. UDC Address
Register and UDC RAM
unaffected.
2Flash FL Accesses Flash RAM. Address
inputs A0–A2 select digit address
while data bit D0 sets (D0=1) or
resets (D0=0) Flash bit, A3 and A4
ignored.
3Address
input A0 A0–A2 select specific digits.
See Table „Memory Sel ection“
(page 9).
4A1 Same as A0
5A2 Same as A0
6Address
input A3 A3 and A4 access parts of memory
together with Flash pin. See Table
1.
7–9 No pins —No connections
10 Address
input A4 Same as A3
11 Clock
Select CLS Selects internal or external clock
source. CLS=1 selects internal
clock (master), CLS=0 selects
external clock (slave operation).
12 Clock
In/Out CLK Inputs or outputs clock as
determined by CLS.
13 Write WR Writes data into display when
WR=0. Note CE=0 to enabl e w rite
cycle.
14 Chip
Enable CE Enables display’s write and read
cycles when CE=0.
15 Positive
supply VCC Positive power supply input.
IDPA5110
0123
4567
16 Supply
ground GNDsup Analog ground for LED drivers
17 —NC No connection
18 Logic
ground GNDlog Logic ground for digital
circuitry
19 Read RD Reads data from display when
RD=0. Also CE=0.
20 Data bit
zero D0 Least significant data bit.
21 Data bit
one D1 Second data bit.
22–24 No pins —No connections
25 Data bit
two D2 Third data bit.
26 Data bit
three D3 Fourth data bit.
27 Data bit
four D4 Fifth data bit.
28 Data bit
five D5 Sixth data bit.
29 Data bit
six D6 Seventh data bit.
30 Data bit
seven D7 Most significant data bit.
Pin Assignments
Pin # Name Symbol Definition
2006-03-30 8
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Cascading Diagram
Block Diagram
IDCD5031
RD WR FL CLK CLK
Display
CC
V
D0-D7 A0-A4 CE
Up to 14 more
displays in between
I/O SEL
CE
Display
D0-D7 A0-A4
Data I/O
Address
Decoder
Address Address Decode Chip 1 to 14
A6
A7
A9
WR
FL
RST
RST
0
15
RD
RSTRD WR FL CLK
SEL
CLK
I/O
A8
IDBD5064
OSC
32
Counter Counter
7
8 Digit Display
Drivers
Counter
128
Counter
3
Decode
RAM
Character
Character
RAM
D Latch
Holding
Register Decode
Word
ROM
for Display
Decode
Character
(Read/Write)
Character
Decode
Register
Address
UDC
Bus
Row
ROM
4
64
4RAM
16
16 UDC
Column
Latch
Master
Slave
5 25
5
and
Controls
Cursor
Display
MUX
25
Word
Register
Control
Test
Self Flash
RAM
Drivers
Column
Data
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 9
Functional Description
The displa y's user inte rface is orga ni zed into fiv e memory areas.
They are accessed using the Flash Input, FL , and address lines,
A3 and A4. All the listed RAMs and Registers may be read or writ-
ten through the d ata bus. Se e Table „Mem ory Selection“ ( page 9).
Each input pin is described in Pin Definitions.
RST can be used to initialize display operation upon power up or
during normal operation. Whe n acti vated, RST will clear the Flash
RAM and Control Word Register (00H) and reset the internal
counter. All eight display memory locations will be set to 20H to
show blanks in all digits.
FL pin enables access to the Flash RAM. The Flas h RA M will set
(D0=1) or reset (D0=0) flashing of the character addressed by A0–
A2.
The 1 x 8 bit Control Wor d Register is loaded with attribute data if
A3=0.
The Control Word Logic decodes attribute data for proper imple-
mentation.
Character ROM is designed for 128 ASCII characters. The ROM
is Mask Programma ble for custom fonts.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an e xte rnal clock (CLKSEL=0) could
be an input from another HDSP211X display for synchronizing
blinking for multiple displays.
The Di splay Multi plexer controls the Row Drivers so no additional
logic is required for a display system.
The Display has eight digit s. Each digit has 35 LEDs.
Theory of O p er ation
The PDSP188X Display is designed to work with all major micro-
processors. Data entry is via an eight bit parallel bus. Three bits of
address route the data to the proper digit location in the RAM.
Standard control signals like WR and CE allow the data to be writ-
ten into the display.
D0–D7 data bits are used for both Character RAM and control
word data input. A3 acts as the mode selector. If A3=1, character
RAM is selected. Then input data bit D7 will determine whether
input data bits D0–D6 is ASCII coded data (D7=0) or UDC data
(D7=1). See section on „UDC Address Register and UDC RAM“
(page 10).
For normal op eration FL pin should be held high. When FL is held
low, Fl a sh RA M is accessed to set character b l i nkin g.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each displa y cycle, and it takes f ourteen display cy cles to write into
eight digits.
The rows are multipl exed in two sets of seven rows each. The
internal timing and control logic synchronizes the turning on of
rows and presentation of column data to assure proper display
operation.
Power Up Sequence
Upon power up the d ispl ay will come on at random . Th us the di s -
play should be reset on power-up. Reset will clear the Flash
RAM, Control Word Register and reset the internal counter. All
the digits will show blanks and display brightness level will be
100%.
The display m ust not be accessed unt il three clo ck pulses (110 µs
minimum u sing t he in ternal clock) after th e rising ed ge of t he re set
line.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data bus
(D0–D7), the 4-bit address bus (A0–A3) and control lines FL , CE
and WR.
To write data (ASCII/ Co ntr o l Word ) i nt o th e di sp l ay CE should be
held low, address and data signals stable and WR should be
brought low. The data is written on the low to high transition of
WR.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a d iff erent functi on. The code f or displa y brightness
changes the duty cycle for the column drivers. The peak LED cur-
rent stays the same but the average LED current diminishes
depending on the intensity level.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with the column drive signal to make the col-
umn driver cycle at 2.0 Hz. Thus the char acte r flash es at 2.0 Hz.
Five Basic Memory Areas
Character RAM Stores either ASCII (Katakana)
character data or an UDC RAM
address
Flash RAM 1 x 8 RAM which stores Flash data
User-Defined
Character RAM
(UDC RAM)
Stores dot pattern for custom
characters
User-Defined Address
Register (UDC Address
Register)
Provides address to UDC RAM
when user is writing or reading
custom character
Control Word
Register Enables adjustment of display
brightnes s, flash indivi dual
characters, blink, self test or clearing
the display
Memory Selection
FL A4 A3 Section of Memory A2–A0 Data Bits Used
0XX Flash RAM Character Address D0
100 UDC Address Register Don’t Care D3–D0
101 UDC RAM Row Address D4–D0
111 Character RAM Charact er Address D7–D0
110 Control Word Register Don’t Care D7–D0
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 10
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby making
all eight digits blink at 2.0 Hz.
The Self Test function of the IC consists of two internal routines
which exercise major portions of the IC and illuminates all the
LEDs.
Clear bit clears the charact er RAM and writ es a blank into the dis -
play memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display
at this point. For multiple display operation, CLK I/O must be
properly selected. CL K I/O will output t he internal clock if CLK-
SEL=1, or will allow input from an external clock if CLKSEL=0.
Character RAM
The Character RAM is selected when FL , A4 and A3 are set to
1,1,1 during a read or write cycle. The Character RAM is a 8 by 8
bit RAM wit h each of th e eight lo cations correspo nding to a digit on
the displa y. Digit 0 is on the left si de of the di splay and digit 7 is on
the right side of the display. Address lines, A2–A0 select the digit
address with A2 being the most significant bit and A0 being the
least significant bit. The two types of data stored in the Character
RAM are the ASCII coded data and the UDC Address Data. The
type of data stored in the Character R AM is determined by da ta bit,
D7. If D7 is low, then ASCII coded data is stored in data bits D6–
D0. If D7 is high, then UDC Address Data is stored in data bit D3–
D0.
The ASCII coded data is a 7 bit code used to select one of 128
ASCII characters permanently stored in the ASCII ROM.
The UDC Addres s data is a 4 bit code used to selec t one of the
UDC characters in the UDC RAM. There are up to 16 character s
available. See Table „Character RAM Access Logic“ (page 10).
UDC Address Register and UDC RAM
The UDC Address Register and UDC RAM allows the user to gen-
erate and store up to 16 custom characters. Each custom charac-
ter is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to
define a custom character, one cycle to load the UDC Address
Register and 7 cycles to define the character. The contents of the
UDC Address Re gister w ill store the 4 bi t addr ess f or one of t he 16
UDC RAM locations. The UDC RAM is used to store the custom
character.
UDC Address Register
The UDC Address Register is selected by setting FL=1, A4=0,
A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the
4 bit address code (D7–D4 are ignored). The address code
selects one of 16 UDC RAM locations for custom character gen-
eration.
UDC RAM
The UDC RAM is selected b y setting FL=1, A4=0, A3=1. The RAM
is comprised of a 7 x 5 bit RAM. As shown in Table „UDC Charac-
ter Map“ (page 11), address lines, A2-A0 select one of the 7 rows
of the custom character. Data bits, D4-D0 determine the 5 bits of
column data in each row. Each data bit corresponds to a LED. If
the data bit is high, then the LED is on. If the data bit is low, the
LED is off. To create a character, each of the 7 rows of column
data need to be defined. See Table „UDC Address Register and
UDC RAM“ (page 10) fo r logic.
Character RAM Access Logic
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 1 1 Character Address for
Digits 0–7 0 7 bit ASCII code for a Write Cycle
1 0 1 0 1 1 1 Character Address for
Digits 0–7 0 7 bit AS CII code read du ring a Read Cycl e
1 0 0 1 1 0 0 Character Address for
Digits 0–7 1 D3–D0=UDC address for a Write Cycle
1 0 1 0 1 0 0 Character Address for
Digits 0–7 1 D3–D0=UDC address for Read Data
UDC Address Register and UDC Character RAM
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 0 0 Not used for UDC
Address Register D3–D0=UDC RAM Address Code
for Write Cycle
UDC
Address
Register
1 0 1 0 1 0 0 Not used for UDC
Address Register D3–D0=UDC RAM Address Code
for Read Cycle
1 0 0 1 1 0 1 A2–A0=Character
Row Address D4–D0=Chara c te r Column Data
for Write Cycle
UDC
RAM
1 0 1 0 1 0 1 A2–A0=Character
Row Address D4–D0=Chara c te r Column Data
read during a Read Cycle
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 11
Flash RAM
The Flash RAM allo w s the displ a y to flash one or mo re of t he char -
acters being displayed. The Flash Ram is accessed by setting FL
low. A4 and A3 are ignored. Th e Flash RAM i s a 8 x 1 bit RAM with
each bit corresp on di ng to a d i gi t a ddr e ss. Digit 0 i s o n the l eft sid e
of the displa y and d igit 7 is on the right side of t he displa y. Addre ss
lines, A2–A0 sel ect the digi t addr ess with A2 be ing the most signif -
icant digit and A0 being the least significant digit. Data bit, D0, sets
and resets the flash bit f or each dig it. When D 0 is high, the fla sh bit
is set; and when D0 is low, it is reset. See Table „Flash RAM
Access Logic“ (page 11).
Control Word
The Control Word is used to set up the attributes required by the
user. It is addressed by setting FL=1, A4=1, A3=0. The Control
Word i s a n 8 b it r egiste r an d i s a ccesse d usi ng da ta bi ts, D7–D0.
See Table „Control Word Access Logic“ (page 11) and Figu re
„Control Word Data Definition“ (page 12) for the logic and attrib-
uted control. The Control Word has 5 functions. They are bright-
ness control, flashing character enable, blinking character
enable, self test, and clear (Flash and Character RAMS only).
Brightness Control
Control Word bits, D2–D0, control the brightness of the display
with a binary code of 000 being 100% brightness and 111 being
display blank. See Figure „Control Word Data Definition“
(page 12) f o r brightness le vel v ersus binary code. The a v er age ICC
can be calculated by multiplying the 100% brightness level ICC
value by the display’s brightness level. For example, a display set
to 80% brightness with a 100% aver a ge ICC value of 200 mA will
have an average ICC val ue of 200 mA x 80%=160 mA.
Flash Function
Control Word bit, D3, enables or disables the Flash Function.
When D3 is 1, the Flash Function is enabled and any digit with its
corresponding bit set in the Flash RAM will flash at approximately
2.0 Hz. When using an external clock, the flash rate can be deter-
mined by dividing the clock rate by 28,672. When D3 is 0, the
Flash Function is disabled and the contents of the Flash RAM is
ignored. For synchronized flashing on multiple displays, see the
Reset Section (page 12).
Blink Function
Control W ord bit, D4, enable s or disab les the Blink Funct ion. When
D4 is 1, the Blin k Functi on is e nab led and al l char acte rs on th e di s-
play will blink at approximately 2.0 Hz. The Blink Function will over-
ride the Flash Function if both functions are enabled. When D4 is
0, the Blink Function is d isabled. Whe n using an e xternal clock, the
blink rate can be determined by dividing the clock rate by 28,672.
For synchronized blinking on multiple displays, see the Reset Sec-
tion (page 12).
Self Test
Control Word bits, D6 and D5, are used for the Self Test Function.
When D6 is 1, the Self Test is initiated. Results of the Self Test are
stored in bit D5. Control Word bit, D5, is a read only bit. When D5
is 1, Self Test has passed. When D5 is 0, Self Test failed is indi-
cated. The Self Test function of the IC consists of two internal rou-
tines which exercise major portions of the IC and illuminates all of
the LEDs. The first routine cycles the ASCII de coder ROM through
all states and performs a check sum on the out-put. If the check
sum is correct, D5 is set to a 1 (Pass).
UDC Character Map
Row Data
A2 A1 A0 Row #
Column Data
C1 C2 C3 C4 C5
D4 D3 D2 D1 D0
0001
5 x 7
Dot Matrix
Pattern
0012
0103
0114
1005
1016
1107
Flash RAM Access Logic
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 X X Flash RAM Address
for Digits 0–7 D0=Flash Data, 0=Flash Off and 1=Flash On
(Write Cycle)
1 0 1 0 0 X X Flash RAM Address
for Digits 0–7 D0=Flash Data, 0=Flash Off and 1=Flash On
(Read Cycle)
Control Word Access Logic
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 1 0 Not used for Control
Word Control Word data for a Write Cycle,
see Figure „Control Word Data Definition“
(page 12)
1 0 1 0 1 1 0 Not used for Control
Word Control Word data for a Read during a
Read Cycle
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 12
The second routine provides a visual test of the LEDs. This is
accomplished by writing checkered and inversed checkered pat-
terns to the display. Each pattern is displayed for approximately
2.0 sec. During the self test function the display must not be
accessed. The time needed to execute the self test function is cal-
culated by multiplying the clock time by 262,144 (typical
time ≈ 4.6 s). At the end of the self test, the Character RAM is
loaded with blanks; the Control Word Register is set to zeroes
except D 5; the Fl ash RA M is cleared and the UDC Ad dr ess Re gi s-
ter is set to all 1.0 sec.
Clear Function (see Figure „Control Word Data Definition“
(page 12) and Table „Clear Functi on“ (page 12))
Control Word bit, D7 clears the character RAM to 20 hex and the
flash RAM to all zeroes. The RAMs are cleared within three clock
cycles (110 µs minimum, using the internal clock) when D7 is set
to 1. During the clear time the display must not be accessed.
When the clear function is finished, bit 7 of the Co ntrol Word RAM
will be reset to a “0”.
Reset Function
The display should be reset on power up of the display
(RST=LO W). When th e displa y i s reset, the Char acter RAM , Flash
RAM, and Control Word Register are cleared.
The display's internal counters are reset. Reset cycle takes three
clock cycles (110 µs minimum using the internal clock). The dis-
play must not be accessed during this time.
To synchronize the flashing and blinking of multiple displays, it is
necessary for the display to use a commo n cloc k source and reset
all the displays at the same time to start the internal counters at
the same place.
While RST is low, the display must not be accessed by RD nor
WR.
Control Word Data Definition
Key
C Clear Function
ST Self test
BL Blink function
FL Flash function
Br Brightness control
IDCW5161
Function
Blink
Self Test
Function Brightness Control
D7 D6 D5 D4 D3 D2 D1 D0
D1 D0 Brightness Control
100% Brightness0080% Brightness01
1 53% Brightness0
1 40% Brightness1
Disabled
Flash FunctionD3
0Enabled1
Enabled (overrides Flash Function)
Disabled
Blink Function
D4
1
0
Normal Operation (X = bit ignored)
R
D5
XRun Self Test, R = Test Result (1 = pass, 0 = fail)
Self Test
Clear Flash RAM & Character RAM (Character RAM = 20 Hex)
Normal Operation0
1
Clear FunctionD7
Clear Flash
Function
D2
0
0
0
0
27% Brightness
Blank Display11
1
11
0
10
1
0
0 20% Brightness
13% Brightness
0
0
1
D6
Clear Function
CE WR FL A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
00
01
10
0X
XX
XX
X0
1X
XX
XX
XX
XX
XX
XX
XClear disabled
Clear user RAM, flash RAM
and display
X=don’t care
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 13
Display Cycle Using Built -in RO M Exa mple
Display message “Showtime.” Dig it 0 is leftmost—closest to pin 1.
Logic levels: 0=Low, 1=High, X=Don’t care.
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation Display
0 X1 11XXXXXXXXXXXXXReset. No
Read/Write
Within 3 Clock
Cycles
All Blank
1 00 1110XXX00X0001153% Brightness
Selected All Blank
1 00 111100001010011Write “S” to Digit 0 S
1 00 111100101001000Write “H” to Digit 1 SH
1 00 111101001001111Write “O” to Digit 2 SHO
1 00 111101101010111Write “W” to Digit 3 SHOW
1 00 111110001010100Write “T” to Digit 4 SHOWT
1 00 111110101001001Write “I” to Digit 5 SHOWTI
1 00 111111001001101Write “M” to Digit 6 SHOWTIM
1 00 111111101000101Write “E” to Digit 7 SHOWTIME
Displaying User Defined Char act e r Example
Load character “A” into UDC-5 and then display it in digit 2.
Logic levels: 0=Low, 1=High, X=Don‘t care
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation Display
0 X1 11XXXXXXXXXXXXXReset. No
Read/Write
Within 3 Clock
Cycles
All Blank
1 0 0 1 1 0 0 X X X X X X X 0 1 0 1 Select UDC-5 All Blank
1 00 1101000XXX01110Write into Row 1 of
UDC-5 All Blank
1 00 1101001XXX10001Write into Row 2 of
UDC-5 All Blank
1 00 1101010XXX10001Write into Row 3 of
UDC-5 All Blank
1 00 1101011XXX11111Write into Row 4 of
UDC-5 All Blank
1 00 1101100XXX10001Write into Row 5 of
UDC-5 All Blank
1 00 1101101XXX10001Write into Row 6 of
UDC-5 All Blank
1 00 1101110XXX10001Write into Row 7 of
UDC-5 All Blank
1 00 11110101XXX0101Write UDC-5 into
Digit 2 (Digit 2) A
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 14
Electrical and Mechanical Considerations
Voltage Transient Suppression
For best results power the display and the components that inter-
face with the display to avoid logic inputs higher than VCC. Addi-
tionally, the LEDs may cause transients in the power supply line
while they change display states. The common practice is to place
a parallel combin ation of a 0.01 µF an d a 22 µF capacitor between
VCC and GND for all display packages.
ESD Protection
The input protection structure of the PDSP188X provides signifi-
cant protection ag ai nst E SD dam a ge. It is capable of withstanding
discharges greater than 4.0 kV. Take all the standard precautions
normal for CMOS components. These include properly grounding
personnel, tools, tables, and transport carriers that come in con-
tact with unshi elded parts. If these condi tions are not, or cannot be
met, keep the leads of the device shorted together or the parts in
anti-static packaging.
Soldering Considerations
The PDSP188X can be hand soldered with SN63 solder using a
grounded iron set to 260 °C.
Wave soldering is also possible. Use water soluble organic acid
flux or resin based RMA flux.
A wa v e temperat ure of 24 5 °C ± 5 °C with a dwell between 1.5 sec
to 3.0 sec can be used. Exposure to the wave sho uld not exceed
temperatures above 260 °C for five seconds at 1.59 mm (0.063")
below the seating plane. The packages should not be immersed in
the wave.
Po st Solder Cl eaning Procedures
The least offensive cleaning solution is hot D.I. water (60 °C) for
less than 15 minutes. Addition of mild saponifiers is acceptable.
Do not use commercial dishwasher detergents.
For faster cleaning, solvents may be used. Exercise care in choos-
ing solvents as some may chemically attack the polycarbonate
package. Maximum exposure should not exceed two minutes at
elevated temp eratures. Accepta ble solv e nts are TF (trichorotrifluo-
rethane), and IPA.
Some major solvent manufacturers are: Allied Chemical Corpora-
tion, Specialty Chemical Division, Morristown, NJ;
Baron-Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; E.I.
DuPont de Nemours & Co., Wilmington, DE.
For further information refer t o App note 1 9 at www .osram-os.com
An alternative to soldering and cleaning the display modules is to
use sockets. Naturally, 28 pin DIP sockets 7.62 mm (0.300") wide
with 2.54 mm (0.100") centers work well for single displays. Multi-
ple display assemblies are best handled by longer SIP sockets or
DIP sock ets wh en av aila ble f or unif orm packag e alignmen t. Soc ket
manufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry
Manufacturing, New Brunswick, NJ; Robinson-Nugent, New
Albany, IN; and Samtec Electronic Hardward, New Albany, IN.
Optical Considerations
The 4.70 mm (0.180") high character of the PDSP188X gives
readability up to eight feet. Proper filter selection e nhances re ad-
ability over this distance.
Using filters emphasizes the contrast ratio between a lit LED and
the character background. This will increase the discrimination of
different characters. The only limitation is cost. Take into consider-
ation the ambient lighting environment for the best cost/benefit
ratio for filters.
Incandescent (wit h almost no g reen) or fluorescent (w ith almost no
red) lights do not have the flat spectral response of sunlight. Plas-
tic band-pass filter s are an in expensive and effective way to
strengthen contrast ratios. The PDSP1880 / PDSP1882 are
red / high efficiency red displays and should be matched with a
long wavelength pass filter in the 570 n m to 590 nm range. The
PDSP1883 should be matched with a yellow-green band-pass fil-
ter that peaks at 565 nm. For displays of multiple colors, neutral
density grey filters offer the best compromise.
Additional contrast enhancement is gained by shading the dis-
plays. Plastic band-pass filters with built-in louvers offer the next
step up in contrast improvement. Plastic filters can be improved
further with anti-refle ctive coatings to re duce glare . The trad e-off is
fuzzy characters. Mounting the filters close to the display reduces
this effect. Tak e care not to overhe at the plastic filter by allowing f or
proper air flow.
Optimal filter enhancements are gained by using circular polarized,
anti-reflecti ve, band-pass filters. The circula r polarizing further
enhances contr ast b y red ucing th e light that t ra v els th rough t he filter
and reflects bac k o ff t he display to le ss than 1%.
Several filter manufacturers supply quality filter materials. Some of
them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homa-
lite, Wilmington, DE; 3M Company, Visual Products Division, St.
Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,
MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics,
Inc., Fremont, CA.
One last note on mounting filters: recessing displays and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic
Corp., Burlingame, CA; Photo Chemical Prod ucts of Califor nia,
Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
2006-03-30 15
Published by
OSRAM Opto Semiconductors GmbH
Wernerwerkstrasse 2, D-93049 Regensburg
www.osram-os.com
© All Rights Reserved.
Attention please!
The information describes the type of component and shall not be considered as assured ch aracteristics.
Terms of delivery and rights to change design reserved. Due to technical requirements components may contain
dangerous substances. For information on the types in question please contact our Sales Organization.
If printed or downloaded, please find the latest version in the Internet.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing
material that is retu rned to us unsorted or which we are not obliged to a ccept, we shall have t o invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose! Critical
components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.
1) A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.
2) Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain
human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.
Revision History: 2006-03-30
Previous Version: 2004-12-09
Page Subjects (major changes since last revision) Date of change
all Lead free device 2006-01-23
