M54/74HC374
M54/74HC534
March1993
HC374 NON INVERTING - HC534 INVERTING
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R M74HCXXXM1R
M74HCXXXB1R M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage) C1R
(Chip Carrier)
PIN CONNECTION (top view)
.HIGH SPEED
fMAX = 77 MHz (TYP.) AT VCC =5V
.LOWPOWER DISSIPATION
ICC =4µA(MAX.) AT TA=25°C
.HIGH NOISEIMMUNITY
VNIH =V
NIL =28%V
CC (MIN)
.OUTPUTDRIVE CAPABILITY
15 LSTTLLOADS
.SYMMETRICAL OUTPUT IMPEDANCE
IOL =IOH= 6 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
tPLH =tPHL
.WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO6 V
.PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS374/534
DESCRIPTION
The M54/74HC374, M54/74HC534, arehigh speed
CMOSOCTAL D-TYPEFLIPFLOPWITH3-STATE
OUTPUTS fabricated with in silicon gate C2MOS
technology. They have the same high speed per-
formance of LSTTLcombined with true CMOS low
power comsuption. These8-bit D-type flip-flops are
controlled by aclockinput(CK) and anouputenable
input(OE).On thepositivetransition oftheclock,the
Qoutputswillbesettothelogicstatethatweresetup
at the D inputs (HC374) or their complements
(HC534).
While the OE input is low, the eight outputs will be
in a normal logic state (high or low logic level), and
whilehigh level, the outputs willbe in a high imped-
ance state.The outputcontrol does notaffect thein-
ternaloperation offlip-flops.That is, theolddatacan
be retained or the new data can be entered even
while the outputs are off. The application engineer
has a choice of combination of inverting andnon-in-
vertingoutputs. The HC374and HC574 are identi-
cal, apart from pin layout. The 3-state output
configuration and the wide choice of outline make
bus-organized systems simple. All inputs are
equipped with protection circuits against static dis-
chargeand transient excess voltage.
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