ISL28133FHZ-T7A - Intersil Corporation

Single Micropower, Chopper Stabilized, RRIO

Operational Amplifier

ISL28133

The ISL28133 is a single micropower, chopper stabilized

operational amplifier that is optimized for single supply

operation from 1.8V to 5.5V. Its low supply current of 18µA

and wide input range enable the ISL28133 to be an excellent

general purpose op amp for a range of applications. The

ISL28133 is ideal for handheld devices that operates off 2 AA

or single Li-ion batteries.

The ISL28133 is available in the 5 Ld SOT-23, the 5 Ld SC70 and

the 6 Ld 1.6mmx1.6mm µTDFN packages. All devices operates

over the extended temperature range of -40°C to +125°C.

Related Literature

•AN1480 “ISL28133ISENS-EV1Z Evaluation Board Users

Guide”

•AN1499 “ISL28133EVAL1Z High Gain Evaluation Board

User’s Guide”

Features

• Low Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . 8µV, Max.

• Low Offset TC . . . . . . . . . . . . . . . . . . . . . . . . 0.075µV/°C, Max

• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . 300pA, Max.

• Quiescent Current . . . . . . . . . . . . . . . . . . . . . . . . . . .18µA, Typ.

• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V

• Low Noise (0.01Hz to 10Hz) . . . . . . . . . . . . . . . . . 1.1µVP-P, Typ.

• Rail-to-Rail Inputs and Output

• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C

Applications

• Bidirectional Current Sense

• Temperature Measurement

•Medical Equipment

• Electronic Weigh Scales

BIDIRECTIONAL CURRENT SENSE AMPLIFIER

I-SENSE+

0.1

4.99k

4.99k 499k

499k

ISL28133

V+

V-

GND

VSENSE

OUT

VREF

1.8V TO +5.5V

I-SENSE-

FIGURE 1. TYPICAL APPLICATION CIRCUIT

-6

-4

-2

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

VOS (µV)

MEDIAN

MIN

MAX

N = 67

FIGURE 2. VOS vs TEMPERATURE

July 22, 2011

FN6560.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL28133

2FN6560.5

July 22, 2011

Block Diagram

IN-

V+

IN+

V-

CLOCK GEN + DRIVERS

MAIN AMPLIFIER

VOUT

5kHz CROSSOVER

FILTER

Ordering Information

PART

NUMBER PART MARKING

PACKAGE

Tape & Reel

(Pb-Free)

PKG.

DWG. #

ISL28133FHZ-T7 (Notes 1, 2) BCFA 5 Ld SOT-23 P5.064A

ISL28133FHZ-T7A (Notes 1, 2) BCFA 5 Ld SOT-23 P5.064A

ISL28133FEZ-T7 (Notes 1, 2) BHA 5 Ld SC70 P5.049

ISL28133FRUZ-T7 (Notes 1, 3) T8 6 Ld µTDFN L6.1.6x1.6

ISL28133ISENS-EV1Z Evaluation Board

ISL28133EVAL1Z Evaluation Board

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified

at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL28133. For more information on MSL please see techbrief TB363.

ISL28133

3FN6560.5

July 22, 2011

Pin Configuration

ISL28133

(5 LD SOT-23)

TOP VIEW

ISL28133

(5 LD SC-70)

TOP VIEW

ISL28133

(6 LD µTDFN)

TOP VIEW

OUT

V-

IN+

V+

IN-

IN+

V-

IN-

V+

OUT

V-

IN -

V+

IN +

Pin Descriptions

ISL28133

(5 Ld SOT23)

ISL28133

(5 Ld SC70)

ISL28133

(6 Ld µTDFN)

NAME FUNCTION EQUIVALENT CIRCUIT

3 1 4 IN+ Non-inverting

input

Circuit 1

2 2 2 V- Negative supply

4 3 3 IN- Inverting input (See Circuit 1)

141OUTOutput

Circuit 2

5 5 6 V+ Positive supply

5 NC Not Connected – This pin is not electrically connected internally.

IN-

V+

IN+

V-

CLOCK GEN + DRIVERS

V+

V-

OUT

ISL28133

4FN6560.5

July 22, 2011

Absolute Maximum Ratings Thermal Information

Max Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V

Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V

Max Input Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V

Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V

ESD Rating

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V

Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500V

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

5 Ld SOT-23 (Note 5, 6) . . . . . . . . . . . . . . . . 225 110

5 Ld SC70 (Note 5). . . . . . . . . . . . . . . . . . . . 206 N/A

6 Ld µTDFN (Note 5). . . . . . . . . . . . . . . . . . . 240 N/A

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTE:

5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

6. For θJC, the “case temp” location is taken at the package top center.

Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = Open, unless otherwise specified. Boldface limits

apply over the operating temperature range, -40°C to +125°C.

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 7) TYP

MAX

(Note 7) UNIT

DC SPECIFICATIONS

VOS Input Offset Voltage -8 ±2 8 µV

-15.5 15.5 µV

TCVOS Input Offset Voltage Temperature

Coefficient

0.02 0.075 µV/°C

IOS Input Offset Current -60 pA

IBInput Bias Current -300 ±30 300 pA

-600 600 pA

Common Mode Input

Voltage Range

V+ = 5.0V, V- = GND -0.1 5.1 V

CMRR Common Mode Rejection Ratio VCM = -0.1V to 5.0V 118 125 dB

115 dB

PSRR Power Supply Rejection Ratio Vs = 2V to 5.5V 110 138 dB

110 dB

VOH Output Voltage Swing, High RL = 10kΩ4.965 4.981 V

VOL Output Voltage Swing, Low RL = 10kΩ18 35 mV

AOL Open Loop Gain RL = 1MΩ174 dB

V+Supply Voltage (Note 8) 1.8 5.5 V

ISSupply Current RL = OPEN 18 25 µA

35 µA

ISC+ Output Source Short Circuit Current RL = Short to ground or V+ 13 17 26 mA

ISC- Output Sink Short Circuit Current -26 -19 -13 mA

AC SPECIFICATIONS

GBWP Gain Bandwidth Product

f = 50kHz

AV = 100, RF = 100kΩ,

RG=1kΩ, RL = 10kΩ to VCM

400 kHz

ISL28133

5FN6560.5

July 22, 2011

eN VP-P Peak-to-Peak Input Noise Voltage f = 0.01Hz to 10Hz 1.1 µVP-P

eNInput Noise Voltage Density f = 1kHz 65 nV/√(Hz)

iNInput Noise Current Density f = 1kHz 72 fA/√(Hz)

f = 10Hz 79 fA/√(Hz)

Cin Differential Input Capacitance f = 1MHz 1.6 pF

Common Mode Input Capacitance 1.12 pF

TRANSIENT RESPONSE

SR Positive Slew Rate VOUT = 1V to 4V, RL = 10kΩ0.2 V/µs

Negative Slew Rate 0.1 V/µs

tr, tf, Small Signal Rise Time, tr 10% to 90% AV = +1, VOUT = 0.1VP-P,

RF=0Ω, RL = 10kΩ, CL=1.2pF

1.1 µs

Fall Time, tf 10% to 90% 1.1 µs

tr, tf Large Signal Rise Time, tr 10% to 90% AV = +1, VOUT = 2VP-P, RF=0Ω,

RL = 10kΩ, CL= 1.2pF

8µs

Fall Time, tf 10% to 90% 10 µs

tsSettling Time to 0.1%, 2VP-P Step AV = +1, RF = 0Ω, RL=10kΩ,

CL= 1.2pF

35 µs

NOTES:

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

8. Parts are 100% tested with a minimum operating voltage of 1.8V to a VOS limit of ±15µV.

Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25°C, RL = Open, unless otherwise specified. Boldface limits

apply over the operating temperature range, -40°C to +125°C. (Continued)

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 7) TYP

MAX

(Note 7) UNIT

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open.

FIGURE 3. AVERAGE INPUT OFFSET VOLTAGE vs SUPPLY

VOLTAGE

FIGURE 4. VOS vs TEMPERATURE, VS = ±1.0V, VIN =0V,

RL=INF

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

AVERAGE VOS (µV)

+25°C

N = 67 -40°C

125°C

-12

-10

-8

-6

-4

-2

-40 -20 20 40 60 80 100 120

TEMPERATURE (°C)

VOS (µV)

100800

MIN

MAX N = 67

MEDIAN

ISL28133

6FN6560.5

July 22, 2011

FIGURE 5. VOS vs TEMPERATURE, VS = ±2.5V, VIN =0V, R

L =

INF

FIGURE 6. IB+ vs SUPPLY VOLTAGE vs TEMPERATURE

FIGURE 7. IB- vs SUPPLY VOLTAGE vs TEMPERATURE FIGURE 8. IOS vs SUPPLY VOLTAGE vs TEMPERATURE

FIGURE 9. AVERAGE SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 10. MIN/MAX SUPPLY CURRENT vs TEMPERATURE,

VS = ±0.8V, VIN = 0V, RL = INF

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)

-6

-4

-2

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

VOS (µV)

MEDIAN

MIN

MAX

N = 67

-50

100

150

200

1.52.02.53.03.54.04.55.05.5

SUPPLY VOLTAGE (V)

IBIAS IN+(pA)

-40°C

+25°C

+125°C

N = 12

+100°C

+75°C

-40°C

-50

100

150

200

250

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

IBIAS IN- (pA)

+25°C

-40°C

N = 12

+100°C

+125°C

+75°C

+25°C

-40°C

-80

-70

-60

-50

-40

-30

-20

-10

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

AVERAGE IOS (pA)

+125°C

N = 67

+25°C

-40°C

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

AVERAGE SUPPLY CURRENT (µA)

+25°C

N = 67

-40°C

+125°C

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

MEDIAN

MIN

MAX

N = 67

ISL28133

7FN6560.5

July 22, 2011

FIGURE 11. MIN/MAX SUPPLY CURRENT vs TEMPERATURE,

VS = ±2.5V, VIN = 0V, RL = INF

FIGURE 12. INPUT NOISE VOLTAGE 0.01Hz TO 10Hz

FIGURE 13. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY FIGURE 14. INPUT NOISE CURRENT DENSITY vs FREQUENCY

FIGURE 15. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL =

10k

FIGURE 16. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL =

10M

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

MEDIAN

MIN

MAX

N = 67

TIME (s)

INPUT NOISE VOLTAGE (nV)

-600

-400

-200

200

400

600

800

0 102030405060708090100

V+ = 5V

RL = 100k

Rg = 10, Rf = 100k

AV = 10,000

CL = 3.7pF

FREQUENCY (Hz)

100

1000

INPUT NOISE VOLTAGE (nV/√Hz)

0.001 0.01 0.1 1 10 100 1k 10k 100k

V+ = 5V

AV = 1

FREQUENCY (Hz)

0.01

0.1

1.0

0.001 0.01 0.1 1 10 100 1k 10k 100k

INPUT NOISE CURRENT (pA/√Hz)

V+ = 5V

AV = 1

-100

-50

100

150

200

1 100 10k 100k1M 10M

OPEN LOOP GAIN (dB)/PHASE (°)

FREQUENCY (Hz)

RL = 10k

SIMULATION

CL = 100pF

GAIN

PHASE

1k10100m10m1m0.1m

-100

-50

100

150

200

OPEN LOOP GAIN (dB)/PHASE (°)

FREQUENCY (Hz)

RL = 10M

SIMULATION

CL = 100pF

GAIN

PHASE

1 100 10k 100k1M 10M1k10100m10m1m0.1m

ISL28133

8FN6560.5

July 22, 2011

FIGURE 17. GAIN vs FREQUENCY vs RL, VS = 1.6V FIGURE 18. GAIN vs FREQUENCY vs RL, VS = 5V

FIGURE 19. GAIN vs FREQUENCY vs FEEDBACK RESISTOR

VALUES Rf/Rg

FIGURE 20. GAIN vs FREQUENCY vs VOUT, RL = OPEN

FIGURE 21. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 22. GAIN vs FREQUENCY vs SUPPLY VOLTAGE

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)

-8

-7

-6

-5

-4

-3

-2

-1

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

10k 100k 1M 10M

100

V+ = 1.6V

AV = +1

VOUT = 10mVP-P

CL = 3.7pF

RL = 1k

RL = 10k

RL = 49.9k

RL = 100k RL = OPEN

-8

-7

-6

-5

-4

-3

-2

-1

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

10k 100k 1M 10M

100

V+ = 5V

AV = +1

VOUT = 10mVP-P

CL = 3.7pF

RL = 100k

RL = 1k

RL = 10k

RL = OPEN

RL = 49.9k

100 1k 10k 100k 1M

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

V+ = 5V

RL = 100k

AV = +2

VOUT = 10mVP-P

CL = 3.7pF

Rf = Rg = 100k

Rf = Rg = 10k

Rf = Rg = 1k

-9

-8

-7

-6

-5

-4

-3

-2

-1

10k 100k 1M 10M

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

V+ = 5V

RL = OPEN

AV = +1

CL = 3.7pF

100

VOUT = 10mV

VOUT = 100mV

VOUT = 1V

VOUT = 250mV

VOUT = 500mV

-10

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

GAIN (dB)

AV = 1

AV = 10

AV = 100

AV = 1000

V+ = 5V

VOUT = 10mVP-P

CL = 3.7pF

RL = 100k

Rg = 10k, Rf = 100k

Rg = 100, Rf = 100k

Rg = 1k, Rf = 100k

Rg = OPEN, Rf = 0

-9

-8

-7

-6

-5

-4

-3

-2

-1

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

10k 100k 1M 10M

100

RL = 100k

AV = +1

VOUT = 10mVP-P

CL = 3.7pF

V+ = 1.6V

V+ = 3.0V

V+ = 5.5V

V+ = 1.2V

ISL28133

9FN6560.5

July 22, 2011

FIGURE 23. GAIN vs FREQUENCY vs CLFIGURE 24. CMRR vs FREQUENCY, VS = 5V

FIGURE 25. PSRR vs FREQUENCY, VS = 5V FIGURE 26. CMRR vs FREQUENCY, VS = 1.6V

FIGURE 27. PSRR vs FREQUENCY, VS = 1.6V FIGURE 28. CMRR vs TEMPERATURE, VCM = -2.5V TO +2.5V, V+

= ±2.5V

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

-10

-8

-6

-4

-2

10k 100k 1M 10M

100

V+ = 5V

RL = 100k

AV = +1

VOUT = 10mVP-P

CL = 824pF

CL = 224pF

CL = 474pF

CL = 51pF

CL = 3.7pF

CL = 104pF

CMRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

V+ = 5V

RL = 100k

AV = +1

VCM = 1VP-P

CL = 16.3pF

PSRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR-

PSRR+ V+ = 5V

RL = 100k

AV = +1

VCM = 1VP-P

CL = 16.3pF

CMRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

V+ =1.6V

RL = 100k

AV = +1

VCM = 1VP-P

CL = 16.3pF

PSRR (dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

PSRR-

PSRR+

V+ = 1.6V

RL = 100k

AV = +1

VCM = 1VP-P

CL = 16.3pF

100

120

140

160

180

200

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

CMRR (dB)

MEDIAN

MIN

MAX

N = 67

ISL28133

10 FN6560.5

July 22, 2011

FIGURE 29. PSRR vs TEMPERATURE, V+ = 2V TO 5.5V FIGURE 30. LARGE SIGNAL STEP RESPONSE (4V)

FIGURE 31. LARGE SIGNAL STEP RESPONSE (1V) FIGURE 32. SMALL SIGNAL STEP RESPONSE (100mV)

FIGURE 33. VOUT HIGH vs TEMPERATURE, RL = 10k, VS +-2.5V FIGURE 34. VOUT LOW vs TEMPERATURE, RL = 10k, VS +-2.5V

Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued)

105

115

125

135

145

155

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

PSRR (dB)

MEDIAN

MIN

MAX

N = 67

TIME (µs)

LARGE SIGNAL (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 50 100 150 200 250 300 350 400

V+ = 5V

RL = 100k

AV = 1

CL = 3.7pF

VOUT = 4VP-P

TIME (µs)

LARGE SIGNAL (V)

0.2

0.4

0.6

0.8

1.0

1.2

0 102030405060708090100

V+ = 5V

RL = 100k

AV = 1

CL = 3.7pF

VOUT = 1VP-P

TIME (µs)

SMALL SIGNAL (V)

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0 5 10 15 20 25 30 35 40

V+ = 5V

RL = 100k

AV = 1

CL = 3.7pF

VOUT = 100mVP-P

4.972

4.974

4.976

4.978

4.980

4.982

4.984

4.986

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

VOUT (V)

MEDIAN

MIN

MAX

N = 67

0.016

0.017

0.018

0.019

0.020

0.021

0.022

0.023

0.024

-40 -20 0 20 40 60 80 100 120

TEMPERATURE (°C)

OUT

(V)

MEDIAN

MIN

MAX

N = 67

ISL28133

11 FN6560.5

July 22, 2011

Applications Information

Functional Description

The ISL28133 uses a proprietary chopper-stabilized architecture

shown in the “Block Diagram” on page 2. The ISL28133

combines a 400kHz main amplifier with a very high open loop

gain (174dB) chopper stabilized amplifier to achieve very low

offset voltage and drift (2µV, 0.02µV/°C typical) while

consuming only 18µA of supply current per channel.

This multi-path amplifier architecture contains a time continuous

main amplifier whose input DC offset is corrected by a

parallel-connected, high gain chopper stabilized DC correction

amplifier operating at 100kHz. From DC to ~5kHz, both

amplifiers are active with DC offset correction and most of the

low frequency gain is provided by the chopper amplifier. A 5kHz

crossover filter cuts off the low frequency amplifier path leaving

the main amplifier active out to the 400kHz gain-bandwidth

product of the device.

The key benefits of this architecture for precision applications are

very high open loop gain, very low DC offset, and low 1/f noise.

The noise is virtually flat across the frequency range from a few

mHz out to 100kHz, except for the narrow noise peak at the

amplifier crossover frequency (5kHz).

Rail-to-rail Input and Output (RRIO)

The RRIO CMOS amplifier uses parallel input PMOS and NMOS

that enable the inputs to swing 100mV beyond either supply rail.

The inverting and non-inverting inputs do not have back-to-back

input clamp diodes and are capable of maintaining high input

impedance at high differential input voltages. This is effective in

eliminating output distortion caused by high slew-rate input

signals.

The output stage uses common source connected PMOS and

NMOS devices to achieve rail-to-rail output drive capability with

17mA current limit and the capability to swing to within 20mV of

either rail while driving a 10kΩ load.

IN+ and IN- Protection

All input terminals have internal ESD protection diodes to both

positive and negative supply rails, limiting the input voltage to

within one diode beyond the supply rails. For applications where

either input is expected to exceed the rails by 0.5V, an external

series resistor must be used to ensure the input currents never

exceed 20mA (see Figure 35).

Layout Guidelines for High Impedance Inputs

To achieve the maximum performance of the high input

impedance and low offset voltage of the ISL28133 amplifiers,

care should be taken in the circuit board layout. The PC board

surface must remain clean and free of moisture to avoid leakage

currents between adjacent traces. Surface coating of the circuit

board will reduce surface moisture and provide a humidity barrier,

reducing parasitic resistance on the board.

High Gain, Precision DC-Coupled Amplifier

The circuit in Figure 36 implements a single-stage, 10kV/V

DC-coupled amplifier with an input DC sensitivity of under 100nV

that is only possible using a low VOS amplifier with high open

loop gain. This circuit is practical down to 1.8V due to it's

rail-to-rail input and output capability. Standard high gain DC

amplifiers operating from low voltage supplies are not practical

at these high gains using typical low offset precision op amps

because the input offset voltage and temperature coefficient

consume most of the available output voltage swing. For

example, a typical precision amplifier in a gain of 10kV/V with a

±100µV VOS and a temperature coefficient of 0.5µV/°C would

produce a DC error at the output of >1V with an additional

5mV°C of temperature dependent error. At 3V, this DC error

consumes > 30% of the total supply voltage, making it

impractical to measure sub-microvolt low frequency signals.

The ±8µV max VOS and 0.075µV/°C of the ISL28133 produces a

temperature stable maximum DC output error of only ±80mV

with a maximum temperature drift of 0.75mV/°C. The additional

benefit of a very low 1/f noise corner frequency and some

feedback filtering enables DC voltages and voltage fluctuations

well below 100nV to be easily detected with a simple single

stage amplifier.

FIGURE 35. INPUT CURRENT LIMITING

RIN

VIN

VOUT

FIGURE 36. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER

100Ω

VIN

VOUT

1MΩ

1MΩ,

100Ω-2.5V

+2.5V

ACL = 10kV/V

0.018µF

ISL28133

12 FN6560.5

July 22, 2011

Long Term VOS Drift

Figure 37 shows a plot of daily VOS drift measurements of 30

individual ISL28133 amplifiers over a continuous 572 day period

at +25°C. The 30 units were connected in a gain of 10k,

mounted on a single PC board and kept at room temp. The 30

amplifier outputs were measured daily by a DVM and scanner

under computer control. The daily VOS measurements were

subtracted from the initial VOS value to calculate the VOS shift.

The test board was powered from a UPS to maintain

uninterrupted power to the test units. Three instances of lost

measurement data ranging from 2 days to 2 weeks due to power

loss to the measurement scanner were detected, and data were

interpolated.

The change in amplifier VOS over the 572 day period for all 30

amplifiers (see Figure 38) was less than ±100nV, and no clear

VOS long term drift trend was evident in the data. The excellent

long term drift performance is a result of the chopper amplifier’s

ability to measure and correct VOS errors, leaving only the VOS

error contribution due to changes in the long term stability of the

external components (see Figure 39).

ISL28133 SPICE Model

Figure 40 shows the SPICE model schematic and Figure 41

shows the net list for the ISL28133 SPICE model. The model is a

simplified version of the actual device and simulates important

parameters such as noise, Slew Rate, Gain and Phase. The

model uses typical parameters from the ISL28133. The poles

and zeros in the model were determined from the actual open

and closed-loop gain and phase response. This enables the

model to present an accurate AC representation of the actual

device. The model is configured for ambient temperature of

+25°C.

Figures 42 through 49 show the characterization vs simulation

results for the Noise Density, Frequency Response vs Close Loop

Gain, Gain vs Frequency vs CL and Large Signal Step Response

(4V).

FIGURE 37. LONG TERM DRIFT (VOS vs TIME) FOR 30 UNITS FIGURE 38. LONG TERM DRIFT (VOS vs TIME) FOR A SINGLE UNIT

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 30 60 90 120 180 240 300 360 420 480 540 600

(µV)

TIME (DAYS)

-1.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 30 60 90 120 180 240 300 360 420 480 540 600

(µV)

TIME (DAYS)

10Ω

1kΩ

VOUT

100kΩ

10Ω

100kΩ

FIGURE 39. LONG TERM DRIFT TEST CIRCUIT

+2.5V

-2.5V

ACL = 10kV/V

ISL28133

13 FN6560.5

July 22, 2011

M1 M2

R2R1

R3 R4

R21R22

Dn1

V15

Dn2

V16

Cin1 Cin2

Vin+

Vin-

VV3

R5 D1

VV3

E1 G5

R12

R11

R10

R9 L2

R14

R13 C4

G9 G10

D7 D8

G11

G10

R16

R15

V+

Vout

V-

Voltage Noise Input Stage

Gain Stage SR Limit & First Pole

Pole Output Stage

Zero/Pole

FIGURE 40. SPICE CIRCUIT SCHEMATIC

ISL28133

14 FN6560.5

July 22, 2011

* ISL28133 Macromodel

* Revision B, April 2009

* AC characteristics, Voltage Noise

* Connections: +input

* | -input

* | | +Vsupply

* | | | -Vsupply

* | | | | output

* | | | | |

.subckt ISL28133 3 2 7 4 6

*Voltage Noise

D_DN1 102 101 DN

D_DN2 104 103 DN

R_R21 0 101 120k

R_R22 0 103 120k

E_EN 8 3 101 103 1

V_V15 102 0 0.1Vdc

V_V16 104 0 0.1Vdc

*Input Stage

C_Cin1 8 0 0.4p

C_Cin2 2 0 2.0p

R_R1 9 10 10

R_R2 10 11 10

R_R3 4 12 100

R_R4 4 13 100

M_M1 12 8 9 9 pmosisil

+ L=50u

+ W=50u

M_M2 13 2 11 11 pmosisil

+ L=50u

+ W=50u

I_I1 4 7 DC 92uA

I_I2 7 10 DC 100uA

*Gain stage

G_G1 4 VV2 13 12 0.0002

G_G2 7 VV2 13 12 0.0002

R_R5 4 VV2 1.3Meg

R_R6 VV2 7 1.3Meg

D_D1 4 14 DX

D_D2 15 7 DX

V_V3 VV2 14 0.7Vdc

V_V4 15 VV2 0.7Vdc

*SR limit first pole

G_G3 4 VV3 VV2 16 1

G_G4 7 VV3 VV2 16 1

R_R7 4 VV3 1meg

R_R8 VV3 7 1meg

C_C1 VV3 7 12u

C_C2 4 VV3 12u

D_D3 4 17 DX

D_D4 18 7 DX

V_V5 VV3 17 0.7Vdc

V_V6 18 VV3 0.7Vdc

*Zero/Pole

E_E1 16 4 7 4 0.5

G_G5 4 VV4 VV3 16 0.000001

G_G6 7 VV4 VV3 16 0.000001

L_L1 20 7 0.3H

R_R12 20 7 2.5meg

R_R11 VV4 20 1meg

L_L2 4 19 0.3H

R_R9 4 19 2.5meg

R_R10 19 VV4 1meg

*Pole

G_G7 4 VV5 VV4 16 0.000001

G_G8 7 VV5 VV4 16 0.000001

C_C3 VV5 7 0.12p

C_C4 4 VV5 0.12p

R_R13 4 VV5 1meg

R_R14 VV5 7 1meg

*Output Stage

G_G9 21 4 6 VV5 0.0000125

G_G10 22 4 VV5 6 0.0000125

D_D5 4 21 DY

D_D6 4 22 DY

D_D7 7 21 DX

D_D8 7 22 DX

R_R15 4 6 8k

R_R16 6 7 8k

G_G11 6 4 VV5 4 -0.000125

G_G12 7 6 7 VV5 -0.000125

.model pmosisil pmos (kp=16e-3 vto=10m)

.model DN D(KF=6.4E-16 AF=1)

.MODEL DX D(IS=1E-18 Rs=1)

.MODEL DY D(IS=1E-15 BV=50 Rs=1)

.ends ISL28133

FIGURE 41. SPICE NET LIST

ISL28133

15 FN6560.5

July 22, 2011

Characterization vs Simulation Results

FIGURE 42. CHARACTERIZED INPUT NOISE VOLTAGE DENSITY

vs FREQUENCY

FIGURE 43. SIMULATED INPUT NOISE VOLTAGE DENSITY vs

FREQUENCY

FIGURE 44. CHARACTERIZED FREQUENCY RESPONSE vs

CLOSED LOOP GAIN

FIGURE 45. SIMULATED FREQUENCY RESPONSE vs CLOSED

LOOP GAIN

FIGURE 46. CHARACTERIZED GAIN vs FREQUENCY vs CLFIGURE 47. SIMULATED GAIN vs FREQUENCY vs CL

FREQUENCY (Hz)

100

1000

INPUT NOISE VOLTAGE (nV/√Hz

0.001 0.01 0.1 1 10 100 1k 10k 100k

V+ = 5V

AV = 1

FREQUENCY (Hz)

100

1000

INPUT NOISE VOLTAGE (nV/√Hz

0.1 1 10 100 1k 10k 100k

V+ = 5V

AV = 1

-10

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

GAIN (dB)

= 1

= 10

= 100

= 1000

= 5V

OUT

= 10mV

P-P

= 3.7pF

= 100k

= 10k, R

= 100k

= 100, R

= 100k

= 1k, R

= 100k

= OPEN, R

= 0

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

AV = 1

AV = 10

AV = 100

AV = 1000

Rg = 1k, Rf = 100k

Rg = 100, Rf = 100k

Rg = 10M Rf = 1

Rg = 10k, Rf = 100k

-10

GAIN (dB)

FREQUENCY (Hz)

NORMALIZED GAIN (dB)

-10

-8

-6

-4

-2

10k 100k 1M 10M

100

V+ = 5V

RL = 100k

AV = +1

VOUT = 10mVP-P

CL = 824pF

CL = 224pF

CL = 474pF

CL = 51pF

CL = 3.7pF

CL = 104pF

CL = 824pF

CL = 474pF

CL = 224pF

CL = 824pF

CL = 3.7pF

FREQUENCY (Hz)

-10

-8

-6

-4

-2

10k 100k 1M 10M

100

CL = 224pF

NORMALIZED GAIN (dB)

ISL28133

16 FN6560.5

July 22, 2011

FIGURE 48. CHARACTERIZED LARGE SIGNAL STEP RESPONSE

(4V)

FIGURE 49. SIMULATED LARGE SIGNAL STEP RESPONSE (4V)

Characterization vs Simulation Results (Continued)

TIME (µs)

LARGE SIGNAL (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 50 100 150 200 250 300 350 400

V+ = 5V

RL = 100k

AV = 1

CL = 3.7pF

VOUT = 4VP-P

VOUT

VIN

TIME (µs)

LARGE SIGNAL (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 50 100 150 200 250 300 350 400

ISL28133

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6560.5

July 22, 2011

For additional products, see www.intersil.com/product_tree

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL28133

To report errors or suggestions for this data sheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE REVISION CHANGE

5/31/11 FN6560.5 Changed minimum operating supply voltage from +1.65V to +1.8V throughout entire datasheet.

Added Tjc information for 5 Ld SOT-23 package in Thermal information on page 5.

2/1/11 FN6560.4 -Converted to Updated Intersil Template.

-Page 1 Graphics numbered as Figures 1 and 2.

-Updated Ordering Information on page 2 by adding part ISL28133FHZ-T7A.

-Changed Note on page 5, which read “Parameters with MIN and/or MAX limits are 100% tested at +25°C,

unless otherwise specified. Temperature limits established by characterization and are not production tested.”

to “Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or

design.”

-Added two Long Term Drift Curves (Figures 37 and 38) and section “Long Term VOS Drift” on page 12

-Replaced POD MDP0038 (no dimension changes), now obsolete with P5.064A.

5/3/10 FN6560.3 Title Page 1: Replaced “Zero-Drift” with “Chopper Stabilized” for title and part description

On page 3: Pin Configuration: MTDFN -> uTDFN

On page 7: Figure 12: Changed 0.1Hz to 0.01Hz in Figure caption

On page 11: In “Functional Description”; Paragraph 1, 2nd sentence:

Changed text from "…open loop gain (200dB)…" -to- "…open loop gain (174dB)…"

Changed TYP for “Open Loop Gain” on page 4 from 200dB to 174dB.

On page 11: In “High Gain, Precision DC-Coupled Amplifier”; Paragraph 2, 1st sentence:

Changed text from

"...DC output error of only ±80mV with a maximum temperature drift of 0.75µV/°C."

"… DC output error of only ±80mV with a maximum temperature drift of 0.75mV/C."

2/24/10 Removed “Coming Soon” from ISL28133EVAL1Z in the ordering information table on pg 2.

09/24/09 FN6560.2 Converted to new Intersil template. Removed ISL28233 and ISL28433 from data sheet, added Applications,

Related Literature, Typical Application Circuit, Performance Curve,

updated ordering information by removing “coming soon” on SC70 and uTDFN packages and adding Eval board

listed as “coming soon”. Added Block Diagram, Changed in Abs Max Rating Voltage from “5.75V” to “6.5V”.

Removed Tjc from Thermal Information until provided by packaging scheduled for 9-11-09. Changed Low Offset

“drift” to Low Offset “TC”, added Max Junction Temp 140C, added SPICE model and simulation results, removed

supply current graph at +-3V, re-ordered typical performance curves, removed guard ring information from

application section. Added Revision History and Products Information

05/29/09 FN6560.1 Page 4: Removed the RL = 100 Curve from Figures 3, 4 and 5.

Page 1: Under Features, removed the word "Output" from "Low Output Noise"

03/25/09 FN6560.0 Initial Release to WEB

ISL28133

18 FN6560.5

July 22, 2011

Small Outline Transistor Plastic Packages (SC70-5)

AA1

0.20 (0.008) M

0.10 (0.004) C

-C-

SEATING

PLANE

123

VIEW C

4X θ1

GAUGE PLANE

SEATING

αL2

PLANE

BASE METAL

WITH

PLATING

0.4mm

0.75mm

0.65mm

2.1mm

TYPICAL RECOMMENDED LAND PATTERN

P5.049

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.031 0.043 0.80 1.10 -

A1 0.000 0.004 0.00 0.10 -

A2 0.031 0.039 0.80 1.00 -

b 0.006 0.012 0.15 0.30 -

b1 0.006 0.010 0.15 0.25

c 0.003 0.009 0.08 0.22 6

c1 0.003 0.009 0.08 0.20 6

D 0.073 0.085 1.85 2.15 3

E 0.071 0.094 1.80 2.40 -

E1 0.045 0.053 1.15 1.35 3

e 0.0256 Ref 0.65 Ref -

e1 0.0512 Ref 1.30 Ref -

L 0.010 0.018 0.26 0.46 4

L1 0.017 Ref. 0.420 Ref. -

L2 0.006 BSC 0.15 BSC

α0o8o0o8o-

N5 55

R 0.004 - 0.10 -

R1 0.004 0.010 0.15 0.25

Rev. 3 7/07

NOTES:

1. Dimensioning and tolerances per ASME Y14.5M-1994.

2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.

3. Dimensions D and E1 are exclusive of mold flash, protrusions,

or gate burrs.

4. Footlength L measured at reference to gauge plane.

5. “N” is the number of terminal positions.

6. These Dimensions apply to the flat section of the lead between

0.08mm and 0.15mm from the lead tip.

7. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

ISL28133

19 FN6560.5

July 22, 2011

Package Outline Drawing

L6.1.6x1.6

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL)

Rev 1, 11/07

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

TOP VIEW

BOTTOM VIEW

SIDE VIEW

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES:

1.60

5X 0 . 40 ± 0 . 1

0.15

( 1 . 4 )

(4X)

( 6X 0 . 25 )

( 1X 0 .70 )

( 4X 0 . 5 )

0 . 55 MAX

BASE PLANE

SEATING PLANE

0.08

0.10

0.25 +0.05 / -0.07

SEE DETAIL "X"

0.10

CAMB

INDEX AREA

PIN 1

1.60 A

PIN #1 INDEX AREA

0.50

2X 1.00

( 5X 0 . 60 )

0 . 00 MIN.

0 . 05 MAX.

0 . 2 REF

1X 0.5 ±0.1

ISL28133

20 FN6560.5

July 22, 2011

Package Outline Drawing

P5.064A

5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

Rev 0, 2/10

Dimension is exclusive of mold flash, protrusions or gate burrs.

This dimension is measured at Datum “H”.

Package conforms to JEDEC MO-178AA.

Foot length is measured at reference to guage plane.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to ASME Y14.5M-1994.

Dimensions are in millimeters.1.

NOTES:

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

INDEX AREA

PIN 1

SEATING PLANE

GAUGE

0.45±0.1

(2 PLCS)

10° TYP

1.90

0.40 ±0.05

2.90

0.95

1.60

2.80

0.05-0.15

1.14 ±0.15

0.20 CA-B DM

(1.20)

(0.60)

(0.95)

(2.40)

0.10 C

0.08-0.20

SEE DETAIL X

1.45 MAX

(0.60)

0-3°

0.20 C

(1.90)

0.15 C

A-B

(0.25)

END VIEW

PLANE