Advanced v.1 HiRel SX-A Family FPGAs Le a di n g E d ge P er f o r m a n ce * 100% Military Temperature Tested (-55C to +125C) * 215 MHz System Performance (Military Temperature) * 66 MHz PCI Compliant * 5.3 ns Clock-to-Out (Pin-to-Pin) (Military Temperature) * CPLD and FPGA Integration * 284 MHz Internal Performance (Military Temperature) * Single-Chip Solution Sp e ci f i c a t i on s * Configurable I/O Support for 3.3V/5.0V PCI, LVTTL, and TTL * 12,000 to 108,000 Available System Gates * Up to 225 User-Programmable I/O Pins * Up to 2,012 Dedicated Flip-Flops * 0.25 CMOS Process Technology * Configurable Weak Resistor Pull-up or Pull-down for Tristated Outputs at Power Up * 100% Resource Utilization with 100% Pin Locking Fe a t ur es * 2.5V, 3.3V, and 5.0V Mixed-Voltage Operation with 5.0V Input Tolerance and 5.0V Drive Strength * I/Os with Live or "Hot-Swapping" Capability * Very Low Power Consumption * Power Up/Down Friendly (No Sequencing Required for Supply Voltages) * Deterministic, User-Controllable Timing * Offered as Commercial or Military Temperature Tested and Class B * Cost Effective QML MIL-Temp Plastic Packaging Options * Standard Hermetic Package Offerings * QML Certified Devices * Unique In-System Diagnostic and Verification Capability with Silicon Explorer II * Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) * Secure Programming Technology Prevents Reverse Engineering and Design Theft Pr od uc t P r o f i l e Device A54SX32A A54SX72A Capacity Typical Gates System Gates 32,000 48,000 72,000 108,00 Logic Modules 2,880 6,036 Combinatorial Cells 1,800 4,024 Register Cells (Dedicated Flip-Flops) 1,080 2,012 Maximum User I/Os 225 206 Global Clocks 3 3 Quadrant Clocks 0 4 Boundary Scan Testing Yes Yes 3.3V/5.0V PCI Yes Yes Clock-to-Out 5.4 ns 6.7 ns Input Setup (External) Speed Grades Package (by pin count) CQFP April 2000 (c) 2000 Actel Corporation 0 ns 0 ns Std, -1 Std, -1 208, 256 208, 256 1 G en er al D e sc r i p t i on Q M L Ce r t i f i c a t i o n Actel's SX-A family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX-A devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-intensive applications. Actel has achieved full QML certification, demonstrating that quality management, procedures, processes, and controls are in place and comply with MIL-PRF-38535, the performance specification used by the Department of Defense for monolithic integrated circuits. QML certification is a good example of Actel's commitment to supplying the highest quality products for all types of high-reliability, military, and space applications. Actel's SX-A architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. The routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. This enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or "sea-of-modules"), which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX-A devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three antifuses). The unique local and general routing structure featured in SX-A devices gives fast and predictable performance, allows 100 percent pin locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with minimum effort. Further complementing SX-A's flexible routing structure is a hardwired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input setup times. SX-A devices have easy-to-use I/O cells that do not require HDL instantiation, facilitating design re-use and reducing design and verification time. 2 Many suppliers of microelectronics components have implemented QML as their primary worldwide business system. Appropriate use of this system not only helps in the implementation of advanced technologies, but also allows for a quality, reliable and cost-effective logistics support throughout QML products' life cycles. D ev e l op m en t T o ol S up p or t The SX-A devices are fully supported by Actel's line of FPGA development tools, including the Actel DeskTOP series and Designer Advantage tools. The Actel DeskTOP series is an integrated design environment for PCs that includes design entry, simulation, synthesis, and place-and-route tools. Designer Advantage, Actel's suite of FPGA development point tools for PCs and Workstations, includes the ACTgen Macro Builder, Designer with DirectTime timing-driven place-and-route and analysis tools, and device programming software. In addition, the SX-A devices contain ActionProbe circuitry that provides built-in access to every node in a design, enabling 100-percent real-time observation and analysis of a device's internal logic nodes without design iteration. The probe circuitry is accessed by Silicon Explorer II, an easy to use integrated verification and logic analysis tool that can sample data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer. Silicon Explorer II allows designers to complete the design verification process at their desks and reduces verification time from several hours per cycle to only a few seconds. Hi R e l S X -A F a m i ly F PG A s O r d e r i n g I nf o r m a t i o n A54SX16 A - 1 CQ 208 Application (Temperature Range) Blank = Commercial (0 to +70C) M = Military (-55 to +125C) PP = Pre-production B = MIL-STD-883 Package Lead Count Package Type CQ = Ceramic Quad Flat Pack Speed Grade Blank = Standard Speed -1 = Approximately 15% Faster than Standard A = 0.25 CMOS Technology Part Number A54SX32 = 48,000 System Gates A54SX72 = 108,000 System Gates Pr od uc t P l a n Speed Grade* Application Std -1 C M* B 208-Pin Ceramic Quad Flat Pack (CQFP) P P P P P 256-Pin Ceramic Quad Flat Pack (CQFP) P P P P P 208-Pin Ceramic Quad Flat Pack (CQFP) P P P P P 256-Pin Ceramic Quad Flat Pack (CQFP) P P P P P A54SX32A Device A54SX72A Device Contact your Actel sales representative for product availability. Applications: C = Commercial Availability: P = Planned M = Military B = MIL-STD-883 *Speed Grade: -1 = Approx. 15% faster than Standard * Only Std and -1 Speed Grades C er a m i c De v i ce R es ou r c es User I/Os (including clock buffers) CQFP 208-Pin CQFP 256-Pin A54SX32A 174 228 A54SX72A 171 213 Device Contact your Actel sales representative for product availability. Package Definitions CQFP = Ceramic Quad Flat Pack 3 A ct e l M I L - ST D - 88 3 Pr od uc t F l ow 883--Class B Requirement Step Screen 883 Method 1. Internal Visual 2010, Test Condition B 100% 2. Temperature Cycling 1010, Test Condition C 100% 3. Constant Acceleration 2001, Test Condition D or E, Y1, Orientation Only 100% 4. Seal a. Fine b. Gross 1014 5. Visual Inspection 2009 100% 6. Pre-Burn-In Electrical Parameters In accordance with applicable Actel device specification 100% 7. Burn-in Test 1015, Condition D, 160 hours @ 125C or 80 hours @ 150C 100% 8. Interim (Post-Burn-In) Electrical Parameters In accordance with applicable Actel device specification 100% 9. Percent Defective Allowable 5% 10. Final Electrical Test In accordance with applicable Actel device specification, which includes a, b, and c: a. Static Tests (1) 25C (Subgroup 1, Table I) (2) -55C and +125C (Subgroups 2, 3, Table I) b. Functional Tests (1) 25C (Subgroup 7, Table I) (2) -55C and +125C (Subgroups 8A and 8B, Table I) 11. Note: 4 100% 100% All Lots 100% 5005 5005 100% 5005 5005 c. Switching Tests at 25C (Subgroup 9, Table I) 5005 100% External Visual 2009 100% When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method 2018 must be waived. Hi R e l S X -A F a m i ly F PG A s SX - A F am i l y A r ch i t e ct ur e The SX-A family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. P rog ra m ma ble Int er con nect E l em ent The SX-A family provides efficient use of silicon by locating the routing interconnect resources between the Metal 2 (M2) and Metal 3 (M3) layers (Figure 1). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actel's patented metal-to-metal programmable antifuse interconnect elements, which are embedded between the M2 and M3 layers. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the SX-A family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. Additionally, the interconnect (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. Routing Tracks Metal 3 Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Note: A54SX72A has 4 layers of metal with the antifuse between Metal 3 and Metal 4. Figure 1 * SX-A Family Interconnect Elements 5 Logi c Modul e Des ign The SX-A family architecture is described as a "sea-of-modules" architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. Actel's SX-A family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 2). The R-cell registers feature programmable clock polarity selectable on a register by register basis. This provides additional flexibility while allowing mapping of synthesized functions into the SX-A FPGA. The clock source for the R-cell can be chosen from either the hardwired clock or the routed clock. The C-cell implements a range of combinatorial functions up to 5 inputs (Figure 3 on page 7). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX-A architecture. An example of the improved flexibility enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. Chi p Ar chi tec tu re delivers the best register/logic mix for a wide variety of new and emerging applications. Mo dul e Or gan iz at io n Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 4 on page 7). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX-A devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. R out ing R eso urc es Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (Figure 5 and Figure 6 on page 8). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. The SX-A family's chip architecture provides a unique approach to module organization and chip routing that S0 Routed Data Input S1 PSETB Direct Connect Input D Q HCLK CLRB CLKA, CLKB, Internal Logic CKS Figure 2 * R-Cell 6 CKP Y Hi R e l S X -A F a m i ly F PG A s D0 D1 Y D2 D3 Sa Sb DB A0 B0 A1 B1 Figure 3 * C-Cell R-Cell S0 C-Cell D0 Routed Data Input S1 D1 PSETB Y D2 Direct Connect Input D Q Y D3 Sa Sb HCLK CLRB CLKA, CLKB, Internal Logic DB CKS CKP Cluster 1 A0 Cluster 1 Type 1 SuperCluster Cluster 2 B0 A1 B1 Cluster 1 Type 2 SuperCluster Figure 4 * Cluster Organization 7 DirectConnect * No antifuses * 0.1 ns routing delay FastConnect * One antifuse * 0.5 ns routing delay Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters Figure 5 * DirectConnect and FastConnect for Type 1 SuperClusters DirectConnect * No antifuses * 0.1 ns routing delay FastConnect * One antifuse * 0.5 ns routing delay Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters Figure 6 * DirectConnect and FastConnect for Type 2 SuperClusters 8 Hi R e l S X -A F a m i ly F PG A s FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.2 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. Actel's segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays. Actel's high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select MUX in each R-cell. This provides a fast propagation path for the clock signal, enabling the 5.3 ns clock-to-out (pin-to-pin) performance of the SX-A devices. The hardwired clock is tuned to provide clock skew as low as 0.29 ns. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the SX-A device. designers can achieve highly deterministic device performance. With SX-A devices, designers do not need to use complicated performance-enhancing design techniques such as the use of redundant logic to reduce fanout on critical nets or the instantiation of macros in HDL code to achieve high performance. I/O Modules Each I/O on an SX-A device can be configured as an input, an output, a tristate output, or a bidirectional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 5.3 ns. I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in SX-A FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. Hot S wa ppin g In addition, the A54SX72A device provides four quadrant clocks (QCLKA, QCLKB, QCLKC, QCLKD), which can be sourced from external pins or from internal logic signals within the device. Each of these clocks can individually drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. SX-A I/Os are specifically designed to be programmed to be hot swappable. During power-up/down (or partial up/down), all I/Os are tristated. VCCA and VCCI do not have to be stable during power up/down and they do not require a specific power up or power down sequence in order to avoid damage to the SX-A devices. After the SX-A device is plugged into an electrically active system, the device will not degrade the reliability of or cause damage to the host system. The devices' output pins are driven to a high impedance state until normal chip operating conditions are reached. O t he r A r c hi t ec tu ral Fe atu r e s P ower Requ ir em ent s Actel's SX-A family is implemented on a high-voltage twin-well CMOS process using 0.25 design rules (moving quickly to 0.22). The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ("on" state) resistance of 25 ohms with capacitance of 1.0 fF for low signal impedance. The SX-A family supports 2.5V/3.3V/5.0V mixed voltage operation and is designed to tolerate 5.0V inputs in each case (Table 1). Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced because of the small number of low resistance antifuses in the path. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest-power architecture FPGA available today. P erf orm a nce Table 1 * Supply Voltages T echno log y The combination of architectural features described above enables SX-A devices to operate with internal clock frequencies exceeding 284 MHz, enabling very fast execution of even complex logic functions. Thus, the SX-A family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an SX-A device with dramatic improvements in cost and time to market. Using timing-driven place-and-route tools, A54SX32A A54SX72A Maximum Maximum Input Output Tolerance Drive VCCA VCCI 2.5V 2.5V 5.0V 2.5V 2.5V 3.3V 5.0V 3.3V 2.5V 5.0V 5.0V 5.0V 9 Bou ndar y S can T es ti ng (BS T ) All SX-A devices are IEEE 1149.1 compliant. SX-A devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins in conjunction with the program fuse. The functionality of each pin is described in Table 2. Table 2 * Boundary Scan Pin Functionality Program Fuse Blown (Dedicated Test Mode) Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are dedicated BST pins TCK, TDI, TDO are flexible and may be used as I/Os No need for pull-up resistor for TMS Use a pull-up resistor of 10k3/4 on TMS S X- A P rob e C ir cui t Co nt rol P i ns The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS, and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 7 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. The TRST pin is equipped with an internal pull-up resistor. To remove the boundary scan state machine from the reset state during probing, it is recommended that TRST be left floating. D esi gn Con si der at ion s The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the Probe Circuitry. Channels In the dedicated test mode, TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10k3/4. TMS can be pulled LOW to initiate the test sequence. 18 The program fuse determines whether the device is in dedicated or flexible mode. The default (fuse not blown) is flexible mode. SX-A FPGA TDI TCK TMS Serial Connection Silicon Explorer II TDO PRA PRB Figure 7 * Probe Setup 10 Hi R e l S X -A F a m i ly F PG A s 2. 5 V / 3. 3 V / 5. 0 V O p er a t i n g C on di t i on s Abs ol ut e M axim u m Ra ti ngs 1 Symbol Parameter Re com m ende d Op er ati ng Con dit io ns Limits Units Parameter Military Units -55 to +125 C VCCI DC Supply Voltage -0.3 to +6.0 V Temperature Range1 VCCA DC Supply Voltage -0.3 to +3.0 V 3.3V Power Supply Tolerance 10 %VCC VI Input Voltage -0.5 to +5.5 V 5.0V Power Supply Tolerance 10 %VCC -0.5 to +VCCI + 0.5 V 2.5V Power Supply Tolerance 8 %VCC C Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. VO TSTG 2 Output Voltage Storage Temperature -65 to +150 Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. 2. The I/O source sink numbers refer to tristated inputs and outputs. Electrical Specifications Commercial Symbol Parameter VOH (IOH = -20uA) (CMOS) (IOH = -8mA) (TTL) Min. Military Max. Min. Max. Units (VCCI - 0.1) VCCI (VCCI - 0.1) VCCI V 2.4 VCCI 2.4 VCCI (IOH = -6mA) (TTL) VOL (IOL= 20uA) (CMOS) 0.10 (IOL = 12mA) (TTL) 0.50 V (IOL = 8mA) (TTL) 0.50 VIL Low Level Inputs 0.8 0.8 VIH High Level Inputs 2.0 IIL Input Leakage Current, VIN = VCCI or GND -10 10 -10 10 A IOZ 3-State Output Leakage Current, VOUT = VCCI or GND -10 10 -10 10 A tR, tF Input Transition Time tR, tF 10 10 ns CIO I/O Capacitance 10 10 pF ICC Standby Current 10 20 mA 2.0 V V 11 PC I C o m pl i a n ce f o r t h e S X - A Fa m i l y The SX-A family supports 3.3V and 5V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. DC Specifications (5.0V PCI Operation) Symbol Parameter VCCA VCCI Condition Min. Max. Units Supply Voltage for Array 2.3 2.7 V Supply Voltage for I/Os 4.75 5.25 V VIH 1 Input High Voltage 2.0 VCCI + 0.5 V VIL 1 Input Low Voltage -0.5 0.8 V IIH Input High Leakage Current VIN = 2.7 70 A IIL Input Low Leakage Current VIN = 0.5 -70 A VOH Output High Voltage IOUT = -2 mA VOL 2 Output Low Voltage 2.4 IOUT = 3 mA, 6 mA 3 CIN Input Pin Capacitance CCLK CLK Pin Capacitance 5 V 0.55 V 10 pF 12 pF Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull up must have 6 mA; the latter includes, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). 12 Hi R e l S X -A F a m i ly F PG A s AC S pec if i cat ion s (5.0 V P C I Op era ti on) Symbol Parameter Condition Min. 0 < VOUT 1.4 1 IOH(AC) 1.4 VOUT < 2.4 Switching Current High 1, 2 mA (-44 + (VOUT - 1.4)/0.024) mA Equation A on page 14 VOUT = 3.1 3 -142 VOUT 2.2 1 IOL(AC) ICL slewR slewF 2.2 > VOUT > 0.55 1 Switching Current Low VOUT = 0.71 3 Low Clamp Current -5 < VIN -1 Output Rise Slew Rate Output Fall Slew Rate mA 95 mA (VOUT/0.023) mA Equation B on page 14 0.71 > VOUT > 0 1, 3 (Test Point) Units -44 3.1 < VOUT < VCCI 1, 3 (Test Point) Max. 206 -25 + (VIN + 1)/0.015 mA mA 0.4V to 2.4V load 4 1 5 V/ns 2.4V to 0.4V load 4 1 5 V/ns Notes: 1. Refer to the V/I curves in Figure 8 on page 14. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 8 on page 14. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer VCC 10 pF 1k 1k 13 Figure 8 shows the 5.0V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 200.0 IOL MAX Spec IOL 150.0 100.0 Current (mA) IOL MIN Spec 50.0 0.0 0 -50.0 0.5 1 1.5 2 2.5 3 3.5 IOH MIN Spec 4 4.5 5 5.5 IOH MAX Spec -100.0 -150.0 -200.0 IOH Voltage Out (V) Figure 8 * 5.0V PCI Curve for SX-A Family Equation A IOH = 11.9 * (VOUT - 5.25) * (VOUT + 2.45) for VCCI > VOUT > 3.1V 14 Equation B IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V 6 Hi R e l S X -A F a m i ly F PG A s DC Specifications (3.3V PCI Operation) Symbol Parameter VCCA Condition Min. Max. Units Supply Voltage for Array 2.3 2.7 V VCCI Supply Voltage for I/Os 3.0 3.6 V VIH Input High Voltage 0.5VCCI VCCI + 0.5 V VIL Input Low Voltage -0.5 0.3VCCI V IIPU Input Pull-up Voltage1 IIL Input Leakage Current2 0 < VIN < VCCI VOH Output High Voltage IOUT = -500 A VOL Output Low Voltage IOUT = 1500 A CIN Input Pin Capacitance3 CCLK CLK Pin Capacitance 0.7VCCI V 10 0.9VCCI 5 A V 0.1VCCI V 10 pF 12 pF Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). 15 AC Specifications (3.3V PCI Operation) Symbol Parameter Condition Min. 0 < VOUT 0.3VCCI 1 IOH(AC) Switching Current High 0.3VCCI VOUT < 0.9VCCI 1 IOL(AC) mA Equation C on page 17 -32VCCI Switching Current Low 0.6VCCI > VOUT > 0.1VCCI 1 ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current VCCI + 4 > VIN VCCI + 1 Output Rise Slew Rate Output Fall Slew Rate mA 16VCCI mA (26.7VOUT) mA Equation D on page 17 0.18VCCI > VOUT > 0 1, 2 VOUT = 0.18VCC 2 slewF (-17.1 + (VCCI - VOUT)) 1 (Test Point) slewR mA VOUT = 0.7VCC 2 VCCI > VOUT 0.6VCCI Units -12VCCI 0.7VCCI < VOUT < VCCI 1, 2 (Test Point) Max. 38VCCI mA -25 + (VIN + 1)/0.015 mA 25 + (VIN - VCCI - 1)/0.015 mA 0.2VCCI to 0.6VCCI load 3 1 4 V/ns 0.6VCCI to 0.2VCCI load 3 1 4 V/ns Notes: 1. Refer to the V/I curves in Figure 9 on page 17. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. "Switching Current High" specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD, which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 9 on page 17. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. pin 1/2 in. max. output buffer VCC 10 pF 1k 16 1k Hi R e l S X -A F a m i ly F PG A s Figure 9 shows the 3.3V PCI V/I curve and the minimum and maximum PCI drive characteristics of the SX-A family. 150.0 IOL MAX Spec IOL Current (mA) 100.0 50.0 IOL MIN Spec 0.0 0 -50.0 0.5 1 1.5 2 2.5 3 3.5 4 IOH MIN Spec -100.0 IOH MAX Spec IOH -150.0 Voltage Out (V) Figure 9 * 3.3V PCI Curve for SX-A Family Equation C IOH = (98.0/VCCI) * (VOUT - VCCI) * (VOUT + 0.4VCCI) for VCCI > VOUT > 0.7 VCCI Equation D IOL = (256/VCCI) * VOUT * (VCCI - VOUT) for 0V < VOUT < 0.18 VCCI 17 Ju n ct i o n Te m p er a t u r e ( T J ) The temperature variable in the Designer Series software refers to the junction temperature, not the ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Equation 4, shown below, can be used to calculate junction temperature. Junction Temperature = T + Ta (4) Where: Ta = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient P = Power calculated from Estimating Power Consumption section ja = Junction to ambient of package. ja numbers are located in the Package Thermal Characteristics section below. P ac k ag e T h er m al C h ar a c t er i st i c s The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. The maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a CQFP 256-pin package at commercial temperature and still air is as follows: T = ja * P Max. junction temp. (C) - Max. ambient temp. (C) 150C - 70C Maximum Power Allowed = --------------------------------------------------------------------------------------------------------------------------------- = ----------------------------------- = 4.0W ja (C/W) 20C/W Pin Count jc ja Still Air ja 300 ft/min Units Ceramic Quad Flatpack (CQFP) 208 6.3 22 14 C/W Ceramic Quad Flatpack (CQFP) 256 6.2 20 10 C/W Package Type 18 Hi R e l S X -A F a m i ly F PG A s SX - A T i m i ng M o de l * Input Delays I/O Module tINY = 0.9 ns Internal Delays Predicted Routing Delays Combinatorial Cell Output Delays I/O Module tIRD2 = 0.7 ns tDHL = 4.3 ns tPD =1.3 ns tRD1 = 0.5 ns tRD4 = 1.2 ns tRD8 = 2.0 ns I/O Module tDHL = 4.3 ns Register Cell D Q Register Cell tRD1 = 0.5 ns D Q tRD1 = 0.5 ns tENZL = 3.9 ns tSUD = 0.7 ns tHD = 0.0 ns tRCO = 1.2 ns Routed Clock tRCO = 1.2 ns tRCKH = 3.9 ns (100% Load) FMAX = 161 MHz Hardwired Clock tHCKL = 1.6 ns FHMAX = 241 MHz *Values shown for A54SX32A-1, worst-case military conditions. Har dwi re d C loc k Ro ute d C loc k External Setup External Setup = tINY + tIRD1 + tSUD - tHCKL = 0.9 + 0.5 + 0.7 - 1.6 = 0.5 ns Clock-to-Out (Pin-to-Pin) = tINY + tIRD1 + tSUD - tRCKH = 0.9 + 0.5 + 0.7 - 3.9 = -1.8 ns Clock-to-Out (Pin-to-Pin) = tHCKL + tRCO + tRD1 + tDHL = tRCKH + tRCO + tRD1 + tDHL = 1.6 + 1.2 + 0.5 + 4.3 = 7.6 ns = 3.9 + 1.2 + 0.5 + 4.3 = 9.9 ns 19 O ut p u t B uf f e r D e l ay s E D VCC In 50% Out VOL PAD To AC test loads (shown below) TRIBUFF VCC 50% VOH GND En 1.5V 1.5V 50% VCC VCC GND 50% 1.5V Out En Out GND 10% VOL tDLH tENZL tDHL tENLZ GND 50% VOH 50% 90% 1.5V tENHZ tENZH A C T e st L oa d s Load 3 (Used to measure disable delays) Load 2 (Used to measure enable delays) Load 1 (Used to measure propagation delay) To the output under test VCC 35 pF To the output under test VCC GND R to VCC for tPZL R to GND for tPZH R = 1 k GND R to VCC for tPLZ R to GND for tPHZ R = 1 k To the output under test 5 pF 35 pF I n pu t B uf f er D e l ay s PAD INBUF C- C e l l D el a ys S A B Y Y VCC 3V In Out GND 1.5V 1.5V VCC 50% 0V S, A or B 50% 50% VCC Out GND 50% 50% tPD 50% tPD VCC Out 50% tPD 20 GND GND tPD 50% Hi R e l S X -A F a m i ly F PG A s C el l T i m i n g C h ar a c t er i st i c s Fl ip- Flo ps D Q PRESET CLK CLR (Positive edge triggered) tHD D tHP tHPWH, tRPWH tSUD CLK tRCO tHPWL, tRPWL Q tCLR tPRESET CLR tWASYN PRESET Ti m i ng C ha r a ct e r i s t i c s Long T r acks Timing characteristics for SX-A devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all SX-A family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with postlayout delays. Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three to five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to six percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout (FO=24) routing delays in the Timing Characteristics tables starting on page 22. Cr it ic al Net s and T ypi cal Ne ts Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to six percent of the nets in a design may be designated as critical, while 90 percent of the nets in a design are typical. T im in g D er at ing SX-A devices are manufactured with a CMOS process. Therefore, device performance varies according to temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s ( N or m ali z ed to W or st - Cas e Com m er ci al, T J = 70 C, V C C A = 2.3 V) Junction Temperature (TJ) VCCA -55 -40 0 25 70 85 125 2.3 0.75 .079 0.88 0.89 1.00 1.04 1.16 2.5 0.70 0.74 0.82 0.83 0.93 0.97 1.08 2.7 0.66 0.69 0.79 0.79 0.88 0.92 1.02 21 A 54 SX 3 2A T i m i ng C ha r a ct er i st i c s (W or st -C as e M il it ar y Cond it ion s, V C C A = 2.3 V , V C C I = 3.0 V, T J = 1 25 C) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 1.3 1.4 ns C-Cell Propagation Delays1 tPD Internal Array Module Predicted Routing Delays 2 tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.2 0.2 ns tRD1 FO=1 Routing Delay 0.5 0.6 ns tRD2 FO=2 Routing Delay 0.7 0.8 ns tRD3 FO=3 Routing Delay 0.9 1.0 ns tRD4 FO=4 Routing Delay 1.2 1.3 ns tRD8 FO=8 Routing Delay 2.0 2.4 ns tRD12 FO=12 Routing Delay 2.9 3.5 ns tRCO Sequential Clock-to-Q 1.2 1.4 ns tCLR Asynchronous Clear-to-Q 0.9 1.0 ns tPRESET Asynchronous Preset-to-Q 1.0 1.3 ns tSUD Flip-Flop Data Input Setup 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.6 1.9 ns tRECASYN Asynchronous Recovery 0.4 0.5 ns tHASYN Asynchronous Hold Time 0.4 0.5 ns R-Cell Timing Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 0.9 1.0 ns tINYL Input Data Pad-to-Y LOW 1.4 1.6 ns Input Module Predicted Routing Delays 2 tIRD1 FO=1 Routing Delay 0.5 0.6 ns tIRD2 FO=2 Routing Delay 0.7 0.8 ns tIRD3 FO=3 Routing Delay 0.9 1.0 ns tIRD4 FO=4 Routing Delay 1.2 1.3 ns tIRD8 FO=8 Routing Delay 2.0 2.4 ns tIRD12 FO=12 Routing Delay 2.9 3.5 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 22 Hi R e l S X -A F a m i ly F PG A s A 54 SX 3 2A T i m i n g C ha r a ct er i st i c s (Continued) (W or st -C as e M il it ar y Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 12 5C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH tHCKL Input LOW to HIGH (Pad to R-Cell Input) 1.9 2.2 ns Input HIGH to LOW (Pad to R-Cell Input) 1.6 2.0 ns tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns tHPWL Minimum Pulse Width LOW 2.1 2.4 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.2 4.2 0.2 4.9 ns ns 241 206 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.8 3.3 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 3.0 3.5 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 3.1 3.6 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 3.2 3.8 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 3.9 4.6 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 3.9 4.6 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tRCKSW Maximum Skew (Light Load) 1.3 1.5 ns tRCKSW Maximum Skew (50% Load) 2.2 2.2 ns tRCKSW Maximum Skew (100% Load) 2.0 2.3 ns 23 A 54 SX 3 2A T i m i ng C ha r a ct er i st i c s (Continued) (W or st -C as e M il it ar y Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 12 5C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 3.3V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 3.7 4.3 ns tDHL Data-to-Pad HIGH to LOW 3.6 4.2 ns tENZL Enable-to-Pad, Z to L 2.0 2.3 ns tENZH Enable-to-Pad, Z to H 2.4 2.9 ns tENLZ Enable-to-Pad, L to Z 3.8 4.5 ns tENHZ Enable-to-Pad, H to Z 4.4 5.1 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF 2 3.3V TTL Output Module Timing tDLH Data-to-Pad LOW to HIGH 4.9 5.7 ns tDHL Data-to-Pad HIGH to LOW 4.3 5.1 ns tENZL Enable-to-Pad, Z to L 3.9 4.6 ns tENZH Enable-to-Pad, Z to H 4.9 5.7 ns tENLZ Enable-to-Pad, L to Z 4.2 4.9 ns tENHZ Enable-to-Pad, H to Z 5.0 5.8 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF Note: 1. Delays based on 10 pF loading. 2. Delays based on 35 pF loading. 24 Hi R e l S X -A F a m i ly F PG A s A 54 SX 3 2A T i m i n g C ha r a ct er i st i c s (Continued) (W or st -C as e M il it ar y Cond it ion s V C C A = 2 .3V , V C C I = 4.75 V, T J = 1 25 C) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 5.0V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 4.7 5.0 ns tDHL Data-to-Pad HIGH to LOW 5.2 6.1 ns tENZL Enable-to-Pad, Z to L 2.0 2.3 ns tENZH Enable-to-Pad, Z to H 2.2 2.6 ns tENLZ Enable-to-Pad, L to Z 4.1 4.8 ns tENHZ Enable-to-Pad, H to Z 5.1 6.0 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF 2 5.0V TTL Output Module Timing tDLH Data-to-Pad LOW to HIGH 3.8 4.5 ns tDHL Data-to-Pad HIGH to LOW 4.8 5.6 ns tENZL Enable-to-Pad, Z to L 3.9 4.6 ns tENZH Enable-to-Pad, Z to H 3.5 4.2 ns tENLZ Enable-to-Pad, L to Z 5.1 6.0 ns tENHZ Enable-to-Pad, H to Z 6.4 7.3 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF Note: 1. Delays based on 50 pF loading. 2. Delays based on 35 pF loading. 25 A 54 SX 7 2A T i m i ng C ha r a ct er i st i c s (W or st -C as e M il it ar y Cond it ion s, V C C A = 2.3 V , V C C I = 3.0 V, T J = 1 25 C) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 1.3 1.5 ns C-Cell Propagation Delays1 tPD Internal Array Module Predicted Routing Delays 2 tDC FO=1 Routing Delay, Direct Connect 0.1 0.1 ns tFC FO=1 Routing Delay, Fast Connect 0.2 0.2 ns tRD1 FO=1 Routing Delay 0.5 0.6 ns tRD2 FO=2 Routing Delay 0.7 0.8 ns tRD3 FO=3 Routing Delay 0.9 1.0 ns tRD4 FO=4 Routing Delay 1.2 1.3 ns tRD8 FO=8 Routing Delay 2.0 2.4 ns tRD12 FO=12 Routing Delay 2.9 3.5 ns tRCO Sequential Clock-to-Q 1.1 1.4 ns tCLR Asynchronous Clear-to-Q 0.9 1.0 ns tPRESET Asynchronous Preset-to-Q 1.0 1.3 ns tSUD Flip-Flop Data Input Setup 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.6 1.9 ns tRECASYN Asynchronous Recovery 0.4 0.5 ns tHASYN Asynchronous Hold Time 0.4 0.5 ns R-Cell Timing Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 0.9 1.0 ns tINYL Input Data Pad-to-Y LOW 1.4 1.6 ns Input Module Predicted Routing Delays 2 tIRD1 FO=1 Routing Delay 0.5 0.6 ns tIRD2 FO=2 Routing Delay 0.7 0.8 ns tIRD3 FO=3 Routing Delay 0.9 1.0 ns tIRD4 FO=4 Routing Delay 1.2 1.3 ns tIRD8 FO=8 Routing Delay 2.0 2.4 ns tIRD12 FO=12 Routing Delay 2.9 3.5 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn , tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 26 Hi R e l S X -A F a m i ly F PG A s A 54 SX 7 2A T i m i n g C ha r a ct er i st i c s (Continued) (W or st -C as e M il it ar y Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 12 5C ) Dedicated (Hardwired) Array Clock Network Parameter Description tHCKH Input LOW to HIGH (Pad to R-Cell Input) Input HIGH to LOW (Pad to R-Cell Input) tHCKL `-1' Speed Min. Max. `Std' Speed Min. Max. Units 2.4 2.9 ns 2.1 2.6 ns tHPWH Minimum Pulse Width HIGH 2.1 2.4 ns tHPWL Minimum Pulse Width LOW 2.1 2.4 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.5 4.2 0.6 4.9 ns ns 241 206 MHz Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 4.2 4.9 ns Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 4.4 5.2 ns Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 5.1 6.0 ns Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 5.2 6.2 ns Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 7.0 8.1 ns Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 7.0 8.2 ns Routed Array Clock Networks tRCKH tRCKL tRCKH tRCKL tRCKH tRCKL tRPWH Min. Pulse Width HIGH 3.1 3.7 ns tRPWL Min. Pulse Width LOW 3.1 3.7 ns tRCKSW Maximum Skew (Light Load) 1.3 1.5 ns tRCKSW Maximum Skew (50% Load) 1.9 2.2 ns tRCKSW Maximum Skew (100% Load) 2.0 2.3 ns Quadrant Clock Networks tQCKH Input LOW to HIGH (Light Load) 2.3 2.7 ns tQCKL Input HIGH to LOW (Light Load) 2.6 3.1 ns tQCKH Input LOW to HIGH (50% Load) 2.4 2.8 ns tQCKL Input HIGH to LOW (50% Load) 2.7 3.2 ns tQCKH Input LOW to HIGH (100% Load) 2.6 3.0 ns tQCKL Input HIGH to LOW (100% Load) 2.9 3.4 ns tQCKSW Maximum Skew (Light Load) 0.3 0.4 ns tQCKSW Maximum Skew (50% Load) 0.4 0.5 ns tQCKSW Maximum Skew (100% Load) 0.5 0.6 ns 27 A 54 SX 7 2A T i m i ng C ha r a ct er i st i c s (Continued) (W or st -C as e M il it ar y Cond it ion s V C C A = 2. 3V , V C C I = 3 .0V , T J = 12 5C ) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 3.3V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 3.7 4.3 ns tDHL Data-to-Pad HIGH to LOW 3.6 4.2 ns tENZL Enable-to-Pad, Z to L 2.0 2.3 ns tENZH Enable-to-Pad, Z to H 2.4 2.9 ns tENLZ Enable-to-Pad, L to Z 3.8 4.5 ns tENHZ Enable-to-Pad, H to Z 4.4 5.1 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF 2 3.3V TTL Output Module Timing tDLH Data-to-Pad LOW to HIGH 4.9 5.7 ns tDHL Data-to-Pad HIGH to LOW 4.3 5.1 ns tENZL Enable-to-Pad, Z to L 3.9 4.6 ns tENZH Enable-to-Pad, Z to H 4.9 5.7 ns tENLZ Enable-to-Pad, L to Z 4.2 4.9 ns tENHZ Enable-to-Pad, H to Z 5.0 5.8 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF Notes: 1. Delays based on 10 pF loading. 2. Delays based on 35 pf loading. 28 Hi R e l S X -A F a m i ly F PG A s A 5 4S X 72 A Ti m i n g Ch a r ac t e r i s t i cs (Continued) (W or st -C as e M il it ar y Cond it ion s V C C A = 2 .3V , V C C I = 4.75 V, T J = 1 25 C) `-1' Speed Parameter Description Min. Max. `Std' Speed Min. Max. Units 5.0 V PCI Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 4.3 5.0 ns tDHL Data-to-Pad HIGH to LOW 5.2 6.2 ns tENZL Enable-to-Pad, Z to L 2.0 2.3 ns tENZH Enable-to-Pad, Z to H 2.2 2.6 ns tENLZ Enable-to-Pad, L to Z 4.1 4.8 ns tENHZ Enable-to-Pad, H to Z 5.1 5.9 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF 2 5.0V TTL Output Module Timing tDLH Data-to-Pad LOW to HIGH 3.8 4.5 ns tDHL Data-to-Pad HIGH to LOW 4.8 5.6 ns tENZL Enable-to-Pad, Z to L 3.9 4.6 ns tENZH Enable-to-Pad, Z to H 3.5 4.2 ns tENLZ Enable-to-Pad, L to Z 5.1 6.0 ns tENHZ Enable-to-Pad, H to Z 6.4 7.3 ns dTLH Delta LOW to HIGH 0.02 0.04 ns/pF dTHL Delta HIGH to LOW 0.05 0.05 ns/pF Notes: 1. Delays based on 50 pF loading. 2. Delays based on 35 pf loading. 29 Pi n D es c r i pt i on CLKA/B Clock A and B TCK Test Clock These pins are 3.3V/5.0V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. (For A54SX72A, these clocks can be configured as bidirectional.) Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 2 on page 10). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. QCLKA/B/C/D Quadrant Clock A, B, C, and D TDI These four pins are the quadrant clock inputs. They are 3.3V/5.0V PCI/TTL clock input for clock distribution networks. Each of these clock inputs can drive up to a quarter of the chip, or they can be grouped together to drive multiple quadrants. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. (These quadrant clocks are only for A54SX72A). Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 2 on page 10). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. TDO Test Data Input Test Data Output LOW supply voltage. Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 2 on page 10). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. HCLK TMS GND Ground Dedicated (Hardwired) Array Clock This pin is the 3.3V/5.0V PCI/TTL clock input for sequential modules. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, 3.3V PCI, or 5.0V PCI specifications. Unused I/O pins are automatically tristated by the Designer Series software. NC No Connection This pin is not connected to circuitry within the device. PRA, I/O Probe A The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB, I/O Probe B The Probe B pin is used to output data from any node within the device. This diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. 30 Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 2 on page 10). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 Specifications. TRST Boundary Scan (JTAG) Reset Pin Once configured as the Boundary Scan Reset pin, the TRST pin functions as an active low input to asynchronously initialize or reset the boundary scan circuit. The TRST is equipped with an internal pull-up resistor. This pin functions as an I/O when "Reserve JTAG Reset Pin" is not selected in Designer. V C CI Supply Voltage Supply voltage for I/Os. See Table 1 on page 9. V C CA Supply Voltage Supply voltage for Array. See Table 1 on page 9. Hi R e l S X -A F a m i ly F PG A s Pa c ka ge P i n A s si g nm e n t s 208-Pin CQFP (Top View) 208 207 206 205 204 203 202 201 200 164 163 162 161 160 159 158 157 Pin #1 Index 1 156 2 155 3 154 4 153 5 152 6 151 7 150 8 149 208-Pin CQFP 44 113 45 112 46 111 47 110 48 109 49 108 50 107 51 106 52 105 53 54 55 56 57 58 59 60 61 97 98 99 100 101 102 103 104 31 208- P in CQF P 32 Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O NC GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS VCCI I/O I/O I/O I/O I/O GND VCCA I/O I/O I/O I/O I/O I/O GND VCCA GND I/O TRST, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCA GND VCCR I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O NC I/O I/O I/O I/O I/O I/O I/O I/O QCLKA I/O PRB, I/O GND VCCA GND NC I/O HCLK VCCI QCLKB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O TDO, I/O I/O Hi R e l S X -A F a m i ly F PG A s 208- P in CQF P (Co nti nue d) Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND VCCR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB NC GND VCCA GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD I/O CLKA CLKB NC GND VCCA GND PRA, I/O VCCI I/O I/O QCLKC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O 33 Pa c ka ge P i n A s si g nm e n t s (continued) 256-Pin CQFP (Top View) 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 Pin #1 Index 1 192 2 191 3 190 4 189 5 188 6 187 7 186 8 185 256-Pin CQFP 56 137 57 136 58 135 59 134 60 133 61 132 62 131 63 130 64 129 65 66 67 68 69 70 71 72 73 34 121 122 123 124 125 126 127 128 Hi R e l S X -A F a m i ly F PG A s 256-Pin CQFP Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O GND TDI, I/O I/O I/O I/O I/O I/O I/O I/O I/O TMS I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI GND VCCA GND I/O I/O TRST, I/O I/O VCCA GND I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI I/O I/O I/O I/O I/O 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PRB, I/O GND VCCI GND VCCA I/O HCLK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKA PRB, I/O GND VCCI GND VCCA I/O HCLK I/O QCLKB I/O I/O I/O I/O I/O I/O 35 256-Pin CQFP (Continued) 36 Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TDO, I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O TDO, I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA VCCI GND VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 I/O GND NC GND VCCI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND NC GND VCCI VCCA I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCA GND GND I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O Hi R e l S X -A F a m i ly F PG A s 256-Pin CQFP (Continued) Pin Number A54SX32A Function A54SX72A Function Pin Number A54SX32A Function A54SX72A Function 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CLKA CLKB VCCI GND VCCR GND PRA, I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O QCLKD CLKA CLKB VCCI GND NC GND PRA, I/O I/O I/O VCCA I/O I/O QCLKC I/O 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TCK, I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCI I/O I/O I/O I/O I/O I/O TCK, I/O 37 Pa c ka ge M e ch an i c al D r a w i ng s 208- P in and 256 -P in CQF P (Ca vi ty Up ) Top View H D1 D2 No. 1 Ceramic Tie Bar L1 E2 F e b Side View A A1 Lid Heat Sink for CQ256 Notes: 1. Outside lead frame holes (from dimension H) are circular. 2. Seal ring and lid are connected to Ground. 3. Lead material is Kovar with minimum 50 microinches gold plate over nickel. 4. Packages are shipped unformed with the ceramic tie bar. 5. CQ256 has a Heat Sink on the back. 38 t C Lead Kovar E1 k Hi R e l S X -A F a m i ly F PG A s Cer am i c Qu ad Flat Pa ck CQFP 208 CQFP 256 Dimension Min. Nom. Max. Min. Nom. Max. A 2.20 2.44 2.67 2.19 2.44 2.69 A1 2.05 2.29 2.52 2.04 2.29 2.50 b 0.18 0.20 0.22 0.18 0.20 0.22 c 0.10 0.15 0.20 0.10 0.15 0.18 D1/E1 28.96 29.21 29.46 35.64 36.00 36.36 D2/E2 25.50 BSC 31.50 BSC e 0.50 BSC 0.50 BSC F 6.86 7.75 8.64 7.67 7.75 H 70.00 BSC 70.00 BSC K 65.90 BSC 65.90 BSC L1 t 74.60 75.00 75.40 7.83 74.62 75.00 75.38 0.38 0.51 0.64 Notes: 1. All dimensions are in millimeters. 2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance. 39 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44-(0)125-630-5600 Fax: +44-(0)125-635-5420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81-(0)3-3445-7671 Fax: +81-(0)3-3445-7668 5172148-0/4.00