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General Description
The MAX157/MAX159 low-power, 10-bit analog-to-digi-
tal converters (ADCs) are available in 8-pin µMAX and
DIP packages. Both devices operate with a single
+2.7V to +5.25V supply and feature a 7.4µs succes-
sive-approximation ADC, automatic power-down, fast
wake-up (2.5µs), an on-chip clock, and a high-speed,
3-wire serial interface.
Power consumption is only 3.2mW (VDD = +3.6V) at the
maximum sampling rate of 108ksps. At slower through-
put rates, the 0.2µA automatic shutdown further
reduces power consumption.
The MAX157 provides 2-channel, single-ended opera-
tion and accepts input signals from 0 to VREF. The
MAX159 accepts pseudo-differential inputs ranging
from 0 to VREF. An external clock accesses data
through the 3-wire serial interface, which is SPI™,
QSPI™, and MICROWIRE™ compatible.
Excellent dynamic performance and low power, com-
bined with ease of use and a small package size, make
these converters ideal for battery-powered and data
acquisition applications, or for other circuits with
demanding power-consumption and space require-
ments. For pin-compatible 12-bit upgrades, see the
MAX144/MAX145 data sheet.
Applications
Battery-Powered Systems Instrumentation
Portable Data Logging Test Equipment
Isolated Data Acquisition Medical Instruments
Process-Control Monitoring System Supervision
Features
♦Single-Supply Operation (+2.7V to +5.25V)
♦Two Single-Ended Channels (MAX157)
Single Pseudo-Differential Channel (MAX159)
♦Low Power
0.9mA (at 108ksps, +3V)
100µA (at 10ksps, +3V)
10µA (at 1ksps, +3V)
<0.2µA (power-down mode)
♦Internal Track/Hold
♦108ksps Sampling Rate
♦SPI/QSPI/MICROWIRE-Compatible 3-Wire
Serial Interface
♦Space-Saving 8-Pin µMAX Package
♦Pin-Compatible 12-Bit Upgrades Available
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
________________________________________________________________
Maxim Integrated Products
1
CS/SHDN
REFGND
1
2
8
7
SCLK
DOUT
( ) ARE FOR MAX159 ONLY.
CH0 (CH+)
CH1 (CH-)
VDD
µMAX/DIP
TOP VIEW
3
4
6
5
MAX157
MAX159
19-1388; Rev 0; 11/98
Pin Configuration
Ordering Information
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
*
Contact factory for availability.
±18 CERDIP*-55°C to +125°CMAX159BMJA ±0.58 CERDIP*-55°C to +125°CMAX159AMJA ±18 Plastic DIP-40°C to +85°CMAX159BEPA ±0.58 Plastic DIP-40°C to +85°CMAX159AEPA ±18 µMAX-40°C to +85°CMAX159BEUA
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±0.5
±1
±0.5
±1
±0.5
INL
(LSB)
8 CERDIP*
8 CERDIP*
8 Plastic DIP-40°C to +85°C
-55°C to +125°C
-55°C to +125°CMAX157BMJA
MAX157AMJA
MAX157BEPA 8 Plastic DIP
8 µMAX-40°C to +85°C
-40°C to +85°CMAX157AEPA
MAX157BEUA
8 µMAX
8 Plastic DIP0°C to +70°C
-40°C to +85°CMAX159AEUA
MAX159BCPA 8 Plastic DIP
8 µMAX
8 µMAX0°C to +70°C
0°C to +70°C
0°C to +70°CMAX159ACPA
MAX159BCUA
MAX159ACUA
8 µMAX
8 Plastic DIP0°C to +70°C
-40°C to +85°CMAX157AEUA
MAX157BCPA 8 Plastic DIP
8 µMAX
8 µMAX
PIN-
PACKAGE
TEMP.
RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°CMAX157ACPA
MAX157BCUA
MAX157ACUA
PART
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND..............................................................-0.3V to +6V
CH0, CH1 (CH+, CH-) to GND...................-0.3V to (VDD + 0.3V)
REF to GND................................................-0.3V to (VDD + 0.3V)
Digital Inputs to GND ...............................................-0.3V to +6V
DOUT to GND.............................................-0.3V to (VDD + 0.3V)
DOUT Sink Current ............................................................ 25mA
Continuous Power Dissipation (TA= +70°C)
µMAX (derate 4.1mW/°C above +70°C) ......................330mW
Plastic DIP (derate 9.09mW/°C above +70°C) ............727mW
CERDIP (derate 8.00mW/°C above +70°C).................640mW
Operating Temperature Ranges
MAX157/MAX159_C_A .......................................0°C to +70°C
MAX157/MAX159_E_A ....................................-40°C to +85°C
MAX157/MAX159_MJA................................. -55°C to +125°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (fIN (sine wave) = 10kHz, VIN = 2.5Vp-p, 108ksps, external fSCLK = 2.17MHz, CH- = GND for MAX159)
PARAMETER SYMBOL MIN TYP MAX UNITS
Gain Error (Note 3) ±2 LSB
Offset Error ±2 LSB
Differential Nonlinearity DNL ±0.5 LSB
±1
Gain Temperature Coefficient ±0.8 ppm/°C
Channel-to-Channel Offset
Matching ±0.02 LSB
Channel-to-Channel Gain
Matching ±0.02 LSB
Resolution RES 10 Bits
Relative Accuracy (Note 2) INL ±0.5 LSB
Signal-to-Noise Ratio plus
Distortion SINAD 66 dB
Total Harmonic Distortion
(including 5th-order harmonic) THD -70 dB
Spurious-Free Dynamic Range SFDR 70 dB
Channel-to-Channel Crosstalk -75 dB
Small-Signal Bandwidth 2.25 MHz
Full-Power Bandwidth 1.0 MHz
CONDITIONS
No missing codes over temperature
MAX15_B
External reference, VREF = 2.5V
fIN = 65kHz, VIN = 2.5Vp-p (Note 4)
-3dB rolloff
MAX15_A
MHz
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
CONVERSION RATE
0.5
ISINK = 16mA
Three-State Output Capacitance 15 pFCOUT CS/SHDN = VDD (Note 8)
Output High Voltage VDD - 0.5 VVOH
Output Low Voltage 0.4 VVOL ISINK = 5mA
ISOURCE = 0.5mA
Input Capacitance 15 pFCIN
Input Leakage Current ±1 µAIIN VIN = 0 or VDD
(Note 8)
Input Hysteresis 0.2 VVHYS
V
V
3.0
VDD > 3.6V
Input Low Voltage 0.8
VIL
Input High Voltage 2.0
VIH VDD ≤3.6V
Shutdown REF Input Current 0.01 10 µA
Input Resistance 18 25 kΩ
Input Current 100 140 µAVREF = 2.5V
Input Voltage Range (Note 7) 0 VDD
+ 50mV VVREF
Analog Input Voltage Range
(Note 6) 0V
REF VVIN
Input Capacitance 16 µACIN
Multiplexer Leakage Current ±0.01 ±1 µAOn/off-leakage current, VIN = 0 to VDD
Aperture Delay 25 ns
Aperture Jitter <50 ps
Serial Clock Frequency 0.1 2.17
fSCLK 05
MHz
External clock mode
Internal clock mode, for data transfer only
PARAMETER SYMBOL MIN TYP MAX UNITS
7.4 µsConversion Time (Note 5) tCONV 5 7
T/H Acquisition Time tACQ 2.5 µs
CONDITIONS
External clock, fSCLK = 2.17MHz, 16 clock
cycles per conversion
Internal clock
Three-State Output Leakage
Current ±10 µA
CS/SHDN = VDD
CONVERSION RATE
ANALOG INPUTS
EXTERNAL REFERENCE
DIGITAL INPUTS (CS/SHDN, SCLK) AND DIGITAL OUTPUT (DOUT)
MAX157/MAX159
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
TIMING CHARACTERISTICS (Figure 7)
(VDD = +2.7V to +5.25V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps),
CH- = GND for MAX159, TA= TMIN to TMAX, unless otherwise noted. Typical values are at TA= +25°C.)
Note 1: Tested at VDD = +2.7V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset nulled.
Note 4: The on channel is grounded; the sine wave is applied to off channel (MAX157 only).
Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from GND to VDD (MAX159 only).
Note 7: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 8: Guaranteed by design. Not subject to production testing.
Note 9: Measured as VFS(2.7V) - VFS(5.25V).
PARAMETER SYMBOL MIN TYP MAX UNITS
05
SCLK Clock Frequency fSCLK 0.1 2.17 MHz
SCLK Fall to Output Data Valid tDO 20 120 ns
215
CS/SHDN Fall to Output Enable
Wake-Up Time tWAKE 2.5 µs
tDV 120 ns
CS/SHDN Rise to Output
Disable tTR 120 ns
SCLK Pulse Width High tCH 50 ns
CONDITIONS
Internal clock, SCLK for data transfer only
(Note 8)
Internal clock, SCLK for data transfer only
External clock
CL= 100pF
External clock
CL= 100pF (Figure 1)
CL = 100pF (Figure 1)
ns
SCLK to CS/SHDN Setup tSCLKS 60
CS/SHDN Pulse Width tCS 60 ns
215
SCLK Pulse Width Low tCL 50 ns
Internal clock, SCLK for data transfer only
(Note 8)
External clock
POWER REQUIREMENTS
Power-Supply Rejection
(Note 9) PSR ±0.15 mVVDD = 2.7V to 5.25V, full-scale input
PARAMETER SYMBOL MIN TYP MAX UNITS
Positive Supply Voltage VDD +2.7 +5.25 V
CONDITIONS
Positive Supply Current IDD 0.9 2.0 mAOperating mode
Positive Supply Current IDD 0.2 5 µA
Shutdown, CS/SHDN = GND
POWER REQUIREMENTS
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________
5
500
700
900
1100
1300
1500
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX157/159 toc01
VDD (V)
SUPPLY CURRENT (µA)
VREF = VDD
RL = ∞
CL = 50pF
CODE = 1010101000
500
750
1000
1250
1500
-60 -20 0-40 20 40 60 80 100 120 140
SUPPLY CURRENT
vs. TEMPERATURE
MAX157/159 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
VREF = VDD
RL = ∞
CL = 50pF
CODE = 1010101000
10,000
0.10.1 1 100 1k 10k
10 100k
SUPPLY CURRENT
vs. SAMPLING RATE
1
MAX157/159 toc03
SAMPLING RATE (sps)
SUPPLY CURRENT (µA)
100
10
1000
VREF = VDD
CODE = 1010101000
CL = 50pF
0
400
200
600
800
1000
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX157/159 toc04
VDD (V)
SHUTDOWN CURRENT (nA)
VREF = VDD
0
0.05
0.10
0.15
0.20
-60 -10 40 90-35 15 65 140115
OFFSET ERROR vs. TEMPERATURE
MAX157/159 toc07
TEMPERATURE (°C)
OFFSET ERROR (LSB)
0
200
400
600
800
1000
-60 20 40-20 0-40 60 80 100 120 140
SHUTDOWN CURRENT
vs. TEMPERATURE
MAX157/159 toc05
TEMPERATURE (°C)
SHUTDOWN CURRENT (nA)
VREF = VDD
0
0.05
0.10
0.15
0.20
2.5 3.0 3.5 4.0 4.5 5.0 5.5
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX157/159 toc06
VDD (V)
OFFSET ERROR (LSB)
Typical Operating Characteristics
(VDD = +3.0V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
6 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VDD = +3.0V, VREF = 2.5V, 0.1µF capacitor at REF, fSCLK = 2.17MHz, 16 clocks/conversion cycle (108ksps); CH- = GND for
MAX159; TA = +25°C, unless otherwise noted.)
-0.2
0.1
-0.1
0
0.2
2.5 3.0 3.5 4.0 5.04.5 5.5
GAIN ERROR
vs. SUPPLY VOLTAGE
MAX157/159 toc08
VDD (V)
GAIN ERROR (LSB)
-0.2
0.1
0
-0.1
0.2
-60 15-35 -10 40 65 90 115 140
GAIN ERROR
vs. TEMPERATURE
MAX157/159 toc09
TEMPERATURE (°C)
GAIN ERROR (LSB)
0
0.15
0.10
0.05
0.20
-60 40-35 -10 15 90 11565 140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX157/159 toc12
TEMPERATURE (°C)
INL (LSB)
-0.03
-0.02
0
-0.01
0.02
0.01
0.03
0 500250 750 1000
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
MAX157/8 toc10
OUTPUT CODE
INL (LSB)
0
0.15
0.10
0.05
0.20
2.5 4.03.0 3.5 4.5 5.0 5.5
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX157/159 toc11
VDD (V)
INL (LSB)
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________ 7
Detailed Description
The MAX157/MAX159 analog-to-digital converters
(ADCs) use a successive-approximation conversion
(SAR) technique and on-chip track/hold (T/H) structure
to convert an analog signal to a serial, 10-bit digital out-
put data stream.
This flexible serial interface provides easy interface to
microprocessors (µPs). Figure 2 shows a simplified
functional diagram of the internal architecture for both
the MAX157 (2 channels, single-ended) and the
MAX159 (1 channel, pseudo-differential).
Single-Ended (MAX157) and Pseudo-
Differential (MAX159) Analog Inputs
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode (MAX157), both chan-
nels CH0 and CH1 are referred to GND and can be
connected to two different signal sources. Following the
power-on reset, the ADC is set to convert CH0. After
CH0 has been converted, CH1 will be converted, and
the conversions will continue to alternate between
channels. Channel switching is performed by toggling
the CS/SHDN pin. Conversions can be performed on
the same channel by toggling CS/SHDN twice between
conversions. If only one channel is required, CH0 and
CH1 may be connected together; however the output
data will still contain the channel identification bit
(before the MSB).
For the MAX159, the input channels form a single differ-
ential channel pair (CH+, CH-). This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side IN- must remain stable
within ±0.5LSB (±0.1LSB for optimum results) with
respect to GND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans from when CS/SHDN falls to
the falling edge of the second clock cycle (external
clock mode) or from when CS/SHDN falls to the first
falling edge of SCLK (internal clock mode). At the end
of the acquisition interval, the T/H switch opens, retain-
ing charge on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). This unbalances node ZERO at the
comparator’s positive input.
6k CL
DOUT
a) HIGH-Z TO V0H, V0L TO V0H, AND VOH TO HIGH-Z
6k
CL
DOUT
GNDGND
VDD
b) HIGH-Z TO V0L, V0H TO V0L, AND VOL TO HIGH-Z
Figure 1. Load Circuits for Enable and Disable Time
Pin Description
NAME FUNCTION
1 VDD Positive Supply Voltage, +2.7V to +5.25V
2 CH0 (CH+) Analog Input, MAX157: Single-Ended (CH0); MAX159: Differential (CH+).
PIN
3 CH1 (CH-) Analog Input, MAX157: Single-Ended (CH1); MAX159: Differential (CH-).
4 GND Analog and Digital Ground
8 SCLK Serial Clock Input. DOUT changes on the falling edge of SCLK.
7 DOUT Serial Data Output. Data changes state at SCLK’s falling edge. High impedance when CS/SHDN is high.
6CS/SHDN Active-Low Chip-Select Input, Active-High Shutdown Input. Pulling CS/SHDN high puts chip into
shutdown with a maximum current of 5µA.
5 REF External Reference Voltage Input. Sets analog voltage range. Bypass with a 100nF capacitor close to the
part.
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
8 _______________________________________________________________________________________
The capacitive digital-to-analog converter (DAC)
adjusts during the remainder of the conversion cycle
to restore node ZERO to 0V within the limits of 10-bit
resolution. This action is equivalent to transferring a
16pF · [(VIN+) - (VIN-)] charge from CHOLD to the bina-
ry-weighted capacitive DAC, which in turn forms a digi-
tal representation of the analog input signal.
Track/Hold
The ADC’s T/H stage enters its tracking mode on the
falling edge of CS/SHDN. For the MAX157 (single-
ended inputs), IN- is connected to GND and the con-
verter samples the positive (“+”) input. For the MAX159
(pseudo-differential inputs), IN- connects to the nega-
tive input (“-”), and the difference of [(VIN+) - (VIN-)] is
sampled. At the end of the conversion, the positive
input connects back to IN+ and CHOLD charges to the
input signal.
The time required for the T/H stage to acquire an input
signal is a function of how fast its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ = 7(RS+ RIN)CIN
where RSis the source impedance of the input signal,
RIN (9kΩ) is the input resistance, and CIN (16pF) is the
input capacitance of the ADC. Source impedances
below 4kΩhave no significant impact on the AC perfor-
mance of the MAX157/MAX159.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor forms
an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX157/MAX159 T/H stage offers both a 2.25MHz
small-signal and a 1MHz full-power bandwidth, which
makes it possible to use the parts for digitizing high-
speed transients and measuring periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended. Most
aliasing problems can be fixed easily with an external
resistor and a capacitor. However, if DC precision is
required, it is usually best to choose a continuous
or switched-capacitor filter, such as the MAX7410/
MAX7414 (Figure 4). Their Butterworth characteristic
generally provides the best compromise (with regard to
rolloff and attenuation) in filter configurations, is easy to
design, and provides a maximally flat passband re-
sponse.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and GND, allow each input channel to
swing within GND - 300mV to VDD + 300mV without
damage. However, for accurate conversions both
inputs must not exceed VDD + 50mV or be less than
GND - 50mV.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 4mA.
MAX157
MAX159
10+2 BIT
SAR
ADC
SCLK
IN OUT
ANALOG
INPUT
MUX
(2 CHANNEL)
CH0
(CH+)
CH1
(CH-)
REF
( ) ARE FOR MAX159
T/H
CONTROL
LOGIC
SCLK
CS/SHDN
INTERNAL
CLOCK
OUTPUT
REGISTER DOUT
Figure 2. MAX157/MAX159 Simplified Functional Diagram
CH0
(CH+)
CH1
(CH-)
GND
CSWITCH TRACK
T/H
RIN
9k
HOLD
CAPACITIVE DAC
CONTROL
LOGIC
REF
ZERO
TO SAR
( ) ARE FOR MAX159
COMPARATOR
–+
CHOLD
16pF
SINGLE-ENDED MODE: CHO, CH1 = IN+; GND = IN-
DIFFERENTIAL MODE: CH+ = IN+; CH- = IN-
INPUT
MUX
Figure 3. Analog Input Channel Structure
Selecting Clock Mode
To start the conversion process on the MAX157/
MAX159, pull CS/SHDN low. At CS/SHDN’s falling
edge, the part wakes up, the internal T/H enters track
mode, and a conversion begins. In addition, the state of
SCLK at CS/SHDN’s falling edge selects internal (SCLK
= high) or external (SCLK = low) clock mode.
Internal Clock (f
SCLK
< 100kHz or f
SCLK
> 2.17MHz)
In internal clock mode, the MAX157/MAX159 run from
an internal, laser-trimmed oscillator to within 20% of the
2MHz specified clock rate. This releases the system
microprocessor from running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
5MHz. Operating the MAX157/MAX159 in internal clock
mode is necessary for serial interfaces operating with
clock frequencies lower than 100kHz or greater than
2.17MHz. Select internal clock mode (Figure 5) by hold-
ing SCLK high during a high/low transition of CS/SHDN.
The first SCLK falling edge samples the data and initi-
ates a conversion using the integrated on-chip oscilla-
tor. After the conversion, the oscillator shuts off and
DOUT goes high, signaling the end of conversion
(EOC). Data can then be read out with SCLK.
External Clock (f
SCLK
= 100kHz to 2.17MHz)
External clock mode (Figure 6) is selected by transition-
ing CS/SHDN from high to low while SCLK is low. The
external clock signal not only shifts data out, but also
drives the analog-to-digital conversion. The input is
sampled and conversion begins on the falling edge of
the second clock pulse. Conversion must be completed
within 140µs to prevent degradation in the conversion
results caused by droop on the T/H capacitors. External
clock mode provides the best throughput for clock fre-
quencies between 100kHz and 2.17MHz.
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
_______________________________________________________________________________________ 9
Figure 4. Analog Input with Anti-Aliasing Filter Structure
DOUT D7D8MSBCHID11EOC
SAMPLING INSTANT
HIGH-Z D6 D5 D4 D3 D2 D1 D0 S1 S0 HIGH-Z
SCLK 6789101112345 1213141516
tCONV
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE ACTIVE
CS/SHDN
Figure 5. Internal Clock Mode Timing
SHDN
OUT
2CLK
REF EXTERNAL
REFERENCE
CS/SHDN
DOUT
2
3
8
4
µP/µC
MAX7410
MAX7414
CH0 VDD
VDD
VDD
GNDOS GNDCOM
0.01µF
0.1µF
470Ω
0.01µF
CH1
IN
fCORNER = 15kHz
7
4
5
5
7
6
8
1
1
63
SCLK
MAX157
1.5MHz
CLOCK
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
10 ______________________________________________________________________________________
Output Data Format
Table 1 illustrates the 16-bit, serial data-stream output
format for both the MAX157 and MAX159. The first three
bits are always logic high (including the EOC bit for
internal clock mode), followed by the channel identifica-
tion (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1 for
MAX159), the 10 bits of data in MSB first format, and
two sub-LSB bits (S1 and S0). After the last bit has been
read out, additional SCLK pulses will clock out trailing
zeros. DOUT transitions on the falling edge of SCLK.
The output remains high impedance when CS/SHDN is
high.
External Reference
An external reference is required for both the MAX157
and MAX159. At REF, the DC input resistance is a mini-
mum of 18kΩ. During a conversion, a reference must
be able to deliver 250µA of DC load current and have
an output impedance of 10Ωor less. Use a 0.1µF
bypass capacitor for best performance. The reference
input structure allows a voltage range of 0 to (VDD +
50mV) although noise levels will decrease effective res-
olution at lower reference voltages.
Automatic Power-Down Mode
Whenever the MAX157/MAX159 are not selected
(CS/SHDN = VDD), the parts enter their shutdown mode.
In shutdown all internal circuitry is turned off, which
reduces the supply current to typically less than 0.2µA.
With an external reference stable to within 1LSB, the
wake-up time is 2.5µs. If the external reference is not sta-
ble within 1LSB, the wake-up time must be increased to
allow the reference to stabilize.
Applications Information
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization error only and results
directly from the ADC’s resolution (N bits):
SNR(MAX) = (6.02 ·N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
DOUT D7D8MSBCHID
SAMPLING INSTANT
HIGH-Z D6 D5 D4 D3 D2 D1 D0 S1 S0 HIGH-Z
SCLK 6789101112345 1213141516
tWAKE
(tACQ)
tCS
POWER
DOWN
ACTIVE ACTIVE
CS/SHDN
Figure 6. External Clock Mode Timing
• • •
• • •
• • •
CS/SHDN
SCLK
DOUT
tCL
tDV
HIGH-Z HIGH-Z
tCH tCS
tDO tTR
tSCLKS
Figure 7. Detailed Serial-Interface Timing Sequence
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise (which includes all
spectral components minus the fundamental), the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
Signal-to-noise plus distortion is the ratio of the funda-
mental input frequency’s RMS amplitude to RMS equiv-
alent of all other ADC output signals:
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the effective number of bits as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first five harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V1is the fundamental amplitude and V2through
V5are the amplitudes of the 2nd through 5th-order har-
monics.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the fundamental
(maximum signal component) to the RMS value of the
next largest spurious component, excluding DC offset.
Connection to Standard Interfaces
The MAX157/MAX159 interface is fully compatible with
SPI/QSPI and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s seri-
al interface as master so that the CPU generates the
serial clock for the MAX157/MAX159. Select a clock fre-
quency from 100kHz to 2.17MHz (external clock mode).
1) Use a general-purpose I/O line on the CPU to pull
CS/SHDN low while SCLK is low.
2) Wait for the minimum wake-up time (tWAKE) speci-
fied before activating SCLK.
3) Activate SCLK for a minimum of 16 clock cycles. The
first falling clock edge will generate a serial data-
stream of three leading ones, followed by the chan-
nel identification, the MSB of the digitized input
signal, and two sub-bits. DOUT transitions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing char-
acteristic. Data should be clocked into the µP on
SCLK’s rising edge.
4) Pull CS/SHDN high at or after the 16th falling clock
edge. If CS/SHDN remains low, trailing zeros will be
clocked out after the sub-bits.
5) With CS/SHDN high, wait at least 60ns (tCS), before
starting a new conversion by pulling CS/SHDN low.
A conversion can be aborted by pulling CS/SHDN
high before the conversion ends; wait at least 60ns
before starting a new conversion.
Data can be output either in two 8-bit sequences or
continuously. The bytes will contain the result of the
conversion padded with three leading ones, the chan-
nel identification before the MSB, and two trailing sub-
bits. If the serial clock hasn’t been idled after the last
sub-bit (S0) and CS/SHDN is kept low, DOUT sends
trailing zeros.
SPI and MICROWIRE Interface
When using SPI (Figure 8a) or MICROWIRE (Figure 8b)
interfaces, set CPOL = 0 and CPHA = 0. Conversion
begins with a falling edge on CS/SHDN (Figure 8c). Two
consecutive 8-bit readings are necessary to obtain the
entire 10-bit result from the ADC. DOUT data transitions
on the serial clock’s falling edge and is clocked into the
µP on SCLK’s rising edge. The first 8-bit data stream
contains three leading ones, followed by channel identi-
fication and the first four data bits starting with the MSB.
The second 8-bit data stream contains the remaining
bits, D5 through D0, and the sub-bits S1 and S0.
THD = 20 log V + V + V + V
V
22324252
12
⋅
()
SINAD(dB) = 20 log Signal
(Noise + Distortion)
RMS RMS
⋅
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 11
Table 1. Serial Output Data Stream for Internal and External Clock Mode
D0D1D2D3D4D5D6D7D8D9CHID11EOCDOUT (Internal Clock) 1413121110987654321SCLK CYCLE
D0D1D2D3D4D5D6D7D8D9CHID111DOUT (External Clock) S0S1 S0S1 1615
MAX157/MAX159
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX157/MAX159 supports a maxi-
mum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a
can be programmed to perform a conversion on each
of the two channels for the MAX157.
Figure 9b shows the QSPI interface timing.
PIC16 with SSP Module
and PIC17 Interface
The MAX157/MAX159 are compatible with a PIC16/
PIC17 microcontroller (µC), using the synchronous seri-
al port (SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master by initializing its synchronous serial
port control register (SSPCON) and synchronous serial
port status register (SSPSTAT) to the bit patterns shown
in Tables 2 and 3.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit readings (Figure
10b) are necessary to obtain the entire 10-bit result
from the ADC. DOUT data transitions on the serial
clock’s falling edge and is clocked into the µC on
SCLK’s rising edge. The first 8-bit data stream contains
three leading ones, the channel identification, and the
first four data bits starting with the MSB. The second 8-
bit data stream contains the remaining bits, D5 through
D0, and the two sub-bits S1 and S0.
Layout, Grounding, and Bypassing
For best performance use printed circuit boards
(PCBs), wire-wrap configurations are not recommend-
ed, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t layout digital sig-
nal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
12 ______________________________________________________________________________________
HIGH-Z
SAMPLING
INSTANT
D9CHID D8 D7 D6 D5
12345678 109111213141516
D4 D3 D2 D1 D0 S0S1
DOUT*
CS/SHDN
SCLK
1ST BYTE READ 2ND BYTE READ
MSB LSB
*WHEN CS/SHDN IS HIGH, DOUT = HIGH -Z
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
CS/SHDN
SCLK
DOUT
CS
SCK
MISO VDD
SS
QSPI
MAX157
MAX159
Figure 9a. QSPI Connections
MAX157
MAX159
CS/SHDN
SCLK
DOUT
I/O
SK
SI
MICROWIRE
CS/SHDN
SCLK
DOUT
I/O
SCK
MISO VDD
SS
SPI
MAX157
MAX159
Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections
star-point (Figure 11) connecting the two ground sys-
tems (analog and digital). For lowest-noise operation,
ensure the ground return to the star ground’s power
supply is low impedance and as short as possible.
Route digital signals far away from sensitive analog and
reference inputs.
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass VDD to the star ground with a network
of two parallel capacitors, 0.1µF and 1µF, located as
close as possible to the power supply pin of the
MAX157/MAX159. Minimize capacitor lead length for
best supply-noise rejection and add an attenuation
resistor (10Ω) if the power supply is extremely noisy.
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 13
SCK
SDI
GND GND
I/O
SCLK
DOUT
CS/SHDN
VDD VDD
MAX157
MAX159
PIC16/PIC17
CHID D9 D8 D7 D6
1 2 3 4 5 6 7 8 9 10111213141516
D5 D4 D3 D2 D1 HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ 2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z MSB LSB
D0 S1 S0
Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
CHID D9 D8 D7 D6
1 2 3 4 5 6 7 8 9 10111213141516
D5 D4 D3 D2 D1 HIGH-Z
DOUT
CS/SHDN
SCLK
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z MSB LSB
D0 S1 S0
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
+3V GND+3V
POWER SUPPLIES
DGND+3V
GNDVDD
DIGITAL
CIRCUITRY
MAX157
MAX159
R* = 10Ω
1µF
0.1µF
* OPTIONAL FILTER RESISTOR
Figure 11. Power-Supply Bypassing and Grounding
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
14 ______________________________________________________________________________________
Table 3. Detailed SSPSTAT Register Content
Table 2. Detailed SSPCON Register Content
CONTROL BIT MAX157/MAX159
SETTINGS SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
WCOL Bit 7 X Write Collision Detection Bit
SSPOV Bit 6 X Receive Overflow Detect Bit
SSPEN Bit 5 1 Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins.
CKP Bit 4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 Bit 3 0
SSPM2 Bit 2 0
SSPM1 Bit 1 0
SSPM0 Bit 0 1
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
fCLK = fOSC / 16.
X = Don’t care
X = Don’t care
D/A
CONTROL BIT MAX157/MAX159
SETTINGS SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
Bit 5 X Data Address Bit
P Bit 4 X Stop Bit
S Bit 3 X
R/W
SMP Bit 7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE Bit 6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Bit 2 X
UA Bit 1 X
BF Bit 0 X
Start Bit
Buffer Full Status Bit
Update Address
Read/Write Bit Information
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
______________________________________________________________________________________ 15
Package Information
Chip Information
TRANSISTOR COUNT: 2,058
SUBSTRATE CONNECTED TO GND
8LUMAXD.EPS
MAX157/MAX159
+2.7V, Low-Power, 2-Channel,
108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
PDIPN.EPS
Package Information (continued)
