74LVC1G86-Q100 2-input EXCLUSIVE-OR gate Rev. 2 -- 12 December 2016 Product data sheet 1. General description The 74LVC1G86-Q100 provides the 2-input EXCLUSIVE-OR function. Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 1.65 V to 5.5 V High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options 74LVC1G86-Q100 Nexperia 2-input EXCLUSIVE-OR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC1G86GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 74LVC1G86GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753 4. Marking Table 2. Marking codes Type number Marking[1] 74LVC1G86GW-Q100 VH 74LVC1G86GV-Q100 V86 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram % $ < PQD Fig 1. PQD Logic symbol Fig 2. IEC logic symbol % < $ Fig 3. PQD Logic diagram 74LVC1G86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 12 December 2016 (c) Nexperia B.V. 2017. All rights reserved 2 of 13 74LVC1G86-Q100 Nexperia 2-input EXCLUSIVE-OR gate 6. Pinning information 6.1 Pinning /9&*4 % $ *1' 9&& < DDD Fig 4. Pin configuration SOT353-1 and SOT753 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output VCC 5 supply voltage 7. Functional description Table 4. Function table[1] Input Output A B Y L L L L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level. 74LVC1G86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 12 December 2016 (c) Nexperia B.V. 2017. All rights reserved 3 of 13 74LVC1G86-Q100 Nexperia 2-input EXCLUSIVE-OR gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions IO output current ICC supply current IGND ground current Ptot total power dissipation Tstg storage temperature Max Unit 0.5 +6.5 V 50 - 0.5 +6.5 V mA VI < 0 V [1] mA - 50 Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA - +100 mA 100 - mA - 250 mW 65 +150 C VO > VCC or VO < 0 V output voltage VO Min VO = 0 V to VCC Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature t/V input transition rise and fall rate 74LVC1G86_Q100 Product data sheet Min Typ Max Unit 1.65 - 5.5 V 0 - 5.5 V Active mode 0 - VCC V VCC = 0 V; Power-down mode 0 - 5.5 V 40 - +125 C VCC = 1.65 V to 2.7 V - - 20 ns/V VCC = 2.7 V to 5.5 V - - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 2 -- 12 December 2016 (c) Nexperia B.V. 2017. All rights reserved 4 of 13 74LVC1G86-Q100 Nexperia 2-input EXCLUSIVE-OR gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH 40 C to +85 C Conditions VCC = 1.65 V to 1.95 V VOH HIGH-level output voltage LOW-level output voltage Max Min Max 0.65VCC - - 0.65VCC - V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V - - 0.35VCC - 0.35VCC V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC V VCC 0.1 - - VCC 0.1 - V 1.2 - - 0.95 - V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V VOL Min Unit VCC = 2.3 V to 2.7 V LOW-level input VCC = 1.65 V to 1.95 V voltage VCC = 2.3 V to 2.7 V VIL 40 C to +125 C Typ[1] IO = 8 mA; VCC = 2.3 V 1.9 - - 1.7 - V IO = 12 mA; VCC = 2.7 V 2.2 - - 1.9 - V IO = 24 mA; VCC = 3.0 V 2.3 - - 2.0 - V IO = 32 mA; VCC = 4.5 V 3.8 - - 3.4 - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 - 0.10 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.30 - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.40 - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.55 - 0.80 V - 0.1 1 - 1 A VI = VIH or VIL II input leakage current IOFF power-off VCC = 0 V; VI or VO = 5.5 V leakage current - 0.1 2 - 2 A ICC supply current VI = 5.5 V or GND; IO = 0 A; VCC = 1.65 V to 5.5 V - 0.1 4 - 4 A ICC additional supply current per pin; VCC = 2.3 V to 5.5 V; VI = VCC 0.6 V; IO = 0 A - 5 500 - 500 A CI input capacitance VCC = 3.3 V; VI = GND to VCC - 5 - - - pF [1] VI = 5.5 V or GND; VCC = 0 V to 5.5 V All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 74LVC1G86_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 -- 12 December 2016 (c) Nexperia B.V. 2017. All rights reserved 5 of 13 74LVC1G86-Q100 Nexperia 2-input EXCLUSIVE-OR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 6. Symbol Parameter 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.0 3.7 9.9 1.0 13.0 ns VCC = 2.3 V to 2.7 V 0.5 2.5 5.5 0.5 7.0 ns VCC = 2.7 V 0.5 2.8 5.8 0.5 7.5 ns VCC = 3.0 V to 3.6 V 0.5 2.3 5.0 0.5 6.5 ns VCC = 4.5 V to 5.5 V 0.5 1.9 4.0 0.5 5.5 ns - 25 - - - pF power dissipation capacitance CPD [3] VI = GND to VCC VCC = 3.3 V [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] [2] propagation delay A, B to Y; see Figure 5 tpd 40 C to +125 C Unit Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. 12. Waveforms $%LQSXW 90 W3+/