HOTLink Transmitter/Receive
r
CY7B92
3
CY7B93
3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-02017 Rev. *C Revised March 25, 2003
Features
• Fibre-Channel-compliant
•IBM ESCON
-compliant
• DVB-ASI-compliant
• ATM-compliant
• 8B/10B-coded or 10-bit unencoded
• Standard HOTLink: 160–330 Mbps
• High-speed HOTLink: 160–400 Mbps for high-speed
applications
• Low-speed HOTLink: 150–160 Mbps for low-cost fiber
applications
• TTL synchronous I/O
• No external phase locked-loop (PLL) components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
• Built-in Self-Test (BIST)
• Single +5V supply
• 28-pin SOIC/PLCC/LCC
•0.8m BiCMOS
Functional Description
The CY7B923 HOTLink‚ Transmitter and CY7B933 HOTLink
Receiver are point-to-point communications building blocks
that transfer dat a over high-spe ed serial lin ks (fiber, coax, and
twisted pair). Standard HOTLink data rates range from
160-330 Mbits/second. Higher speed HOTLink is also
availa ble for high -speed app licat ions (160-4 00 Mbit s/secon d),
as well as for those low-Cost applications HOTLink-155
(150 -160 Mbi ts/se cond op erations). Figure 1 i llustrates typic al
connections to host systems or controllers.
Eight bits of user data or protocol information are loaded into
the HOTLink transmitter and are encoded. Serial data is
shift e d ou t of t he thr e e di ffe re nt i al posi t iv e ECL (PE CL ) se ria l
ports at the bit rate (which is ten times the byte rate).
The HOTLink receiver accepts the serial bit stream at its d iffer-
ential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information
necessary for data reconstruction. The bit stream is deseri-
alized, decoded, and checked for transmission errors.
Recovered bytes are presented in parallel to the receiving host
along with a byte-rate clock.
The 8B/10B encod er/dec oder c an b e disabl ed i n sy stems that
already encode or scramble the transmitted data. I/O signals
are available to create a seamless interface with both
asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A BIST pattern generator and checker allows
testing of the transmitter, receiver, and the connecting link as
a part of a system di agnostic check.
HOTLink devices are ideal for a variety of applications where
a parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
work stations , ser vers , ma ss stor age, and v ideo tra nsmiss ion
equipment.
CY7B923 Transmitter
INPUT REGISTER
D0−7
(Db−h)
SC/D(Da)
SVS(Dj)
ENABLE
ENCODER
SHIFTER
OUTA
OUTB
OUTC
FOTO
CKW
CLOCK
GENERATOR
ENAENNRP
TEST
LOGIC
MODE
BISTEN
CY7B933 Receiver LogicBlockDiagram
RF
A/B
INA+
INB(INB+)
SO
REFCLK
MODE
BISTEN
PECL
TTL
TEST
LOGIC
CLOCK
SYNC
CKR RDY
SC/D(Q
a
)
RVS(Qj)
Q0−7
(Qb−h)
OUTPUT
REGISTER
DECODER
DECODER
REGISTER
SHIFTER
FRAMER
DATA
INA−
SI(INB−)
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Figure 1. HOTLink System Connections
PROTOCOL
LOGIC
HOST
TRANSMIT
MESSAGE
BUFFER
7B923
TRANSMITTER
SERIAL LINK
7B933
RECEIVER
RECEIVE
MESSAGE
BUFFER
PROTOCOL
LOGIC
HOST
CY7B923 Transmitter Pin Configurations
SC/D(Da)
SVS(Dj)
OUTB−
OUTC−
OUTC+
VCCN
BISTEN
GND
MODE
RP
VCCQ
(Dh)D
7
(Dg)D 6
(Df)D 5
(Di)D 4
OUTB+
OUTA+
OUTA−
FOTO
ENN
ENA
VCCQ
CKW
GND
D0(Db)
D2(Dd)
D1(Dc)
D3(De)
43 12 28
8
9
7
6
5
22
21
23
24
25
1213 1514 16
PLCC/LCC
Top View
10
11 20
19
2726
1718
FOTO
ENN
ENA
VCCQ
CKW
GND
SC/D(D a)
BISTEN
GND
MODE
RP
VCCQ
SVS(Dj)
(Dh)D 7
6
DV
OUTC+
OUTC
−
OUTB+
OUTA+
OUTA
−
OUTB
−
SOIC
Top View
7B923
7B923
5
D
4
D
3
D
2
D
1
D
0
D
CCN
d
(D )
e
(D )
i
(D )
f
(D )
g
(D )
c
(D )
b
(D )
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
CY7B933 Receiver Pin Configurations
SC/D (Qa)
INA−
INA+
A/B
BISTEN
RF
GND
RDY
GND
VCCN
RVS(Qj)
(Qh)Q
7
(Qg)Q
6
(Qf)Q
5
(Qi)Q
4
INB(INB+)
SI(INB−)
MODE
REFCLK
VCCQ
SO
CKR
VCCQ
GND
SC/D (Qa)
Q0(Qb)
Q2(Qd)
Q1(Qc)
Q3(Qe)
43 12 28
8
9
7
6
5
22
21
23
24
25
1213 1514 16
PLCC/LCC
Top View
10
11 20
19
2726
1718
REFCLK
VCCQ
SO
CKR
VCCQ
GND
RF
GND
RDY
GND
VCCN
RVS(Qj)
(Qh)Q
7
Q
Q
Q
Q
Q
Q
Q
BISTEN
A/B
INA+
INB (INB+)
SI (INB
−
)
MODE
INA
−
SOIC
Top View
7B933
7B933
6
5
4
3
2
1
0
d
(Q )
e
(Q )
i
(Q )
f
(Q )
g
(Q )
c
(Q )
b
(Q )
1
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
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Pin Descriptions
CY7B923 HOTLink Transmitter
Name I/O Description
D0−7
(Db − h)TTL In Parallel Dat a Inpu t. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW
(or on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is
sent. When MODE is HIGH, D0, 1, ...7 become Db, c,.. .h , respectively.
SC/D (Da)TTL In Special Character/Dat a Select. A HIGH on SC/D when CKW rises causes the transmitter to encode
the p attern on D0−7 as a contro l code (Spe cial Chara cter), while a LOW c auses the d ata to be co ded
using the 8B/10B data alphabet. When MODE is HIGH, SC/D (Da) acts as Da input. SC/D has the
same timing as D0−7.
SVS
(Dj)TTL In Send Violation Symbol. If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent
while the data on the parallel input s is ignored. If SVS is LOW , the state of D0−7 and SC/D dete rmines
the code sent. In normal or test mode, this pin overrides the BIST generator and forces the trans-
mission of a V iolation code. When MODE is HIGH (placing the transmitter in unencoded mode), SVS
(Dj) acts as the Dj input. SVS has the same timing as D0−7.
ENA TTL In Enable Parallel Dat a. If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and
sent. If ENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null
characte r (K2 8.5) to fi ll th e s p a ce be twee n use r d at a . ENA ma y be held HIGH /LOW co ntinuo usly or
it may be pulsed with each data byte to be sent. If ENA is being used for data control, ENN will normally
be strapped HIGH, but can be used for BIST function control.
ENN TTL In Enable Next Parallel Data. If ENN is LOW, the data appearing on D0−7 at the next rising edge of
CKW is loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D0−7 at the
next rising edge of CKW will be ignored and the T ransmitter will insert a Null character to fill the space
between user data. ENN may be held HIGH/LOW continuously or it may be pulsed with each data
byte sent. If ENN is being used for data control, ENA will normally be strapped HIGH, but can be used
for BIST function control.
CKW TTL In Clock Write. CKW is both the clock frequency reference for the multiplying PLL that generates the
high−speed transmit clock, and the byte rate write signal that synchronizes the parallel data input.
CKW must be connected to a crystal controlled time base that runs within the specified frequency
range of the Transmitter and Receiver.
FOTO TTL In Fiber Optic Transmitter Off. FOTO determines the function of two of the three PECL transmitter
output pairs. I f FOTO is LO W, the data encoded by the Transmitte r w il l app ear at the outputs conti n-
uously. If FOT O is HIGH, OU T A± an d OUTB± are forced to their “logic z ero” state (OUT+ = LOW and
OUT− = HIGH), causing a fiber optic transmit module to extinguish its light output. OUTC is unaffected
by the level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testing.
OUTA±
OUTB±
OUTC±
PECL Out Differential Serial Data Outputs. These PECL 100K outputs (+5V referenced) are capable of driving
terminate d transmis sion lines or commercial fiber optic transmitter modules. Unu sed pairs of output s
can be left open, or wired to VCC to reduce power, if the output is not required. OUTA± and OUTB±
are controlled by the level on FOTO, and will remain at their “logical zero” states when FOTO is
asserted . OUTC± is unaf fected by the level on FO TO. (OUTA+ and OUTB+ are used as a di fferen tial
test clock input while in Test mode, i.e., MODE = UNCONNECTED or forced to VCC/2.)
MODE Three-
Level In Encoder Mode Select. The level on MODE determines the encoding method to be used. When wired
to GND, MODE selects 8B/10B encoding. When wired to VCC, data inpu ts bypass the enco der and
the bit pattern on Da-j goes directly to the shifter. When left floating (internal resistors hold the input
at VCC/2) the interna l bi t-cl oc k g ene rato r is dis ab led and OU TA+/OUTB + become the differentia l bi t
clock to be used for factory test. In typical applications MO DE is wired to VCC or GND.
BISTEN TTL In BIST Enable. When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends an alter-
nating 1 –0 p attern (D10.2 or D21.5 ). When either ENA or ENN is set L OW and BISTEN is LOW, the
transmitter begins a repeating test sequence that allows the Transmitter and Receiver to work
together to tes t the fun cti on of the entir e link . In normal use thi s in put is held HIGH or wired to V CC.
The BIST generator is a free-running pattern generator that need not be initialized, but if required,
the BIST se quenc e can be ini tialized by m oment aril y asserti ng SVS whi le BISTEN i s LOW. BI STEN
has the same timing as D0-7.
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RP TTL Out Read Pulse. RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is
independ ent of th e CKW du ty cyc le. Pulse w id ths are set by l ogic i nternal to the tran smitt er. In BIST
mode, RP will remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time
per BIST loop.
VCCN Power for output drivers.
VCCQ Power for internal circuitry.
GND Ground.
CY7B933 HOTLink Receiver
Name I/O Description
Q0−7
(Qb − h)TTL Out Q0-7 Parallel Data Output. Q0-7 contain the most recently received data. These outputs change
synchronously with CKR. When MODE is HIGH, Q0, 1, ...7 become Qb , c,...h, respectively.
SC/D(Qa)TTL Out Special Character/Data Select. SC/D indicates the context of received data. HIGH indicates a Control
(Special Character) code, LOW indicates a Data character . When MODE is HIGH (placing the receiver in
Unencoded mode), SC/D acts as the Qa output. SC/D has the same timing as Q0−7.
RVS (Qj)TTL Out Re ceived V iolation Symbo l. A HIGH on R VS indica tes that a co de rule vio lation has been detec ted
in the received data stream. A LOW shows that no error has been detected. In BIST mode, a LOW
on RVS indicates correct operation of the Transmitter, Receiver, and link on a byte-by-byte basis.
When MO DE is HIGH (placing the re ceiver in U nencod ed mode), R VS acts as the Qj output. RVS has
the same timing as Q0−7.
RDY TTL Out Dat a Outp ut Ready. A LOW pul se on RDY indicates that new data has been received and is ready to be
delivered. A missing pulse on RDY shows that the received data is the Null character (normally inserted by
the transmitter as a pad between data inputs). In BIST mode RDY will remain LOW for all but the last byte of
a test loop and will pulse HIGH one byte time per BIST loop.
CKR TTL Out Clo ck Read . This byte rate clock output is phase and frequency aligned to the incoming serial data
stream. RDY, Q0−7, SC/D, and RVS all switch synchronously with the rising edge of this output.
A/B PECL in Serial Data Input Select. This PECL 100K (+5V referenced) input selects INA or INB as the active
data i n put. If A/B is HIGH, INA is connected to the shifter and signals connected to INA will be decoded. If
A/B is LOW INB is selected.
INA±Diff In Serial Dat a Input A. The differential signal at the receiver end of the communication link may be
connected to the differential input pairs INA± or INB±. Either the INA pair or the INB pair can be used as
the main data input and the other can be used as a loopback channel or as an alternative data input selected
by the st ate of A/B. One input of an intentionally unused differential-pair (INA± or INB±) should be
terminated to VCC through a 1−5 KΩ resistor to assure that no data transitions are accidentally created.
INB
(INB+) PECL in
(Diff In) Serial Dat a Input B. This pin is either a single-ended PECL data receiver (INB) or half of the INB
dif fere ntia l p ai r. If SO is wired to VCC, then INB± can be used as differential line receiver interchangeably
with INA±. If SO is normally connected and loaded, INB becomes a single-ended PECL 100K (+5V referenced)
serial data input. INB is used as the test clock while in Test mode.
SI
(INB−)PECL in
(Diff In) Status Input. This pin is either a single-ended PECL status monitor input (SI) or half of the INB
dif fere ntia l p ai r. If SO is wired to VCC, then INB± can be used as differential line receiver interchangeably
with INA±. If SO is normally connected and loaded, SI becomes a single-ended PECL 100K (+5V referenced)
status monitor input, which is translated into a TTL-level signal at the SO pin.
SO TTL Out Status Out. SO is the TTL-translated output of SI. It is typically used to translate the Carrier Detect
output from a fiber-optic receiver connected to SI. When this pin is normally connected and loaded
(without any external pull-up resistor), SO will assume the same logical level as SI and INB will become
a single-ended PECL serial data input. If the status monitor translation is not desired, then SO may
be wired to VCC and the INB± pair may be used as a dif ferential serial data input.
RF TTL In Reframe Enable. RF c ontrols the Fram er logi c in the R ece iver. When RF is held HIGH, e ach SYNC
(K28.5) symbol detected in the shifter will frame the data that follows. If it is HIGH for 2,048 consecutive
bytes, the internal framer switches to double-byte mode. When RF is held LOW, the reframing logic
is disabled. The incoming data stream is then continuously deserialized and decoded using byte
boundaries set by the internal byte counter. Bit errors in the data stream will not cause alias SYNC
characters to reframe the data erroneously.
CY7B923 HOTLink Transmitter (continued )
Name I/O Description
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CY7B923 HOTLink Transmitter Block Diagram
Description
Input Register
The Input register holds the data to be processed by the
HOTLink transmitter and allows the input timing to be made
consistent with standard FIFOs. The Input register is clocked
by CKW and loaded with information on the D0-7, SC/D, and
SVS pins. Two enable inputs (ENA and ENN) allow the user to
choose when data is loaded in the register. Asserting ENA (Enable,
active LOW) causes the inputs to be loaded in the register on t he
rising edge of CKW . If ENN (Enable Next, active LOW) is asserted
when CKW rises, the data present on the inputs on the next rising
edge of CKW will be loaded into the Input register. If neither ENA
nor ENN are asserted LOW on the rising edge of CKW, then a
SYNC (K28.5) character is sent. These two inputs allow proper
timing and function for compatibility with either asynchronous FIFOs
or clocked FIFOs without external logic, as shown in Figure 4.
In BIST mode, the Input register becomes the signature
pattern generator by logically converting the parallel Input
register into a Linear Feedback Shift Register (LFSR). When
enabled, this LFSR will generate a 511-byte sequence that
includes all Data and Special Character codes, including the
expl ici t viol ati on symbo ls. This patt ern p rov ide s a p redi ctabl e
but pseudo-random sequence that can be matched to an
identic al LFSR in the Rece iv er.
Encoder
The Encoder transforms the input data held by the Input
register into a form more suitable for transmission on a serial
interface link. The code used is specified by ANSI X3.230
(Fibre Channel) and the IBM ESCON channel (code tables are
at the end of this datasheet). The eight D0-7 data inputs are
converted to either a Data symbol or a Special Character,
depending upon the state of the SC/D input. If SC/D is HIGH, the
data inputs represent a control code and are encoded using the
Special Character code table. If SC/D is LOW, the data inputs ar e
converted using the Data code table. If a byte time p asses with the
inputs disabled, the Encoder will output a Special Character
Comma K28.5 (or SYNC) that will maintain link synchronization.
SVS input forces the transmission of a specified Violation symbol to
allow the user to check error handling system logic in the controller
or for proprietary applications.
The 8B / 1 0B c o di ng fu nc ti o n o f the E n code r c an be by passe d
for systems that include an external coder or scrambler
function as part of the controller. This bypass is controlled by
setting the MODE select pin HIGH. When in bypass mode, Da-j
(note that bit order is specified in the Fibre Channel 8B/10B code)
become the ten inputs to the Shifter , with Da being the first bit to be
shifted out.
Shifter
The Shifter accepts p a r all el dat a from th e Enc od er on ce eac h
byte time and shifts it to the serial interface output buffers using
a PLL multiplied bit clock that runs at ten (10) times the byte
clock rate. Timing for the parallel transfer is controlled by the
counte r included in the Clock Gene rator and is no t affec ted by
signal levels or timing at the input pins.
OutA, OutB, OutC
The serial interface PECL output buffers (ECL100K refer-
enced t o +5V) are th e drivers f or the serial media. Th ey are all
connected to the Shifter and contain th e same serial data. T wo
of the output p airs (OUTA± and OUTB±) are cont rollable by the
FOTO input and can be disabled by the system controller to force a
logical zero (i.e., “light off”) at the outputs. The third output pair
(OUTC±) is not affected by FOTO and will supply a continuous data
stream suitable for loop-back testing of the subsystem.
OUTA± and OUTB± will respond to FOTO input changes
within a few bit times. However, since FOTO is not synchro-
nized with the transmitter data stream, the outputs will be
forced of f o r turned on a t arbit rary poin ts in a transm itted byte.
This function is intended to augment an external laser safety
controller and as an aid for Receiver PLL testing.
In wire-based systems, control of the outputs may not be
required , and FO T O can be s trappe d LOW. The thre e outpu ts
are intended to add system and architectural flexibility by
offe ring iden tical se rial bit s treams wit h sep arate interf aces for
REFCLK TTL In Reference Clock. REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets th e approxi mate center f requency for the in ternal PLL to tra ck the i ncoming bi t stream.
REFCL K m us t be c onn ec ted to a c r ys t a l-c ontro ll ed tim e ba se that runs w ith in th e freq uency limit s o f
the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within
CKW ±0.1%).
MODE Three-
Level In Decoder Mode Select. The level on the MODE pin determines the decoding method to be used.
When wired to GND, MODE selects 8B/10B decoding. When wired to VCC, registered shifter contents
bypass the decoder and are sent to Qa−j directly. When left floating (internal resistors hold the MODE pin at
VCC/2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be used for factory
test. In typical applications, MODE is wired to VCC or GND.
BISTEN TTL In Built-In Self-Test Enable. When BISTEN is LOW the Receiver awaits a D0.0 (sent once per BIST
loop) c haracte r and b egins a con tinuou s te st se quenc e that t est s t he func tiona lity o f the Tran smitt er,
the Receiver , and the link connec ting them. In BIST mode the status of the test can be monit ored with
RDY and R VS out put s . In no rma l us e BISTEN is hel d HI GH or wire d to V CC. BISTEN has the s am e
timing as Q0-7.
VCCN Power for output drivers.
VCCQ Power for internal circuitry.
GND Ground.
CY7B933 HOTLink Receiver (continued)
Name I/O Description
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redu ndant conne ctions or for multiple de stination s. Unneed ed
outputs can be wired to VCC to disable and power down the
unused output circuitry.
Clock Generator
The clo ck genera tor is an emb edded phas e-locked lo op (PLL)
that takes a byte-rate reference clock (CKW) and multiplies it
by ten (10) to create a bit rate clock f or driving the se rial shifter .
The byte rate reference comes from CKW, the rising edge of
which cl oc ks dat a into the Inp ut reg is ter. This clock must be a
cryst al referen ced puls e stream th at has a fr equency betw een
the minimum and maximum specified for the HOTLink Trans-
mitter/Receiver pair. Signals controlled by this block form the
bit clock and the timing signals that control internal data
transfers between the Input register and the Shifter.
The read pulse (RP) is derived from the feedback counter
used in the PLL multiplier. It is a byte-rate pulse stream with
the proper phase and pulse widths to allow transfer of data
from an asynchronous FIFO. Pulse width is independent of
CKW duty cycle, since proper phase and duty cycle is
maintained by the PLL. The RP pulse stream will insure correct
data transfers between asynchronous FIFOs and the trans-
mitter input latch with no external logic.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator , the multiplexe r for Test mode clock
distribution, and control logic to properly select the data
encoding. Test logic is discussed in more detail in the
CY7B923 HOTLink Transmitter Operating Mode Description.
CY7B933 HOTLink Receiver Block Diagram
Description
Serial Data Input s
Two pairs of differential line receivers are the inputs for the
serial data stream. INA± or INB± ca n be sele cted w ith the A/B
input. INA± is selected with A/B HIGH and INB± is selected
with A/B LOW . The threshold of A/B is compatible with the ECL
100K signals from PECL fiber optic interface modules. TTL
logic elements can be used to select the A or B inputs by
adding a resistor pull-up to the TTL driver connected to A/B.
The dif ferenti al thre shold of IN A± an d INB± will acco mmod ate
wire interconnect with filtering losses or transmission line
attenuation greater than 20 db (VDIF > 50 mv) or can be directly
connected to fiber optic interface modules (any ECL logic
family, not lim ited to ECL 100K). Th e common mode t olerance
will accomm odate a wide ra nge of signal term ination volt ages.
The highest HIGH input that can be tolerated is VIN = VCC, and
the low est LOW inp ut that can be in terpreted c orrectly is V IN =
GND+2.0V.
PECL-TTL Translator
The function of the INB(INB+) input and the SI(INB-) input is
defined by the connections on the SO output pin. If the
PECL/TTL transl ator func tion is not requi red, the SO ou tput is
wired to VCC. A sensor circuit will detect this connection and cause
the inputs to become INB± (a differential line-receiver serial-data
input). If the PECL/TTL translator function is required, the SO output
is connected to its normal TTL load (typically one or more TTL
inputs, but no pull-up resistor) and the INB+ input becomes INB
(single-ended ECL 100K, serial data input) and the INB- input
becomes SI (single-ended, ECL 100K status input).
This positive-referenced PECL-to-TTL translator is provided to
elimin ate externa l logic be tween an PECL fiber-optic interface
module “carrier de tect” out put and the TTL in put in the cont rol
logic. The input threshold is compatible with ECL 100K levels
(+5V referen ced). It c an also be used as part of th e link s tatu s
indication logic for wire connected systems.
Clock Synchroniz ati on
The Clock Synchronization function is performed by an
embedded PLL that tracks the frequency of the incoming bit
stream and ali gns the pha se of its i nte rnal bit rate clo ck to t he
serial data transitions. This block contains the logic to transfer
the data from the Shifter to the Decode register once every
byte. Th e counter tha t contro ls this transf er is initia lized by the
Framer logic. CKR is a buffered output derived from the bit
counter used to control the Decode register and the output
register transfers.
Clock output logic is designed so that when reframing causes
the counter sequence to be interrupted, the period and pulse
width o f CKR will n ever be les s th an norm al. R efram ing m ay
stretch the period of CKR by up to 90 %, and ei ther CKR Puls e
Width HIGH or Pulse Width LOW may be stretched,
depending on when reframe occurs.
The REFCLK input provides a byte-rate reference frequency
to improve PLL acquisition time and limit unlocked frequency
excursions of the CKR when no data is present at the serial
inputs. The frequency of REFCLK is required to be within
±0.1% of t he freq uen cy of the cl oc k that drives th e tra ns mi tter
CKW pin.
Framer
Framer logic checks the incoming bit stream for the pattern
that de fines the byte bounda ries. This comb inatorial logi c filter
looks for the X3.230 symbol defined as a Special Character
Comm a (K28 .5). W hen i t is foun d, the fr ee-runn ing b it c ounter
in the Clock Synchronization block is synchronously reset to
its initial state, thus framing the data correctly on the correct
byte boundaries.
Random errors that occur in the serial data can corrupt some
data patterns into a bit pattern identical to a K28.5, and thus
cause an erroneous d ata-framing error . The R F input prev ents
this by inhibiting reframing during times when normal message
data is present. When RF is held LOW, the HOTLink receiver
will deseri alize the in coming d at a with out tryi ng to re frame t he
data to incoming patterns. When RF rises, R D Y will be inhibited
until a K28.5 has been detected, after which RDY will resume its
normal function. While RF is HIGH, it is possible that an error could
cause misframing, after which all data will be corrupted. Likewise, a
K28.7 followed by D11.x, D20.x, or an SVS (C0.7) followed by D1 1.x
will create alias K28.5 characters and cause erroneous framing.
These sequences must be avoided while RF is HIGH.
If RF remains HIGH for greater than 2048 bytes, the framer
converts to double-byte framing, requiring two K28.5
characters aligned on the same byte boundary within 5 bytes
in order to reframe. Double-byte framing greatly reduces the
possibility of erroneously reframing to an aliased K28.5
character.
Shifter
The Shifter accepts serial inputs from the Serial Data inputs
one bit at a time, as clocked by the Clock Synchronization
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logic. Dat a is trans ferred to the Framer on eac h bit, and to the
Decode register once per byte.
Decode Register
The Decode register accepts data from the Shifter once per
byte as determined by the logic in the Clock Synchronization
block. It is presented to the Decoder and held until it is trans-
ferred to the output latch.
Decoder
Parallel data is transformed from ANSI-specified X3.230
8B/10B codes back to “raw data” in the Decoder. This block
uses the standard decoder patterns shown in the Valid Data
Characters and Valid Special Character Codes and
Sequences sections of this datasheet. Data patterns are
signaled by a LOW on the SC/D output and Special Character
patterns are signaled by a HIGH on the SC/D output. Unused
patterns or disparity errors are signaled as errors by a HIGH
on the RVS output and by specific Special Character codes.
Output Register
The Outp ut regis ter hold s the rec overed data (Q0-7, SC/D, and
RVS) and aligns it with the recovered byte clock (CKR). This
synchronization insures proper timing to match a FIFO interface or
other logic that requires glitch free and specified output behavior.
Outputs change synchronously with the rising edge of CKR.
In BIST mode, this register becomes the signature pattern
generator and checker by logically converting itself into a
Linear Feedback Shift Register (LFSR) pattern generator.
When enabled, this LFSR will generate a 511-byte sequence
that includes all Data and Special Character codes, including
the explicit violation symbols. This pattern provides a
predictable but pseudo-random sequence that can be
matched to an identical LFSR in the Transmitter. When
synchronized, it checks each byte in the Decoder with each
byte generated by the LFSR and shows errors at RVS.
Patterns generated by the LFSR are compared after being
buffered to the output pins and then fed back to the compar-
ators, allowing test of the entire receive function.
In BIST mode, the LFS R is initialized by the first occurrence of
the transmitter BIST loop start code D0.0 (D0.0 is sent only
once per BIST loop). Once the BIST loop has been started,
RVS will be HIGH for pattern mismatches between the
received sequence and the internally generated sequence.
Code rule violations or running disparity errors that occur as
part of the BIST loop will not cause an error indication. RD Y will
pulse HIGH once per BIST loop and can be used to check test
pattern progress. The receiver B IST generator can be reinitialized
by leaving and re-entering BIST mode.
Test Logic
Test logic includes the initialization and control for the Built-In
Self-Test (BIST) generator , the multiplexer for Test mode clock
distribution, and control logic for the decoder. Test logic is
discussed in more detail in the CY7B933 HOTLink Receiver
Operating Mode Description.
HOTLink CY7B923 Transmitter and CY7B933
Receiver Operation
The CY7B923 Transmitter operating with the CY7B933
Receiver form a general purpose data communications
subsystem capable of transporting user data at up to 33
Mbytes per second (40 Mbytes per second for –400 devices)
over se ve ral type s of s erial in terfac e medi a. Figure 7 illustrates
the flow of data through the HOTLink CY7B923 transmitter pipeline.
Dat a is latc he d int o the trans mitter on the rising edge of CK W
when enabled by ENA or ENN. RP is asserted LOW wi th a 60%
LOW/40% HIGH duty cycle when ENA is LOW . RP may be used as
a read strobe for accessing data stored in a FIFO. The parallel data
flows through the encoder and is then shifted out of the OUTx± PECL
drivers. The bit-rate clock is generated internally from a
multiply-by-ten PLL clock generator. The latency through the
transmitter is approximately 21tB – 10 ns over the operating
range. A more complete description is found in the section
CY7B923 HOTLink Transmitter Operating Mode Description.
Figure 2 illustrates the data flow through the HOTLink
CY7B933 receiver pipeline. Serial data is sampled by the
recei ver on th e INx± i nputs. The receiv er PLL lo cks onto th e
serial bit stream and generates an internal bit rate clock. The
bit stream is deserialized, decoded and then presented at the
parallel output pins. A byte rate clock (bit clock ³ 10)
synchronous with the parallel data is presented at the CKR pin.
The RDY pin will be asserted to LOW to indicate that data or
control charac ters are presen t on the o utput s. RDY will not be
asserted LOW in a field of K28.5s except for any single K28.5
or th e la st one in a cont inuo us se ri es of K28. 5’s. Th e la ten cy
through the receiver is approximately 24tB + 10 ns over the
operating range. A more complete description of the receiver
is in th e section CY7B933 HO TLink Rec eiver Operat ing Mo de
Description.
The HOTL ink Receive r has a built-i n byte framer that s ynchro-
nizes the Receiver pipeline with incoming SYNC (K28.5)
characters. Figure 3 illustrates the HOTLink CY7B933
Receiver framing operation. The Framer is enabled when the
RF pin is asserted H IGH. RF is latc hed into the receiver on the
falling edge of CKR. The framer looks for K28.5 characters
embedded in the serial data stream. When a K28.5 is found,
the framer sets t he paralle l byte boun dary for subseq uent data
to the K28.5 boundary. While the framer is enabled, the RDY
pin indicates the status of the framing operation.
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When the RF pin is asserted HIGH, RDY leaves it normal
mode of operation and is asserted HIGH while the framer
searches the data stream for a K28.5 character. After the
framer has synchronized to a K28.5 character, the Receiver
will assert the RDY pin LOW when the K28.5 character is
present at the parallel output. The RDY pin will then resume
its normal operation as dictated by the MODE and BISTEN
pins.
The normal operation of the RDY pin in encoded mode is to
signal when parallel data is present at the output pins by
pulsing LOW with a 60% LOW/40% HIGH duty cycle. RDY
does not pulse LOW in a field of K28.5 characters; however,
RDY does pulse LOW for the last K28.5 character in the field
or for any single K28.5. In unencoded mode, the normal
operation of the RDY pin is to signal w h en a ny K28 .5 is at the
parallel output pins.
The Transmitter and Receiver parallel interface timing and
functio nality can be made to match the timing and functionality
of eit her an as ynchr ono us FI FO o r a cloc ked F IFO by app ro -
priately connecting signals (See Figure 4) . Proper oper ation of
the FIFO interface depends upon various FIFO-specific access and
response specifications.
The HOTLink Transmitter and Receiver serial interface
provides a seamless interface to various types of media. A
minimal number of external components are needed to
properly terminate transmission lines and provide PECL loads.
For pr oper po wer supp ly de coupl ing, a sin gle 0. 01 mF for each
device is all that is required to bypass the VCC and GND pins.
Figure 5 illustrates a HOTLink Transmitter and Receiver interface to
fiber optic and copper media. More information on interfacing
HOTLink to various media can be found in the HOTLink Design
Considerations application note.
CY7B923 HOTLink Transmitter Operating Mode
Description
In normal operation, the Transmitter can operate in either of
two modes. The Encoded mode allows a user to send and
receive eight-bit data and control information without first
converting it to transmission characters. The Bypass mode is
used for systems in which the encoding and decoding is
performed in an external protocol controller.
In either mode, data is loaded into the Input register of the
Transmitter on the rising edge of CKW. The input timing and
functional response of the Transmitter input can be made to
match the timing and functionality of either an asynchronous
FIFO or a clo cked FIFO by an appro priate c onnec tion of inp ut
signals (see Figure 4). Proper operation of the FIFO interface
depends upon various FIFO-specific access and response specifica-
tions.
Figure 2. CY7B933 Receiver Data Pipeline in Encoded Mode
Figure 3. CY7B933 Framing Operation in Encoded Mode
CKR
Q0−7,
SC/D,
RVS
RDY
INX±
DATAK28.5
DATA
K28.5
SERIAL DATA IN
PARALLEL
DATA OUT
RDY IS HIGH IN FIELD OF K28.5S
RDY IS LOW FOR LAST K28.5
DATA
RDY IS LOW FOR DATA
RECEIVER LATENCY= 24tB+10ns
CKR
Q0−7,
SC/D,
RVS
RDY RDY IS HIGH WHILE WAITING FOR K28.5
RDY IS LOW
FOR K28.5
K28.5
RF
DATADATADATADATADATA DATA DATA
RDY RESUMES
NORMAL
OPERATION
CKR STRETCHES AS
DATA BOUNDARY CHANGES
RF LATCHED ON
FALLING EDGE OF CKR
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Encoded Mode Operation
In Encoded mode the input data is interpreted as eight bits of
data (D0 – D7), a context control bit (SC/D), and a system
diagnostic input bit (SVS). If the context of the data is to be
normal message data, the SC/D input should be LOW , and the
data should be encoded using the valid data character set
described in the Valid Data Characters section of this
data sheet . If the context of the data is to be control or pro tocol
information, the SC/D input will be HIGH, and the data will be
encode d usi ng the vali d spec ial c harac ter set de scribe d in the
Valid Special Character Codes and Sequences section.
Special characters include all protocol characters necessary
to encode packets for Fibre Channel, ESCON, proprietary
systems, and diagnostic purp oses.
The diagnostic characters and sequences available as Special
Characters include those for Fibre Channel link testing, as well
as codes to be used for testing sy stem respons e to link erro rs
and tim ing. A V i olatio n symbo l can b e explic itly s ent as par t of
a user data packet (i.e., send C0.7; D7-0 = 1 1 1 00000 and SC/D
= 1), or it can be s ent in respon se to an exte rnal sy stem using
the SVS input. This will allow system diagnostic logic to
evaluate the errors in an unambiguous manner, and will not
require any modification to the transmission interface to force
transmission errors for testing purposes.
Bypass Mode Operation
In Bypass mode the input data is interpreted as ten (10) bits
(Db-h), SC/D (Da), and SVS (Dj) of pre-encoded transmission
dat a to be se rial iz ed a nd s en t ov er the lin k. T his data can use
any encoding method suitable to the designer. The only
restrictions upon the data encoding method is that it contain
suitable transition density for the Receiver PLL data synchro-
nizer (one per 10 bit byte), and that it be compatible with the
transmission media.
Data loaded into the Input register on the rising edge of CKW
will be loaded into the Shifter on the subsequent rising edges
of CKW. It will then be shifted to the outputs one bit at a time
using the in ternal clock gene rated b y the clock gene rator. The
first bit of the transmission character (Da) will appear at the
output (OUT A± , OUTB±, and OUTC±) after the next CKW edge.
While in either the Encoded mode or Bypass mode, if a CKW
edge arrives when the inputs are not enabled (ENA and ENN
both HIGH), the Encoder will insert a pad character K28.5
(e.g., C5.0) to main tai n prope r link sync hroniz ation (in Byp ass
Figure 4. Seamless FIFO Interface
7C42X/3X/6X/7X
CLOCKED FIFOASYNCHRONOUS FIFO
7C44X/5X
9
RQ
0−8ENR Q0−8
CKR
9
7B923 7B923
ENA D0−7,SC/DCKW RP ENN D0−7,SC/DCKW
FROM CONTROLLER
HOTLIN K T RAN S MI TTER
HOTLINK RECEIVER
7B933 7B933
RDY Q0−7,SC/DCKRRDY Q0−7,SC/DCKR
99
WD
0−8ENW D0−8
CKW
7C42X/3X/6X/7X 7C44X/5X
CLOCKED FIFOASYNCHRONOUS FIFO B923–21
HOTLIN K T RAN S MI TTER
HOTLIN K RECEIVER
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mode the proper sense of running disparity cannot be
guarant eed for t he f irst p ad chara cter, but is correct f or all p ad
characters that follow). This automatic insertion of pad
characters can be inhibited by insuring that the Transmitter is
always enabled (i.e., ENA or ENN is hard-wired LOW).
PECL Output Functional and Connection Options
The three pairs of PECL outputs all contain the same infor-
mation and are intended for use in systems with multiple
connec tions. Ea ch outpu t pai r may be connected to a differ ent
serial media, each of which may be a dif ferent length, link type,
or interface technology. For systems that do not require all
three output pairs, the unused pairs should be wired to VCC to
minimize the power dissipated by the output circuit, and to
minimize unwanted noise generation. An internal voltage
comparator detects when an output differential pair is wired to
VCC, causing the current source for that pair to be disabled.
This results in a power savings of around 5 mA for each
unus ed pair.
In sys tem s th at re qui re th e outputs to be s hu t off during som e
periods when link transmission is prohibited (e.g., for laser
safety functions), the FOTO input can be asserted. While it is
poss ibl e t o i ns u re th at t he ou t p ut s tat e of th e P EC L dri ve r s is
LOW (i .e. , ligh t is off) by se nding all 0’s in B ypass m ode , it is
often inconvenient to insert this level of control into the data
transmission channel, and it is impossible in Encoded mode.
FOT O is provided to simplify and aug ment this control function
(typically found in laser-based transmission systems). FOTO
will force OUTA+ and OUTB+ to go LOW, OUTA- and OUTB-
to go HIGH, while allowing OUTC± to continue to function
normally (OUTC is typically used as a diagnostic feedback and
cannot be disabled). This separation of function allows various
system configurations without undue load on the control
function or data channel logic.
Transmitter Serial Data Characteristics
The CY7B923 HOTLink Transmitter serial output conforms to
the requirements o f the Fibre Channe l specification. The serial
data output is controlled by an internal Phase-Locked Loop
that multiplies the frequency of CKW by ten (10) to maintain
the proper bit clock frequency. The jitter characteristics
(including both PLL and logic components) are shown below:
• Deterministic Jitter (Dj) < 35 ps (peak-peak). Typically
measu red wh il e send ing a contin uou s K28.5 (C5.0).
• Ra ndo m Jitter (Rj) < 175 ps (peak-peak). Typically
measu red wh il e send ing a contin uou s K28.7 (C7.0).
Transmitter Test Mode Description
The CY7B923 Transmitter offers two types of test mode
operation, BIST mode and Test mode. In a normal system
applic ati on, the Built-In Self-Test (BIST) mode can be used to
check the functionality of the Transmitter, the Receiver, and
the link connecting them. This mode is available with minimal
impact on user system logic, and can be used as part of the
normal system diagnostics. Typical connections and timing
are shown in Figure 6.
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Figure 5. HOTLink Connection Diagram
RX
SIG
92421
20
VCC
Control
Config
and
Config
CY7B923
(Dj)
(Dh)
(Dg)
(Df)
(Di)
(De)
(Dd)
(Dc)
(Db)
(Da)
Transmitter
Coax or
Fiber
Fiber
TX
ESignal Det.
Optional
Fiber Optic
Tx
Twisted Pa
ir
Twisted Pa
ir
Coax or
Fiber Optic
Rx
Fiber Optic
PECL Load
Tx PECL Load
Tx PECL Load
Transmission
Line
Termination
Status
Data
Data
Status
Control
and CY7B933
(Qa)
Receiver
(Qb)
(Qh)
(Qg)
(Qc)
(Qd)
(Qe)
(Qi)
(Qf)
(Qj)
.01UF
922
20
8
24
23
5
6
4
10
19
2
3
1
28
26
27
7
25
11
12
13
14
15
16
17
18
21
82
RL/2
RL/2
82 130
649
.01UF
.01UF
.01UF
130
270
.01UF
.01UF
82 130
.01UF
270
270
130
1500
82
25
86
7
26
4
23
19
10
527
28
1
2
11
12
13
14
15
16
17
18
22
3
VCC
GND
RP
ENN
ENA
BISTEN
SVS
SC/D
OUTC–
OUTC+
OUTB–
OUTB+
OUTA–
OUTA+
MODE
FOTO
D7
D6
D5
D4
D3
D2
D1
D0
CKW
VCC
RX–
RX+
GND
VCC
TX–
TX+
GND
B
A
D
C
B
A
D
C
E
REFCLK
GND
RDY
BISTEN
SO
SC/D
RVS
RF IB–
IB+
IA–
IA+
D7
D6
D5
D4
D3
D2
D1
D0
CKR
A/B
MODE
Unused Output Left
Open or Wired to VCC
270
270
to Minimize Powe r Dissi pation
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BIST Mode
BIST mode functions as follows:
1. Set BISTEN LOW to begin test pattern generation. Trans-
mitter begins sending bit rate ...1010...
2. Set either ENA or ENN LOW to begin pattern sequence
generation (use of the Enable pin not being used for normal
FIFO or system interface can minimize logic delays
betwe en the co ntrol le r and transmi tter).
3. Allow the Transm itter to r un throu gh severa l BIST loo ps or
until the Receiver test is complete. RP will pulse LOW once
per BIST loop, and can be used by an external counter to
monitor the number of test pattern loops.
4. When testing is completed, set BISTEN HIGH and ENA and
ENN HIGH and resume normal function.
Note: It may be advisable to send violation characters to test
the R VS outpu t in the R eceiver. This can be done by exp licitl y
sending a violation with the SVS input, or allowing the trans-
mitter BIST loop to run while the Receiver runs in normal
mode. The BIST loop includes deliberate violation symbols
and will adequately test the RVS function.
Figure 6. BIST Illustration
FOTO
MODE
CKW
RP
SC/D
D0−7
SVS
ENA
ENN
BISTEN
REFCLK
MODE
RF
CKR
SC/D
Q0−7
RVS
RDY
BISTEN
OUTA
OUTB
OUTC
DON’ T CARE
SO
INA
INB
A/B
CY7B923
CY7B933
8
8
BIST
Tx
START Tx
STOP
ERROR
TEST
START
TEST
END
Rx
BEGIN
LOOP
BIST
LOOP
TEST
LOW
DON’ T CARE
LOW
WITHIN SPEC.
DON’ T CARE
LOW
DON’ T CARE
WITHIN SPEC.
DON’ T CARE
DON’ T CARE
HIGH
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BIST mode is intended to check the entire function of the
Transmitter (except the Trans mi tter inp ut p in s a nd the by p as s
function in the Encoder), the serial link, and the Receiver. It
augments normal factory ATE testing and provides the
designer with a rigorous test mechanism to check the link
transmission system without requiring any significant system
overhead.
While in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and
BISTEN = LOW causes the Transmitter to switch to Encoded
mode and begin sending the BIST pattern, as if MODE = LOW .
When BISTEN returns to HIGH, the Transmitter resumes
normal Bypass operation. In Test mode the BIST function
works as in the Normal mode. For more information on BIST,
consult the “HOTLink Built-In Self-Test” application note.
Test Mode
The MODE input pin selects between three transmitter
functional modes. When wired to VCC, the D(a-j) inputs bypass
the Encoder and load directly from the Input register into the
Shifter. When wired to GND, the inputs D0-7, SVS, and SC/D
are encoded using the Fibre Channel 8B/10B codes and
sequences (shown at the end of this datasheet). Since the
Transmi tte r is u sua ll y hard w ire d t o En coded or Bypass mode
and no t switched betwee n them, a third function is provided for
the MODE pin. Test mode is selected by floating the MODE
pin (int ernal resis tors hold the MODE pin at VCC/2). Test mo de
is used for factory or incoming device test.
Test mode caus es the Transmitter to function in its Encoded
mode, but with OutA+/OutB+ (used as a differential test clock
input) as the bit rate clock input instead of the internal
PLL-generated bit clock. In this mode, inputs are clocked by
CKW and tran sfe rs between the Inp ut reg ister a nd Sh ifter are
timed by the internal counters. The bit-clock and CKW must
maint ain a fi xed phas e and divi de-by-ten ratio. The p hase and
pulse width of RP are controlled by phases of the bit counter
(PLL feedback counter) as in Normal mode. Input and output
patterns can be synchronized with internal logic by observing
the state of RP or the device can be initialized to match an A TE
test pattern using the following technique:
1. With the MODE pin either HIGH or LOW, stop CKW and
bit-clock.
2. Force the MODE pin to MID (open or VCC/2) while the
clock s are sto ppe d.
3. Start the bit-clock and let it run for at least two cycles.
4. Start the CKW clock at the bit-clock/10 rate.
Test mode is intended to allow logical, DC, and AC testing of
the Transmitter without requiring that the tester check output
data patterns at the bit rate, or accommodate the PLL lock,
tracking, and frequency range characteristics that are required
when the HOTLink part operates in its normal mode. To use
OutA+/OutB+ as the test clock input, the FOTO input is held
HIGH while in Test mode. This fo rce s the two output s to go to
an “P ECL LOW, ” wh ich c an b e ig nore d w hile t he test sys tem
creates a differential input signal at some higher voltage.
CY7B933 HOTLink Receiver Operating Mode
Description
In nor mal user operation, the Receiver can o perate in either of
two mo des . The Encoded mode allows a u ser system to se nd
and receive eight-bit data and control information without first
converting it to transmission characters. The Bypass mode is
used for systems in which the encoding and decoding is
performed by an external protocol controller.
In eithe r mo de, se rial da ta i s recei ved a t one of the differenti al
line receiver inputs and routed to the Shifter and the Clock
Synchronization. The PLL in the Clock Synchronizer aligns the
internally generated bit rate clock with the incoming data
stream and cloc ks the data int o the shifter. At the end of a byte
time (ten bit times), the data accumulated in the shifter is trans-
ferred to the D ecode re gister.
To properly align the incoming bit stream to the intended byte
bounda ries, t he b it co unter i n the Cl ock Sy nchro nizer must be
initialized. The Framer logic block checks the incoming bit
stream for the un ique pattern that defines the byte boundaries.
This combinatorial logic filter looks for the X3.230 symbol
defined as “Special Character Comma” (K28.5). Once K28.5
is found, the free running bit counter in the Clock Synchronizer
block is synchronously reset to its initial state, thus “framing”
the data to the correct byte boundaries.
Since n oise-indu ced errors can caus e the inco ming dat a to be
corrupted, and since many combinations of error and legal
data can create an alias K28.5, an option is included to disable
resynchronization of the bit counter. The Framer will be
inhibi ted when the RF input is he ld LOW . When RF rises, R DY
will be inhibited until a K28.5 has been detected, and RDY will
resum e i ts no r ma l fu nc tio n . D ata w i ll co nti n ue to f low t hro ug h
the Receiver while RDY is inhibited.
Encoded Mode Operation
In Encoded mode the serial input data is decoded into eight
bits of data (Q0 – Q7), a context control bit (SC/D), and a
system diagnostic output bit (RVS). If the pattern in the
Decode register is found in the Valid Data Characters table,
the context of the data is decoded as normal message data
and the SC/D output will be LOW. If the inco ming bit p atte rn is
found in the Valid Special Character Codes and Sequences
tabl e, it is interpreted as “control” or “protocol information,” and
the SC/D output will be HIGH. Special characters include all
protocol characters defined for use in packets for Fibre
Channel, ESCON, and other proprietary and diagnostic
purposes.
The Violation symbol that can be explicitly sent as part of a
user data packet (i.e., Transmitter sending C0.7; D7-0 = 111
00000 and SC/D = 1; or SVS = 1) will be decoded and
indicated in exactly the same way as a noise-induced error in
the transmission link. This function will allow system
diagnostics to evaluate the error in an unambiguous manner,
and will not require any modification to the receiver data
interface for error-testing purposes.
Bypass Mode Operation
In Bypass mode the serial input data is not decoded, and is
transferred directly from the Decode register to the Output
register’s 10 bits (Q(a-j). It is assumed that the data has been
preencoded prior to transmission, and will be decoded in
subsequent logic external to HOTLink. This data can use any
encoding method suitable to the designer . The only restrictions
upon the data encoding method is that it contain suitable
trans ition densit y for the Re ceiver PLL data sy nchronizer (o ne
per 10 bit byte) and th at it be com patibl e with the transmissi on
media.
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The framer function in Bypass mode is identical to Encoded
mode, so a K28.5 pattern can still be used to re frame the serial
bit stream.
Parallel Output Function
The 10 outputs (Q0-7, SC/D, and RVS) all transition simulta-
neously , and are aligned with RDY and CKR with timing allowances
to interface directly with either an asynchronous FIFO or a clocked
FIFO. T ypical FIFO connections are shown in Figure 4.
Data outputs can be clocked into the system using either the
rising or falling edge of CKR, or the rising or falling edge of
RDY. If CKR is used, RDY can be used as an enable for the
receiving logic. A LOW pulse on RDY shows t hat new data has
been received and is ready to be delivered. The signal on RDY
is a 60%-L OW duty cycle byte-rate pulse train sui table for the
write pulse in asynchronous FIFOs such as the CY7C42X, or
the enable write input on Clocked FIFOs such as the
CY7C44X. HIGH on RDY shows that the received data
appearing at the outputs is the null character (normally
inserte d by the tran sm itt er as a p a d be tw ee n da t a in pu ts) and
should be ignored.
When the T ransmitter is disabled it will continuously send pad
charac ters (K28.5). To assure that the rec eive FIFO will not be
overfilled with these dummy bytes, the RDY pulse output is
inhibited during fill strings. D ata at the Q0-7 outputs will reflect the
correct received data, but will not appear to change, since a string
of K28.5s all are decoded as Q7-0 =000 00101 and SC/D = 1
(C5.0). When new data appears (not K28.5), the RDY output w ill
resume normal function. The “last” K28.5 will be accompanied by a
normal RDY pulse.
Fill characters are defined as any K28.5 followed by another
K28.5. All fill characters will not cause RDY to pulse. Any
K28.5 followed by any other character (including violation or
illegal characters) will be interpreted as usable data and will
cause RDY to pulse.
As no ted above , RDY can also be used as an indication of correct
framing of received data. While the Receiver is awaiting receipt of a
K28.5 with RF HIGH, the RDY outputs will be inhibited. When RDY
resumes, the received data will be properly framed and will be
decoded correctly. In Bypass mode with RF HIGH, RDY will pulse
once for each K28.5 received. For more information on the RDY
pin, consult the “HOTLink CY7B933 RDY Pin Description” appli-
cation note.
Code rule violations and reception errors will be indicated as
follows:
RVS SC/DQouts Name
1. Good Data code received
with good running disparity (RD)0000-FFD0.0-31.7
2. Good Special Character
code received with good RD 0 1 00-0B C0.0-11.0
3. K28.7 immediately following
K28.1 (ESCON Connect_SOF)0 1 27 C7.1
4. K28.7 immediately following
K28.5 (ESCON Passive_SOF) 0147C7.2
5. Unassigned code received 1 1 E0 C0.7
6. -K28.5+ received when
RD was + 1 1 E1 C1.7
7. +K28.5- received when
RD was - 1 1 E2 C2.7
8. Good code received
with wrong RD 1 1 E4 C4.7
Receiver Serial Data Requirements
The CY7B933 HOTLink Receiver serial input capability
conforms to the requirements of the Fibre Channel specifi-
cation . The s eria l da t a inp ut is trac ke d by an int erna l PLL that
is used to recov er the clock phase and to ext ract the dat a from
the serial bit stream. Jitter tole ran ce ch ara cte ris tic s (in cl udi ng
both PLL and logic component requirements) are shown
below:
• Deterministic Jitter Tolerance (Dj) > 40% of tB. Typically
measured while receiving data carried by a
bandwidth-limited channel (e.g., a coaxial transmission line)
while maintaining a Bit Error Rate (BER) < 10–12.
• Random Jitter Tolerance (Rj) > 90% of t B. Ty pically
measured while receiving data carried by a
random-noise-limited channel (e.g., a fiber-optic trans-
mission system with low light levels) while maintaining a Bit
Error Rate (BER) < 10–12.
• Total Jitter Tolerance > 90% of tB. Total of Dj + Rj.
• PLL-Acquisition Time < 500-bit times from worst-case
phase o r frequenc y change in th e serial inp ut dat a stream,
to receiving data within BER objective of 10-12. Stable
power s upplies wit hin speci fications , stabl e REFCLK input
frequency and normal data framing protocols are assumed.
Note: Ac quisition time is m easured from worst-cas e phase
or frequency chang e to zero phase and frequency error . As
a resul t of the recei ver’s wide jitte r tolerance, v alid dat a will
appear at the receiver’s outputs a few byte times after a
worst- cas e phase change.
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Receiver Test Mode Description
The CY7B933 Receiver offers two types of test mode
operation, BIST mode and Test mode. In a normal system
applic ati on, the Buil t-In Sel f-Test (BIST) mode can be used to
check the functionality of the T ransmitter , the Receiver and the
link connecting them. This mode is available with minimal
impact on user system logic, and can be used as part of the
normal system diagnostics. Typical connections and timing
are shown in Figure 6.
BIST Mode
BIST Mode function is as follows:
1. Set BISTEN LOW to enable self -test g enerati on and awa it
RDY LOW indicating that the initialization code has been
received.
2. Monitor RVS and check f or any byte time with the pin HIGH
to detect pattern mismatches. RDY will pulse HIGH once
per BIST loop, and can be used by an external counter to
monitor tes t patte rn progress. Q0-7 and SC/D wil l show the
expected pattern and may be useful for debug purposes.
3. When testing is c ompleted, set BISTEN HIGH and resu me
normal function.
Note: A specific test of the RVS output may be required to
assure an adequate test. To perform this test, it is only
necessary to have the Transmitter send violation (SVS =
HIGH) for a few bytes before beginning the BIST test
sequence. Alternatively, the Receiver could enter BIST mode
after the T r ansmitter h as begun sen ding BIST loop da ta, or be
removed before the Transmitter finishes sending BIST loops,
each of wh ich contai n several delibe rate violation s and should
cause RV S to pulse H IGH.
BIST mode is intended to check the entire function of the
Transmitter, serial link, and Receiver. It augments normal
factory ATE testing and provides the user system with a
rigorous test mechanism to check the link transmission
system, without requiring any significant system overhead.
When i n Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and BISTEN =
LOW causes the Receiver to switch to Encoded mode and begin
checking the decoded received data of the BIST pattern, as if
MODE = LOW. When BISTEN returns to HIGH, the Receiver
resumes normal Bypass operation. In Test mode the BIST function
works as in the normal mode.
Test Mode
The MO DE input pin sel ects b etween three rece iver function al
modes. When wired to VCC, the Shifter contents bypass the
Decoder and go directly from the Decoder latch to the Qa-j inputs of
the Output latch. When wired to GND, the outputs are decoded
using the 8B/10B codes shown at the end of this datasheet and
become Q0-7, RVS, and SC/D. The third function is Test mode,
used for factory or incoming device test. This mode can be selected
by leaving the MODE pin open (internal circuitry forces the open pin
to VCC/2).
Test mode causes the Receiver to function in its Encoded
mode, bu t with INB (INB+) as the bit rate Test cloc k instead of
the Internal PLL generated bit clock. In this mode, transfers
betwe en the Shifte r, Deco der reg is ter and Out put reg is ter are
controlled by their normal logic, but with an external bit rate
clock instead of the PLL (the recovered bit clock). Internal logic
and test pattern inputs can be synchronized by sending a
SYNC p attern and al lowing the F ramer to a lign the logic to the
bit stream. The flow is as follows:
1. Assert Test mode for several test clock cycles to establish
normal co unte r sequenc e.
2. Assert RF to enable reframing.
3. Input a repeating sequence of bits representing K28.5
(Sync).
4. RDY falling shows the byte boundary established by the
K28.5 input pattern.
5. Proceed wi th pattern, voltage and ti mi ng t ests as is c onv e-
nient for the test program and tester to be used.
(While in T est mode and in BIST mode with RF HIGH, the Q0-7,
RVS, and SC/D outputs reflect various internal logic states and not
the received data.)
Test mode is intended to allow logical, DC, and AC testing of
the Receiver without requiring that the tester generate input
data at the bit rate or accom modate the PLL lo ck, tracking and
frequency range characteristics that are required when the
part operates in its normal mode.
X3.230 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight
bits at a time into a 10-bit Transmission Character and then
sent serially, bit by bit. Information received over a serial link
is collected ten bits at a time, and those Transmission
Characters that are used for data (Data Characters) are
decoded into the correct eight-bit codes. The 10-bit Trans-
mission Code supports all 256 8-bit combinations. Some of the
remaining Transmission Characters (Special Characters) are
used for functio ns other than data transmission .
The primary rationale for use of a Transmission Code is to
improve the transmission characteristics of a serial link. The
encoding defined by the Transmission Code ensures that suffi-
cient transitions are present in the serial bit stream to make
clock r ecovery possibl e at th e Receiv er. Such e ncoding also
greatly increases the likelihood of detecting any single or
multiple bit errors that may occur during transmission and
recepti on of information. In addition , some Spec ial Characters
of the Transmission Code selected by Fibre Channel Standard
consist of a distinct and easily recognizable bit pattern (the
Special Character Comma) that assists a Receiver in
achieving word alignment on the incoming bit stream.
Notation Conventions
The documentation for the 8B/10B Transmission Code uses
letter notation for the bits in an 8-bit byte. Fibre Channel
Standard notation uses a bit notation of A, B, C, D, E, F, G, H
for the 8-bit byte for the raw 8-bit data, and the letters a, b, c,
d, e, i, f, g, h, j for encoded 10-bit data. There is a correspon-
dence between bit A and bit a, B and b, C and c, D and d, E
and e, F and f, G and g, and H and h. Bits i and j are derived,
respectively, from (A,B,C,D,E) and (F,G,H).
The bit labeled A in the description of the 8B/10B T ransmission
Code corresponds to bit 0 in the numbering scheme of the
FC-2 specification, B corresponds to bit 1, as shown below.
FC-2 bit designation— 76543210
HOTLink D/Q designation—76543210
8B/10B bit designation— H G F E D C B A
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To clarify this correspondence, the following example shows
the conversion from an FC-2 V alid Data Byte to a Transmission
Character (using 8B/10B Transmission Code notation)
FC-2 45
Bits: 7654 3210
0100 0101
Converted to 8B/10B notation (note carefully that the order of
bits is reversed):
Data Byte Name D5.2
Bits:ABCDEFGH
10100 010
Translated to a transmission Character in the 8B/10B Trans-
mission Code: Bits: abcdeifghj
1010010101
Each valid Transmission Character of the 8B/10B Trans-
mission Code has been given a name using the following
conve ntion: cxx.y, where c is used to sho w whether the T rans-
mission Character is a Data Character (c is set to D, and the
SC/D pin is LOW) or a Special Character (c is set to K, and t he
SC/D pin is HIGH). When c is set to D, xx is the decimal value of the
binary number composed of the bits E, D, C, B, and A in that order ,
and the y is the decimal value of the binary number composed of
the bits H, G, and F in that order. When c is set to K, xx and y are
derived by comparing the encoded bit patterns of the Special
Character to those patterns derived from encoded V alid Data bytes
and selecting the names of the patterns most similar to the encoded
bit patterns of the Special Character .
Under the above conventions, the Transmission Character
used fo r the example s above, i s referred to by the name D5 .2.
The Speci al Character K29.7 is so named because the first six
bits (abcdei) of this character make up a bit pattern similar to
that resulting from the encoding of the unencoded 11101
pattern (29), and because the second four bits (fghj) make up
a bit pattern similar to that resulting from the encoding of the
unencoded 111 pattern (7).
Note: This definition of the 10-bit T ra nsmissio n Code is bas ed
on (and is in basic agreement with) the following references,
which describe the same 10-bit transmission code.
A.X. Widmer and P.A. Franaszek. “A DC-Balanced, Parti-
tioned-Block, 8B/10B Transmission Code” IBM Journal of
Research and Development, 27, No. 5: 440-451 (September,
1983).
U.S. Patent 4, 486, 739. Peter A. Franaszek and Albert X.
Widmer. “Byte-Oriented DC Balanced (0.4) 8B/10B Parti-
tioned Block Transmission Code” (December 4, 1984).
Fibre Channel Physical and Signaling Interface (dpANS
X3.230-199X ANSI FC-PH Standard).
IBM Enterprise Systems Architecture/390 ESCON I/O
Interface (document number SA22-7202).
8B/10B Transmission Code
The following information describes how the tables shall be
used for both generating valid Transmission Characters
(enc oding) and ch ecking the va lidity o f received T r ansmis sion
Characters (decoding). It also specifies the ordering rules to
be followed when transmitting the bits within a character and
the characters within the higher-level constructs specified by
the st a nda rd.
Transmission Order
Within the definition of the 8B/10 B Trans mi ssion C o de, th e b it
positions of the Transmission Characters are labeled a, b, c,
d, e, i, f, g , h, j. Bi t “a” sh all be transmit ted first foll owed by bi ts
b, c, d, e, i, f, g, h, and j in that order. (Note that bit i shall be
transmitted between bit e and bit f, rather than in alphabetical
order.)
Valid and Invalid Transmission Characters
The following tables define the valid Data Characters and valid
Special Characters (K characters), respectively. The tables
are used for both generating valid Transmission Characters
(encodi ng) an d che ckin g t he va lidity of re ceiv ed Tran smissi on
Characters (decoding). In the tables, each Valid-Data-byte or
Special -Char acter-c ode ent ry ha s two co lumns that repr esent
two (not necessarily different) Transmission Characters. The
two columns correspond to the current value of the running
disparity (“Current RD-” or “Current RD+”). Running disparity
is a binary parameter with either the value negative (-) or the
value pos iti ve (+).
After powering on, the Transmitter may assume either a
positive or negative value for its initial running disparity. Upon
transmission of any Transmission Character, the transmitter
will select the proper version of the Transmission Character
based on the current running disparity value, and the Trans-
mitter shall calculate a new value for its running disparity
based on the contents of the transmitted character. Special
Character codes C1.7 and C2.7 can be used to force the trans-
mission of a specif ic Spe cial Ch aracte r with a spe cific ru nning
disparity as required for some special sequences in X3.230.
After po wering on , the Re ceive r may as sume either a p ositiv e
or negative value for its initial running disparity . Upon reception
of any Transmission Character, the Receiver shall decide
whether the Transmission Character is valid or invalid
accord ing t o the foll ow in g rul es and t a bles and shall ca lc ulate
a new va lue for it s Runnin g Dispari ty based on the cont ents of
the received character.
The following rules for running disparity shall be used to
calculate the new running-disparity value for Transmission
Characters that have been transmitted (Transmitter’s running
disparity) and that have been received (Receiver’s running
disparity).
Running disparity for a Transmission Character shall be calcu-
lated from sub-blocks, where the first six bits (abcdei) form one
sub-block and the second four bits (fghj) form the other
sub-block. Running disparity at the beginning of the 6-bit
sub-block is the running disparity at the end of the previous
T rans mission C haracter. Running d isparit y at the beg inning of
the 4-bit sub-block is the running disparity at the end of the
6-bit sub-block. Running disparity at the end of the Trans-
mission Character is the running disparity at the end of the
4-bit sub-block.
Running disparity for the sub-blocks shall be calculated as
follows:
1. Running disparity at the end of any sub-block is positive if
the sub-b lock contai ns more ones than zeros. It is also po s-
itive at the end of the 6-bit sub-block if the 6-bit sub-block
is 000 1 11, and it is positive a t the end of the 4-bit sub -block
if the 4-bit sub-block is 0011.
2. Running d ispar ity at the en d of any su b-block is negative if
the sub-block contains more zeros than ones. It is also
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negative at the end of the 6-bit sub-block if the 6-bit
sub-block is 1 1 1000, and it is negative at the end of the 4-bit
sub-block if the 4-bit sub-block is 1100.
3. Otherwise, running disparity at the end of the sub-block is
the same as at the beginning of the sub-block.
Use of the T ables for Generating T ransmission Characters
The appropriate entry in the table shall be found for the Valid
Data byte or the Special Character byte for which a Trans-
mission Character is to be generated (encoded). The current
value of the Transmitter’s running disparity shall be used to
select the Transmission Character from its corresponding
column. For each Transmission Character transmitted, a new
value of the running disparity shall be calculated. This new
value shall be used as the Transmitter’s current running
disparity for the next V alid Data byte or Special Character byte
to be encoded and transmitted. Table 1 shows naming notations
and examples of valid transmission characters.
Use of the Tables for Checking the Validity of Received
Transmission Characters
The column corresponding to the current value of the
Receiver’s runn ing dispari ty shall be sea rched for the received
Transmission Character. If the received Transmission
Character is found in the proper column, then the Trans-
mission Character is valid and the associated Data byte or
Special Character code is determined (decoded). If the
received Transmission Character is not found in that column,
then the Transmission Character is invalid. This is called a
code violation. Independent of the Transmission Character ’s
validi ty, the recei ve d Transm is si on Ch ara cte r sh all be u se d to
calcu late a new value of run ning disp arity . The new v alue shall
be used as the Receiver’s current running disparity for the next
rece iv ed Transm iss io n Ch arac ter.
Detection of a code violation does not necessarily show that
the Transmission Character in which the code violation was
detected is in error. Code violations may result from a prior
error that altered the running disparity of the bit stream which
did not result in a detectable error at the Transmission
Character in which the error occurred. Table 2 shows an
example of this behavior.
Table 1. Valid Transmission Characters
Data
Byte Name DIN or QOUT Hex Value765 43210
D0.0 000 00000 00
D1.0 000 00001 01
D2.0 000 00010 02
.
..
..
..
.
D5.2 010 000101 45
.
..
..
..
.
D30.7 111 11110 FE
D31.7 111 11111 FF
Table 2. Code Violations Resulting from Prior Errors
RD Character RD Character RD Character RD
Transmitted data character –D21.1 –D10.2 –D23.5 +
Transmitted bit stream –101010 1001 –010101 0101 –111010 1010 +
Bit stream after error –101010 1011 +010101 0101 +111010 1010 +
Decoded data character –D21.0 +D10.2 +Code Violation +
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Valid Data Characters (SC/D = LOW)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
D0.0 000 00000 100111 0100 011000 1011
D1.0 000 00001 011101 0100 100010 1011
D2.0 000 00010 101101 0100 010010 1011
D3.0 000 00011 110001 1011 110001 0100
D4.0 000 00100 110101 0100 001010 1011
D5.0 000 00101 101001 1011 101001 0100
D6.0 000 00110 011001 1011 011001 0100
D7.0 000 00111 111000 1011 000111 0100
D8.0 000 01000 111001 0100 000110 1011
D9.0 000 01001 100101 1011 100101 0100
D10.0 000 01010 010101 1011 010101 0100
D11.0 000 01011 110100 1011 110100 0100
D12.0 000 01100 001101 1011 001101 0100
D13.0 000 01101 101100 1011 101100 0100
D14.0 000 01110 011100 1011 011100 0100
D15.0 000 01111 010111 0100 101000 1011
D16.0 000 10000 011011 0100 100100 1011
D17.0 000 10001 100011 1011 100011 0100
D18.0 000 10010 010011 1011 010011 0100
D19.0 000 10011 110010 1011 110010 0100
D20.0 000 10100 001011 1011 001011 0100
D21.0 000 10101 101010 1011 101010 0100
D22.0 000 10110 011010 1011 011010 0100
D23.0 000 10111 111010 0100 000101 1011
D24.0 000 11000 110011 0100 001100 1011
D25.0 000 11001 100110 1011 100110 0100
D26.0 000 11010 010110 1011 010110 0100
D27.0 000 11011 110110 0100 001001 1011
D28.0 000 11100 001110 1011 001110 0100
D29.0 000 11101 101110 0100 010001 1011
D30.0 000 11110 011110 0100 100001 1011
D31.0 000 11111 101011 0100 010100 1011
D0.1 001 00000 100111 1001 011000 1001
D1.1 001 00001 011101 1001 100010 1001
D2.1 001 00010 101101 1001 010010 1001
D3.1 001 00011 110001 1001 110001 1001
D4.1 001 00100 110101 1001 001010 1001
D5.1 001 00101 101001 1001 101001 1001
D6.1 001 00110 011001 1001 011001 1001
D7.1 001 00111 111000 1001 000111 1001
D8.1 001 01000 111001 1001 000110 1001
D9.1 001 01001 100101 1001 100101 1001
D10.1 001 01010 010101 1001 010101 1001
D11.1 001 01011 110100 1001 110100 1001
D12.1 001 01100 001101 1001 001101 1001
D13.1 001 01101 101100 1001 101100 1001
D14.1 001 01110 011100 1001 011100 1001
D15.1 001 01111 010111 1001 101000 1001
D16.1 001 10000 011011 1001 100100 1001
D17.1 001 10001 100011 1001 100011 1001
D18.1 001 10010 010011 1001 010011 1001
D19.1 001 10011 110010 1001 110010 1001
D20.1 001 10100 001011 1001 001011 1001
D21.1 001 10101 101010 1001 101010 1001
D22.1 001 10110 011010 1001 011010 1001
D23.1 001 10111 111010 1001 000101 1001
D24.1 001 11000 110011 1001 001100 1001
D25.1 001 11001 100110 1001 100110 1001
D26.1 001 11010 010110 1001 010110 1001
D27.1 001 11011 110110 1001 001001 1001
D28.1 001 11100 001110 1001 001110 1001
D29.1 001 11101 101110 1001 010001 1001
D30.1 001 11110 011110 1001 100001 1001
D31.1 001 11111 101011 1001 010100 1001
D0.2 010 00000 100111 0101 011000 0101
D1.2 010 00001 011101 0101 100010 0101
D2.2 010 00010 101101 0101 010010 0101
D3.2 010 00011 110001 0101 110001 0101
Valid Data Characters (SC/D = LO W) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
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D4.2 010 00100 110101 0101 001010 0101
D5.2 010 00101 101001 0101 101001 0101
D6.2 010 00110 011001 0101 011001 0101
D7.2 010 00111 111000 0101 000111 0101
D8.2 010 01000 111001 0101 000110 0101
D9.2 010 01001 100101 0101 100101 0101
D10.2 010 01010 010101 0101 010101 0101
D11.2 010 01011 110100 0101 110100 0101
D12.2 010 01100 001101 0101 001101 0101
D13.2 010 01101 101100 0101 101100 0101
D14.2 010 01110 011100 0101 011100 0101
D15.2 010 01111 010111 0101 101000 0101
D16.2 010 10000 011011 0101 100100 0101
D17.2 010 10001 100011 0101 100011 0101
D18.2 010 10010 010011 0101 010011 0101
D19.2 010 10011 110010 0101 110010 0101
D20.2 010 10100 001011 0101 001011 0101
D21.2 010 10101 101010 0101 101010 0101
D22.2 010 10110 011010 0101 011010 0101
D23.2 010 10111 111010 0101 000101 0101
D24.2 010 11000 110011 0101 001100 0101
D25.2 010 11001 100110 0101 100110 0101
D26.2 010 11010 010110 0101 010110 0101
D27.2 010 11011 110110 0101 001001 0101
D28.2 010 11100 001110 0101 001110 0101
D29.2 010 11101 101110 0101 010001 0101
D30.2 010 11110 011110 0101 100001 0101
D31.2 010 11111 101011 0101 010100 0101
D0.3 011 00000 100111 0011 011000 1100
D1.3 011 00001 011101 0011 100010 1100
D2.3 011 00010 101101 0011 010010 1100
D3.3 011 00011 110001 1100 110001 0011
D4.3 011 00100 110101 0011 001010 1100
D5.3 011 00101 101001 1100 101001 0011
D6.3 011 00110 011001 1100 011001 0011
Valid Data Characters (SC/D = LOW) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
D7.3 011 00111 111000 1100 000111 0011
D8.3 011 01000 111001 0011 000110 1100
D9.3 011 01001 100101 1100 100101 0011
D10.3 011 01010 010101 1100 010101 0011
D11.3 011 01011 110100 1100 110100 0011
D12.3 011 01100 001101 1100 001101 0011
D13.3 011 01101 101100 1100 101100 0011
D14.3 011 01110 011100 1100 011100 0011
D15.3 011 01111 010111 0011 101000 1100
D16.3 011 10000 011011 0011 100100 1100
D17.3 011 10001 100011 1100 100011 0011
D18.3 011 10010 010011 1100 010011 0011
D19.3 011 10011 110010 1100 110010 0011
D20.3 011 10100 001011 1100 001011 0011
D21.3 011 10101 101010 1100 101010 0011
D22.3 011 10110 011010 1100 011010 0011
D23.3 011 10111 111010 0011 000101 1100
D24.3 011 11000 110011 0011 001100 1100
D25.3 011 11001 100110 1100 100110 0011
D26.3 011 11010 010110 1100 010110 0011
D27.3 011 11011 110110 0011 001001 1100
D28.3 011 11100 001110 1100 001110 0011
D29.3 011 11101 101110 0011 010001 1100
D30.3 011 11110 011110 0011 100001 1100
D31.3 011 11111 101011 0011 010100 1100
D0.4 100 00000 100111 0010 011000 1101
D1.4 100 00001 011101 0010 100010 1101
D2.4 100 00010 101101 0010 010010 1101
D3.4 100 00011 110001 1101 110001 0010
D4.4 100 00100 110101 0010 001010 1101
D5.4 100 00101 101001 1101 101001 0010
D6.4 100 00110 011001 1101 011001 0010
D7.4 100 00111 111000 1101 000111 0010
D8.4 100 01000 111001 0010 000110 1101
D9.4 100 01001 100101 1101 100101 0010
Valid Data Characters (SC/D = LO W) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
CY7B92
3
CY7B93
3
Document #: 38-02017 Rev. *C Page 20 of 30
D10.4 100 01010 010101 1101 010101 0010
D11.4 100 01011 110100 1101 110100 0010
D12.4 100 01100 001101 1101 001101 0010
D13.4 100 01101 101100 1101 101100 0010
D14.4 100 01110 011100 1101 011100 0010
D15.4 100 01111 010111 0010 101000 1101
D16.4 100 10000 011011 0010 100100 1101
D17.4 100 10001 100011 1101 100011 0010
D18.4 100 10010 010011 1101 010011 0010
D19.4 100 10011 110010 1101 110010 0010
D20.4 100 10100 001011 1101 001011 0010
D21.4 100 10101 101010 1101 101010 0010
D22.4 100 10110 011010 1101 011010 0010
D23.4 100 10111 111010 0010 000101 1101
D24.4 100 11000 110011 0010 001100 1101
D25.4 100 11001 100110 1101 100110 0010
D26.4 100 11010 010110 1101 010110 0010
D27.4 100 11011 110110 0010 001001 1101
D28.4 100 11100 001110 1101 001110 0010
D29.4 100 11101 101110 0010 010001 1101
D30.4 100 11110 011110 0010 100001 1101
D31.4 100 11111 101011 0010 010100 1101
D0.5 101 00000 100111 1010 011000 1010
D1.5 101 00001 011101 1010 100010 1010
D2.5 101 00010 101101 1010 010010 1010
D3.5 101 00011 110001 1010 110001 1010
D4.5 101 00100 110101 1010 001010 1010
D5.5 101 00101 101001 1010 101001 1010
D6.5 101 00110 011001 1010 011001 1010
D7.5 101 00111 111000 1010 000111 1010
D8.5 101 01000 111001 1010 000110 1010
D9.5 101 01001 100101 1010 100101 1010
D10.5 101 01010 010101 1010 010101 1010
D11.5 101 01011 110100 1010 110100 1010
D12.5 101 01100 001101 1010 001101 1010
Valid Data Characters (SC/D = LOW) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
D13.5 101 01101 101100 1010 101100 1010
D14.5 101 01110 011100 1010 011100 1010
D15.5 101 01111 010111 1010 101000 1010
D16.5 101 10000 011011 1010 100100 1010
D17.5 101 10001 100011 1010 100011 1010
D18.5 101 10010 010011 1010 010011 1010
D19.5 101 10011 110010 1010 110010 1010
D20.5 101 10100 001011 1010 001011 1010
D21.5 101 10101 101010 1010 101010 1010
D22.5 101 10110 011010 1010 011010 1010
D23.5 101 10111 111010 1010 000101 1010
D24.5 101 11000 110011 1010 001100 1010
D25.5 101 11001 100110 1010 100110 1010
D26.5 101 11010 010110 1010 010110 1010
D27.5 101 11011 110110 1010 001001 1010
D28.5 101 11100 001110 1010 001110 1010
D29.5 101 11101 101110 1010 010001 1010
D30.5 101 11110 011110 1010 100001 1010
D31.5 101 11111 101011 1010 010100 1010
D0.6 110 00000 100111 0110 011000 0110
D1.6 110 00001 011101 0110 100010 0110
D2.6 110 00010 101101 0110 010010 0110
D3.6 110 00011 110001 0110 110001 0110
D4.6 110 00100 110101 0110 001010 0110
D5.6 110 00101 101001 0110 101001 0110
D6.6 110 00110 011001 0110 011001 0110
D7.6 110 00111 111000 0110 000111 0110
D8.6 110 01000 111001 0110 000110 0110
D9.6 110 01001 100101 0110 100101 0110
D10.6 110 01010 010101 0110 010101 0110
D11.6 110 01011 110100 0110 110100 0110
D12.6 110 01100 001101 0110 001101 0110
D13.6 110 01101 101100 0110 101100 0110
D14.6 110 01110 011100 0110 011100 0110
D15.6 110 01111 010111 0110 101000 0110
Valid Data Characters (SC/D = LO W) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
CY7B92
3
CY7B93
3
Document #: 38-02017 Rev. *C Page 21 of 30
D16.6 110 10000 011011 0110 100100 0110
D17.6 110 10001 100011 0110 100011 0110
D18.6 110 10010 010011 0110 010011 0110
D19.6 110 10011 110010 0110 110010 0110
D20.6 110 10100 001011 0110 001011 0110
D21.6 110 10101 101010 0110 101010 0110
D22.6 110 10110 011010 0110 011010 0110
D23.6 110 10111 111010 0110 000101 0110
D24.6 110 11000 110011 0110 001100 0110
D25.6 110 11001 100110 0110 100110 0110
D26.6 110 11010 010110 0110 010110 0110
D27.6 110 11011 110110 0110 001001 0110
D28.6 110 11100 001110 0110 001110 0110
D29.6 110 11101 101110 0110 010001 0110
D30.6 110 11110 011110 0110 100001 0110
D31.6 110 11111 101011 0110 010100 0110
D0.7 111 00000 100111 0001 011000 1110
D1.7 111 00001 011101 0001 100010 1110
D2.7 111 00010 101101 0001 010010 1110
D3.7 111 00011 110001 1110 110001 0001
D4.7 111 00100 110101 0001 001010 1110
D5.7 111 00101 101001 1110 101001 0001
D6.7 111 00110 011001 1110 011001 0001
D7.7 111 00111 111000 1110 000111 0001
D8.7 111 01000 111001 0001 000110 1110
D9.7 111 01001 100101 1110 100101 0001
D10.7 111 01010 010101 1110 010101 0001
D11.7 111 01011 110100 1110 110100 1000
D12.7 111 01100 001101 1110 001101 0001
D13.7 111 01101 101100 1110 101100 1000
D14.7 111 01110 011100 1110 011100 1000
D15.7 111 01111 010111 0001 101000 1110
D16.7 111 10000 011011 0001 100100 1110
D17.7 111 10001 100011 0111 100011 0001
D18.7 111 10010 010011 0111 010011 0001
Valid Data Characters (SC/D = LOW) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
D19.7 111 10011 110010 1110 110010 0001
D20.7 111 10100 001011 0111 001011 0001
D21.7 111 10101 101010 1110 101010 0001
D22.7 111 10110 011010 1110 011010 0001
D23.7 111 10111 111010 0001 000101 1110
D24.7 111 11000 110011 0001 001100 1110
D25.7 111 11001 100110 1110 100110 0001
D26.7 111 11010 010110 1110 010110 0001
D27.7 111 11011 110110 0001 001001 1110
D28.7 111 11100 001110 1110 001110 0001
D29.7 111 11101 101110 0001 010001 1110
D30.7 111 11110 011110 0001 100001 1110
D31.7 111 11111 101011 0001 010100 1110
Valid Data Characters (SC/D = LO W) (continued)
Data
Byte
Name
Bits Current RD−Current RD+
HGF EDC-
BA abcdei fghj abcdei fghj
CY7B92
3
CY7B93
3
Document #: 38-02017 Rev. *C Page 22 of 30
Valid Special Character Codes and Sequences (SC/D = H IGH) [1, 2]
S.C. Byte Name S.C. Code Name Bits Current RD−Current RD+
HGF EDCBA abcdei fghj abcdei fghj
K28.0 C0.0 (C00) 000 00000 001111 0100 110000 1011
K28.1 C1.0 (C01) 000 00001 001111 1001 110000 0110
K28.2 C2.0 (C02) 000 00010 001111 0101 110000 1010
K28.3 C3.0 (C03) 000 00011 001111 0011 110000 1100
K28.4 C4.0 (C04) 000 00100 001111 0010 110000 1101
K28.5 C5.0 (C05) 000 00101 001111 1010 110000 0101
K28.6 C6.0 (C06) 000 00110 001111 0110 110000 1001
K28.7 C7.0 (C07) 000 00111 001111 1000 110000 0111
K23.7 C8.0 (C08) 000 01000 111010 1000 000101 0111
K27.7 C9.0 (C09) 000 01001 110110 1000 001001 0111
K29.7 C10.0 (C0A) 000 01010 101110 1000 010001 0111
K30.7 C11.0 (C0B) 000 01011 011110 1000 100001 0111
Idle C0.1 (C20) 001 00000 −K28.5+,D21.4,D21.5,D21.5,repeat[3]
R_RDY C1.1 (C21) 001 00001 −K28.5+,D21.4,D10.2,D10.2,repeat[4]
EOFxx C2.1 (C22) 001 00010 −K28.5,Dn.xxx0[5]+K28.5,Dn.xxx1[5]
Follows K28.1 for ESCON Connect−SOF (Rx indication only)
C−SOF C7.1 (C27) 001 00111 001111 1000 110000 0111
Follows K28.5 for ESCON Passive−SOF (R x indication only)
P−SOF C7.2 (C47) 010 00111 001111 1000 110000 0111
Code Rule Violation and SVS Tx Pattern
Exception C0.7 (CE0) 111 00000 100111 1000[6] 011000 0111[6]
−K28.5 C1.7 (CE1) 111 00001 001111 1010[29] 001111 1010[29]
+K28.5 C2.7 (CE2) 111 00010 110000 0101[30] 110000 0101[30]
Running Disparity Violation Pattern
Exception C4.7 (CE4) 111 00100 110111 0101[31] 001000 1010[31]
Notes:
1. All codes not shown are reserved.
2. Notation for Special Character Byte Name is consistent with Fibre Channel and ESCON naming conventions. Special Character Code Name is intended to
describe binary information present on I/O pins. Common usage for the name can either be in the form used for describing Data patterns (i.e., C0.0 through
C31.7), or in hex notation (i.e., Cnn where nn = the specified value between 00 and FF).
3. C0.1 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD when input is held for only one byte time. If held longer, transmitter begins sending the
repeating transmit sequence −K28.5+, D21.4, D21.5, D21.5, (repeat all four bytes)... defined in X3.230 as the primitive signal “Idle word.” This Special Character
input must be held for four (4) byte times or multiples of four bytes or it will be truncated by the new data. The receiver will never output this Special Character ,
since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.
4. C1.1 = Transmit Negative K28.5 (−K28.5+) disregarding Current RD when input is held for only one byte time. If held longer, transmitter begins sending the
repeating transmit sequence −K28.5+, D21.4, D10.2, D10.2,(repeat all four bytes)... defined in X3.230 as the primitive signal “Receiver_Ready (R_RDY).” This
Special Character input must be held for four (4) byte times or multiples of four bytes or it will be truncated by the new data.
The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7 and the subsequent bytes are decoded as data.
5. C2.1 = Transmit either −K28.5+ or +K28.5− as determined by Current RD and modify the Transmission Character that follows, by setting its least significant
bit to 1 or 0. If Current RD at the start of the following character is plus (+) the LSB is set to 0, and if Current RD is minus (−) the LSB beco mes 1. Th is mod ificatio n
allows construction of X3.230 “EOF” frame delimiters wherein the second data byte is determined by the Current RD.
For exampl e, to send “EOFdt” the controller could issue the sequence C2.1−D21.4− D21.4−D21.4, and the HOTLink Transmitter will send either
K28.5−D21.4−D21.4−D21.4 or K28.5−D21.5− D21.4−D21.4 based on Current RD. Likewise to send “EOFdti” the controller could issue the sequence
C2.1−D10.4−D21.4−D21.4, and the HOTLink Transmitter will send either K28.5−D10.4−D21.4− D21.4 or K28.5−D10.5−D21.4− D21.4 based on Current RD.
The receiver will never output this Special Character, since K28.5 is decoded as C5.0, C1.7, or C2.7, and the subsequent bytes are decoded as data.
6. C0.7 = Transmit a deliberate code rule violation. The code chosen for this function follows the normal Running Disparity rules. Transmission of this Special
Character has the same effect as asserting SVS = HIGH.
The receiver will only output this Special Character if the Transmission Character being decoded is not found in the tables.
CY7B92
3
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3
Document #: 38-02017 Rev. *C Page 23 of 30
Maximum Ratings
(Abov e wh ic h th e us eful life may b e i mpaired. For us er gui de-
lines, not tested.)
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Output Current into TTL Outputs (LOW)......................30 mA
Output Current into PECL Outputs (HIGH)................–50 mA
Static Discharge Voltage...........................................> 4001V
(per MIL-STD-883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
CY7B923/CY7B933 Electrical Characteristics Over the Operating Range[7]
Parameter Description Test Conditions Min. Max. Unit
TTL OUTs, CY7B923: RP; CY7B933: Q0−7, SC/D, RVS, RDY, CKR, SO
VOHT Output HIGH Voltage IOH = - 2 mA 2.4 V
VOLT Output LOW Voltage IOL = 4 mA 0.45 V
IOST Output Short Circuit Current VOUT = 0V[8] –15 –90 mA
TTL INs, C Y7B923: D0−7, SC/D, SVS, ENA, ENN, CKW, FOTO, B ISTEN; CY7B933: RF, REFCLK, BISTEN
VIHT Input HIGH Voltage Com’l, Ind’l, and Mil 2.0 VCC V
Ind’l and Mil (CKW and
FOTO, only) 2.2 VCC V
VILT Input LOW Voltage –0.5 0.8 V
IIHT Input HIGH Current VIN = VCC –10 +10 µA
IILT Inp ut LOW Current VIN = 0.0V –500 µA
Transmi tter PECL-Compatible Output Pins: OUTA+, OUTA−, OUTB+, OUTB−, OUTC+, OUTC−
VOHE Output HIGH Voltage
(VCC referenced) Load = 50Ω to
VCC – 2V Com’l VCC – 1.03 VCC – 0.83 V
Ind’l and Mil VCC – 1.05 VCC – 0.83 V
VOLE Output LOW Voltage
(VCC referenced) Load = 50Ω to
VCC – 2V Com’l VCC – 1.86 VCC – 1.62 V
Ind’l and Mil VCC – 1.96 VCC – 1.62 V
VODIF Output Differential Voltage
|(OUT+) − (OUT−)| Load = 50Ω to VCC – 2V 0.6 V
Receiver PECL-Compatible Input Pins: A/B, SI, INB
VIHE Input HIGH Voltage Com’l VCC – 1.165 VCC V
Ind’l and Mil VCC – 1.14 VCC V
VILE Input LOW Voltage Com’l 2.0 VCC – 1.475 V
Ind’l and Mil 2.0 VCC – 1.50 V
IIHE[9] Input HIGH Current VIN = VIHE Max. +500 µA
IILE[9] In put LOW Current VIN = VILE Min. +0.5 µA
Differential Line Receiver Input Pins: INA+, INA−, INB+, INB−
VDIFF Input Differential Voltage
|(IN+) – (IN−)| 50 mV
VIHH Highest Input HIGH Voltage VCC V
VILL Lowest Input LOW Voltage 2.0 V
IIHH Input HIGH Current VIN = VIHH Max. 750 µA
IILL[10] Input LO W Current VIN = VILL Min. –200 µA
Notes:
7. See the last page of this specification for Group A subgroup testing information.
8. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
9. Ap plies to A/ B only.
10. Input currents are always positive at all voltages above VCC/2.
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3
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3
Document #: 38-02017 Rev. *C Page 24 of 30
Miscellaneous Typ. Max.
ICCT[11] Transmitter Power Supply
Current Freq. = Max. Com’l 65 85 mA
Ind’l and Mil 75 95 mA
ICCR[12] Receiver Power Supply
Current Freq. = Max. Com’l 120 155 mA
Ind’l and Mil 135 160 mA
Capacitance[13]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f0 = 1 MHz, VCC = 5.0V 10 pF
AC Test Loads and Waveforms
Notes:
1 1. Maximum ICCT is measured with VCC = Max ., one PECL ou tput pair loaded with 50 ohms to VCC − 2.0V , and other PECL outputs tied to VCC. T ypical ICCT is measured with VCC
= 5.0V, TA = 25°C, one outpu t pai r load ed with 50 ohms t o V CC − 2.0 V, others tied to V CC, BISTEN = LOW . ICCT includes curr ent into VCCQ (pin 9 and pin 22) o nly. Current into
VCCN is determin ed by PECL load currents, ty pically 30 mA with 50 ohms to VCC − 2.0V. Each a dditional enabled PEC L pair add s 5 mA to ICCT and an addi tional lo ad current to
VCCN as describe d. When calcula ting the contrib ution of PECL load cur rents to chip pow er dissip ation, the out put load current shou ld be multipl ied by 1V ins tead o f VCC.
12. Maximum ICCR is measured with VCC = Max., RF = LOW , and outputs unloaded. T ypical ICCR is measured with VCC = 5.0V , TA = 25°C, RF = LOW, BISTEN = LOW, and outputs
unloaded. ICCR includes c urrent i nto VCCQ (pins 21 an d 24). C urrent into VCCN (pin 9) is det ermined by the tot al TTL out put bu ffe r qui escent c urrent plus the sum o f all the l oad
currents for each output pin. The total buffer quiescent current is 10mA max., and max. TTL load current for each output pin can be calculated as follows: Where RL= equivalent
load resistance, CL= capacitive load, and Fpin= frequency in MHz of data on pin. A derating factor of 1.1 has been included to account for worst process corner
and temper atu re con di tion .
13. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
CY7B923/CY7B933 Electrical Characteristics Over the Operating Range[7] (continued)
Parameter Description Test Conditions Min. Max. Unit
2.0V
1.0V
3.0V
GND
2.0V
1.0V
5V
OUTPUT
(a) TTL AC Test Load (b) PECL AC Test Load
<1ns <1ns
80% 20%
80%
20%
<1ns <1ns
(c)TTL Input Test Waveform (d) PECL Input Test Waveform
R1
R2
CL
CLRL
R 1= 910Ω
R 2= 510Ω
CL<30pF
(Includes fixture and
probe capacitance)
RL= 50 Ω
CL<5pF
(Includes fixture and
probe capacitance)
VIHE
3.0V
VCC −2
VIHE
VILE VILE
[14][14]
II CCN
TTLPin =
[
0.95 + (VCCN -5) * 0.3
RL+CL* [
VCCN
2+1.5
] * F
pin
]
*1.1
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3
Document #: 38-02017 Rev. *C Page 25 of 30
Transmitter Switching Characteristics Over the Operating Range[7]
Parameter Description 7B923-155 7B923 7B923-400 UnitMin. Max Min. Max Min. Max
tCKW Wr i te Cl oc k Cyc le 62.5 66.7 30.3 62.5 25 62.5 ns
tBBit Time[15] 6.25 6.67 3.03 6.25 2.5 6.25 ns
tCPWH CKW Pulse Width HIGH 6.5 6.5 6.5 ns
tCPWL CKW Pulse Width LOW 6.5 6.5 6.5 ns
tSD Data Set-Up Time[16] 555ns
tHD Data Hold Time[16] 000ns
tSENP Enable Set-Up Time (to insure correc t RP)[17] 6tB + 8 6tB + 8 6tB + 8 ns
tHENP Enable Hold Time (to insure correct RP)[17] 000ns
tPDR Re ad Pu lse Rise Alignment[18] –4 2–4 2–4 2ns
tPPWH Read Pulse HIGH[18] 4tB–3 4tB–3 4tB–3 ns
tPDF Re ad Pulse Fall Alignment[18] 6tB–3 6tB–3 6tB–3 ns
tRISE PECL Output Rise Time 20−80% (PECL Test Load)[13] 1.2 1.2 1.2 ns
tFALL PECL Output Fall Time 80−20% (PECL Te st Load)[13] 1.2 1.2 1.2 ns
tDJ Deterministic Jitter (peak-peak)[13, 1 9] 35 35 35 ps
tRJ Random Jitter (peak-peak)[13, 20] 175 175 175 ps
tRJ Random Jitter (σ)[13,20] 20 20 20 ps
Receiver Switching Characteristics Over the Operating Range [7]
Parameter Description 7B933-155 7B933 7B933-400 UnitMin. Max Min. Max. Min. Max.
tCKR Read Clock Period (No Serial Data Input), REFCLK
as Reference[21] –1 +1 –1 +1 –1 +1 %
tBBit Time[22] 6.25 6.67 3.03 6.25 2.5 6.25 ns
tCPRH Read Clock Pulse HIGH 5tB–3 5tB–3 5tB–3 ns
tCPRL Read Clock Pulse LOW 5tB–3 5tB–3 5tB–3 ns
tRH RDY Hold Time tB–2.5 tB–2.5 tB–2.5 ns
tPRF RDY Pulse Fall to CKR Rise 5tB–3 5tB–3 5tB–3 ns
tPRH RDY Pulse Width HIGH 4tB–3 4tB–3 4tB–3 ns
tAData Access Time[23, 24] 2tB–2 2tB+4 2tB–2 2tB+4 2tB–2 2tB+4 ns
tROH Data Ho ld Time[23, 24] tB–2.5 tB–2.5 tB–2.5 ns
tHData Hold Time from CKR Rise [23, 24] 2tB–3 2tB–3 2tB–3 ns
tCKX REFCLK Cloc k Period Referenc ed to CKW of T rans-
mitter[25] –0.1 +0.1 –0.1 +0.1 –0.1 +0.1 %
Notes:
15. Transmitter tB is calc ulated as t CKW/10. The by te rat e is on e tent h of the bit rate.
16. Data includes D0−7, SC/D , SVS, ENA, ENN, and BISTEN. tSD and tHD mini mum timin g assu res corre ct da ta load on r ising edge of CKW, but not RP functi on or timing.
17. tSENP and t HENP timing insures corre ct RP fun ctio n and corr ect da ta load on the ri sing edge of C KW.
18. Loading on RP is the sta ndard TTL test load sh own i n p art (a) of AC Test Loads and Wavefo rms excep t C L = 15 pF.
19. While sending continuous K28.5s, RP unl oaded, output s loaded to 50Ω to VCC−2.0V, ov er the operat ing range .
20. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
range.
21. The pe riod of tCKR will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits above.
22. Receiver tB is cal culated as tCKR/10 if no da ta is bein g rece ived, or tCKW/10 if da ta i s be ing recei ved. S ee not e.
23. Data includes Q0−7, SC/D , and RVS.
24. tA, tROH, and t H spec ificat ions are only v alid i f all output s (CKR, RDY, Q0−7, SC/D, and R VS) ar e load ed with simil ar DC an d AC l oads.
25. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within 0.1% of the transmitter CKW frequency, necessitating a ±500-PPM crys tal .
26. The PECL switching threshold is the midpoint between the PECL− VOH, and VOL specifi cation ( approxi mately VCC − 1.35V). The TTL switc hing thre shold i s 1.5V.
27. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. St atic alignment is measured by sliding one bit edge in
3,000 nominal transitions until a byte er ror occurs.
28. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter < 50% Dj.
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tCPXH REFCLK Clock Pulse HIGH 6.5 6.5 6.5 ns
tCPXL REFCLK Clock Pulse LOW 6.5 6.5 6.5 ns
tDS Propagation Delay SI to SO (note PECL and TTL
thresholds)[26] 20 20 20 ns
tSA Stat ic Alignment[13, 27] 100 100 100 ps
tEFW Error Free Window[13, 28] 0.9tB0.9tB0.9tB
Receiver Switching Characteristics Over the Operating Range (continued)[7]
Parameter Description 7B933-155 7B933 7B933-400 UnitMin. Max Min. Max. Min. Max.
Switching Waveforms for the CY7B923 HOTLink Transmitter
CKW
ENA
D0–D7,
SC/D,
SVS,
BISTEN
RP
tSD
tCPWL
tHD
tPDR
VALID DATA
tCPWH
tCKW
tSENP tSD tHENP
tPDF DISABLED
ENABLED
tPPWH
NOTES 16,17
CKW tCPWL tCPWH
tCKW
ENN
D0–D7,
SC/D,
SVS,
BISTEN tSD tHD
VALID DATA
tSD tHD
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Switching W 0aveforms for the CY7B933 HOTLink Receiver
CKR
RDY
Q0−Q7,
SC/D,RVS,
tCPRL
tCPRH
tCKR
tPRH
tPRF
tRH
tAtROH
tH
REFCLK
tCPXL tCPXH
tCKX
SI
SO
VBB
tDS
1.5V
NOTE
INA± ,
INB±
tB/2−tSA
tB/2−tSA
Static Alignment
SAMPLE WINDOW
INA±
INB±
tB
tEFW
BIT CENTER BIT CENTER
Error-free Window
26
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Ordering Information
Speed Ordering Code Package
Name Package Type Operating
Range
Standard CY7B923-JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7B923-JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
CY7B923-SC S21 28-Lead Small Outline IC Commercial
400 CY7B923-400JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7B923-400JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
155 CY7B923-155JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7B923-155JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
Standard CY7B933-JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7B933-JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
CY7B933-SC S21 28-Lead Small Outline IC Commercial
400 CY7B933-400JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7B933-400JI J64 28-Lead plastic Leaded Chip Carrier Industrial
155 CY7B933-155JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7B933-155JI J64 28-Lead Plastic Leaded Chip Carrier Industrial
Notes:
29. C1.7 = Transmit Negative K28.5 (–K28.5+) disregarding Current RD.
The receiver will only output this Special Character if K28.5 is received with the wrong running disparity . The receiver will output C1.7 if −K28.5 is received with
RD+, otherwise K28.5 is decoded as C5.0 or C2.7.
30. C2.7 = Transmit Positive K28.5 (+K28.5–) disregarding Current RD.
The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C2.7 if +K28.5 is received with
RD−, otherwise K28.5 is decoded as C5.0 or C1.7.
31. C4.7 = Transmit a deliberate code rule violation to indicate a Running Disparity violation.
The receiver will only output this Special Character if the Transmission Character being decoded is found in the tables, but Running Disparity does not match.
This might indicate that an error occurred in a prior byte.
CKW
ENA
D0−7,
SC/D,
SVS
RP
K28.5 K28.5
DATA LATCHED IN
DATA SENT
DATA
OUTX±
TRANSMITTER LATENCY = 21 tB−10ns
DATA
Figure 7. CY7B923 Transmitter Data Pipeline
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© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. C ypress Semicond uctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
ESCON is a registered trademark of IBM. HOTLink is a registered trademark of Cypress Semiconductor . All product and comp any
names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
28-lead Plastic Leaded Chip Carrier J64
51-85001-A
28-lead (300-mil)Molded SOIC S21
51-85026-A
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Document History Page
Document Title: CY7B923/CY7B933 HOTLink Transmitter/Receiver
Document Number: 38-02017
REV ECN NO. Issue
Date Orig. of
Change Description of Change
** 105855 03/28/01 SZV Changed from Spec number: 38-00189 to 38-02017
*A 112164 03/25/02 REV Changed OUTA± pin description to improve consistency with diagram.
Changed INA± pin description to include what to do with unused pairs of inputs.
Changed Equation in note 6–old one made no sense.
*B 114562 03/27/02 BSS Changed Hotlink T rans mitte r/Rec eiv er to Hotlink Transmitter/Receiver.
*C 125525 04/01/03 OOR Removed all references to Military parts (Obsolete): CY7B923-LMB,
CY7B933-LMB
