B PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z86E15 CMOS Z8? 8-BiT OTP KEYBOARD CONTROLLER FEATURES ROM RAM* ie) Speed Device (KB) (Bytes) Lines (Mhz) Z86E15 4 188 32 5 Note: General-Purpose 4.5V to 5.5V Operating Range 0C to +70C Operating Temperature Range Low-Power Consumption: 60 mW @ 5 MHz Five Vectored, Priority Interrupts from Five Different Sources m@ A Programmable 8-Bit Counter/Timer, with 6-Bit Programmable Prescaler m Power-On-Reset (POR) Timer, Hardware Watch-Dog Timer (WDT) B Digital Inputs CMOS Levels with Internal Pull-Up Resistors m Four Direct Connect LED Drive Ports m = On-Chip RC Oscillator m Low System EMI Emission GENERAL DESCRIPTION The Z86E15 microcontroller (MCU) is a member of the sin- gle-chip 28 MCU family with 4 KB of EPROM and 188 bytes of general-purpose RAM. The Z86E15 is a pin-compatible, One-Time-Programma- ble (OTP) version of the 286K15 Keyboard Controller. Zilogs CMOS-microcontroller offers fast execution, effi- cient use of memory, sophisticated interrupts, input/output bit manipulation capabilities. To unburden the program from coping with real-time prob- lems such as counting/timing, the Z86E15 offers an on- chip counter/timer with a large number of user-selectable modes. Five different internal or external interrupt sources are maskable and prioritized in which a vectored address is provided for efficient interrupt subroutine handling and multitasking functions. The Z86E15 achieves low EMI by means of several modi- fications in the output drivers and clock circuitry of the de- vice. DS97KEY1501 PRELIMINARY 1Z86E15 OTP CMCS Z8 8-Bit OTP Keyboard Controller Zilog GENERAL DESCRIPTION (Continued) Notes: All signals with a preceding front slash, /, are active Low. For example, B/W (WORD is active Low); Connection Circuit Device /BW (BYTE is active Low, only). Power connections Power Veo Voo follow conventional descriptions below: Ground GND Vss S z = 6 QO < Voc GND Output Input | | Machine Timing & Inst. Control WDT ALU POR Counter/ Timers Flags Register Pointer Interrupt Control Register File Program 188 x 8-Bit Counter 0 Input (Bit Programmable) Open-Drain Open-Drain Output Output Figure 1. Z86E15 Functional Biock Diagram 2 PRELIMINARY DS97KEY 1501Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller PIN DESCRIPTION A P30 cj 1 406 P23 P31 oO FI P22 P32 I P21 P33 6 P20 *NC P37 *NC co P36 P27 & FI P35 P26 & HI P34 P25 q RCIN P24 Z86E15 mm AGND GND q DIP 1 GND vec o I VCC POO & -1 P17 Pol 1 P16 P02 o P15 P03 & P14 P04 oO I P13 POS & mI P12 P06 P14 P07 cj 20 21 P10 Notes: *Pin 5 and 6 used for testing Ground during normal operation. When Pin 5 is connected to V,,. Pin 6 is CLK OUT. When Pin 5 is connected to GND, Pin 6 outputs nothing. These pins must be tied to ground in application. Figure 2. 40-Pin DIP Configuration Table 1. 40-Pin DIP Pin identification Pin # Symbol Function Direction 1-4 P30-P33 Port 3, Pins 0,1,2,3 Input 5-6 NC Tied to GND 7-10 P27-P24 Port 2, Pins 7,6,5,4 In/Output 11 GND Ground 12 Voc Power Supply Input 13-20 P00-P07 Port 0, Pins 0,1,2,3,4,5,6,7 Output 21-28 P10-P17 Port 1, Pins 0,1,2,3,4,5,6,7 Output 29 Voc Power Supply 30 GND Ground 31 AGND Analog Ground 32 RCIN RCIN Input 33-36 P34-P37 Port 3, Pins 4,5,6,7 Output 37-40 P20-P23 Port 2, Pins 0,1,2,3 Input DS97KEY1501 PRELIMINARY 3Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Zilog PIN DESCRIPTION (Continued) OnNr OMNNr OR SOPee PNA gge opoononpaooopoog / 8 1 40 NC {7 395) NC P27 & mr P36 P26 & P35 P25 Mm P34 P24 co Z86E15 I RCIN GND oc PLCC NGC vec q AGND Poo c m GND Pot & FI VCC P02 1 P17 P03 17 296 NC 18 28 DOOOoOOoOodgOoOod TwWOONROrA MO TW O f@eeoeaaaaaandn Notes: Pins 5 and 6 used for testing. Ground during normal operation When Pin 43 is connected to V,,, Pin 44 is CLKOUT. When Pin 43 is connected to GND. Pin 44 outputs nothing. Figure 3. 44-Pin PLCC Pin Assignments Table 2. 44-Pin PLCC Pin Assignments Pin # Symbol Function Direction 1-4 P30-P33 Port 3, Pins 0,1,2,3 Input 5-7 NC Test Pins (GND) 8-11 P27-P24 Port 2, Pins 4,5,6,7 In/Output 12 GND Ground 13 Voc Power Supply 14-21 POO-P07 Port 0, Pins 0,1,2,3,4,5,6,7 Output 22-28 P10-P16 Port 1, Pins 0,1,2,3,4,5,6 Output 29 NC Not Connected 30 P17 Port 1, Pin 7 Output 31 Voc Power Supply 32 GND Ground 33 AGND Analog Ground 34 NC Not Connected 35 RCIN RCIN Input 36-38 P34-P36 Port 3, Pins 4,5,6,7 Output 39 NC Not Connected 40 P37 Port 3, Pin 7 Output 41-44 P20-P23 Port 2, Pins 0,1,2,3 in/Output PRELIMINARY DS97KEY1501Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller o8 8s Fa O Z OOn SeeereeEsSas Dogon oooo oo 33 23 P37 34 22) P16 P20 mF P15 P21 q m P14 P22 ry P13 P23 c mI P12 P30 P ry P11 P31 o rm P10 P32 tH P07 P33 bE P06 NC c hy POS NC 444 12k, P04 \1 1 DOODUDOOOCOUCO SESLAI885Hs zag 6 Qaagadc Notes: Pins 43 and 44 are used for testing ground during normal operation. When Pin 45 is connected to V,,, Pin 46 is CLKOUT. When Pin 45 is connected to GND. Pin 46 outputs nothing. Figure 4. 44-Pin QFP Pin Assignments Table 3. 44-Pin QFP Pin Identification Pin # Symbol Function Direction 1 NC Not Connected 2-5 P24-P27 Port 2, Pins 4,5,6,7 In/Output 6 GND Ground 7 Voc Supply Voltage 8-15 P00-P07 Port 0, Pins 0,1,2,3,4,5,6,7, Output 16-22 P10-P16 Port 1, Pins 0,1,2,3,4,5,6 Output 23 NC Not Connected 24 P17 Port 1, Pin 7 Output 25 Voc Supply Voltage 26 GND Ground 27 AGND Analog Ground 28 NC Not Connected 29 RCIN RCIN Input 30-32 P34-P36 Port 3, Pins 4,5,6 Output 33 NC Not Connected 34 P37 Port 3, Pin 7 Output 35-38 P20-P23 Port 2, Pins 0,1,2,3 Input 39-42 P30-P33 Port 3, Pins 0,1,2,3 Input 43-44 NC Test Pins (GND) DS97KEY1501 PRELIMINARYZ86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Zilog ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units Voc Supply Voltage 0.3 +7.0 V Tore Storage Temp -65 +150 C T, Oper Ambient Temp 0 +105 C Note: * Voltage on all pins with respect to GND. Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; operation of the device at any condition above those indicated in the operational sec- tions of these specifications is not implied. Exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed here apply for standard test con- ditions as noted. All voltages are referenced to GND. Pos- itive current flows into the referenced pin (Figure 5). From Output Under Test T+ T- Figure 5. Test Load Diagram CAPACITANCE T, = 25C; V., = GND = OV; f = 1.0 MHz; unmeasured pins returned to GND. Parameter Max Input Capacitance 12 pF Output Capacitance 12 pF /O Capacitance 12 pF Frequency tolerance +10% 6 PRELIMINARY DS97KEY1501Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller DC CHARACTERISTICS Veg = 5.0V + 10% @ 0C to +70C Sym _ Parameter Min Max Typ* Unit Condition Vo, Clock Input High Voltage 0.7 Veg Veg + 0.3V 2.5 V__ Driven by External Clock Generator V., Clock Input Low Voltage GND -0.3 0.2 Vo, 1.5 V__ Driven by External Ciock Generator Vu Input High Voltage 0.7 Veg Vogt 0.3 2.5 V Vi Input Low Voltage GND -0.3 0.2 Vo, 1.5 V Vo, Output High Voltage Veg 0.4 4.7 Vlg, =-2.0 mA (Port 2 out. in P/P Mode) Vo, Output High Voltage Veg 0.6 V_14,=-2-0 mA (see note 1 below.) Vox Output High Voltage Veo 71.0 Vs 1y4,=-2.0 pA (Port 0 and Port 1) Vo, Output Low Voltage 4 Vo Iy=4mA Vo. Output Low Voltage 8 V_ Iy= 4 mA (see note 1 below.) lo Output Low 10 20 MA Vy = Vo, -2.2 V (see note 1, 2 below.) lo Output Leakage -1 1 <1 HA Vi, = OV, 5.25V lee Veco Supply Current 12 6 mA @5.0 MHz loc, HALTt Mode Current 2 mA @5.0 MHz loos STOP Mode Current 10 pA R, Pull Up Resistor 6.76 14.04 10.4 Kohm Port 20-25 and Port 30-33 R, Pull Up Resistor (P26-P27) 1.8 3 2.4 Kohm (PO&P1) 200 500 Kohm Notes: * Typical @ 25C 1. Ports P37-P34. These may be used for LEDs or as general-purpose outputs requiring high sink current. 2. V,,= 5.0V + 5% @ 0C to + 70C DS97KEY1501 PRELIMINARY 7Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Zilog AC ELECTRICAL CHARACTERISTICS T, = 0C to 70C Voc 5 MHz No Symbol Parameter Note[4] Min Max Units Notes 1 TpC Input Clock Period 5.0V 200 250 ns 1 2 TrC,TfC Clock Input Rise & Fall Times 5.0V 25 ns 1 3 TwC Input Clock Width 5.0V 37 ns 1 4 TwTinL ~ Timer Input Low Width 5.0V 70 ns 1 5 TwTinH Timer Input High Width 5.0V 2.5TpC 1 6 TpTin Timer Input Period 5.0V 4TpC 1 7 TrTin, Timer Input Rise & Fall Timer 5.0V 100 ns 8A TwIL Int. Request Low Time 5.0V 70 ns 1,2 8B TwIL Int. Request Low Time 5.0V 3TpC 1,3 9 TwlH Int. Request Input High Time 5.0V 3TpC 1,2 10 Twsm Stop Mode Recovery Width Spec 5.0V 5TpC ns 14 Tost Oscillator Start-up Time 5.0V 5TpC 12 Twat Watch-Dog Timer Delay Time 5.0V 53 ms 13 Tpor Power--On Reset 5.0V 106 130 ms Notes: 1. Timing Reference uses 0.7 V,, for a logic 1 and 0.2 V.,, for a logic 0. 2. Interrupt request through Port 3 (P31-P33). 3. Interrupt request through Port 3 (P30). 8 PRELIMINARY DS97KEY1501: Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller Clock TIN IRQN Clock Setup Stop Mode E Recovery Source \ Figure 6. Additional Timing DS97KEY1501 PRELIMINARYZ86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller PIN FUNCTIONS Zilog RCIN. A precision resistor is connected between this pin Port 0 (P07-P00). Port 0 is an 8-bit, CMOS-compatible and the power supply to form the precision RC oscillator. open-drain output (Figure 7). CLKOUT. This pin is the system clock of the Z8 and runs at the frequency of the RC oscillator (Test only). (Weak Pullup Port 0 iow Pad oo Output | Figure 7. Port 0 Configuration 10 PRELIMINARY DS97KEY1501Zilog Port 1 (P17-P10). Port 1 is an 8-bit, CMOS-compatible open-drain output port (Figure 8). Z86E15 OTP CMOS Z8@ 8-Bit OTP Keyboard Controller 1 Weak Pullup Output Z86KXX 8 > Port 1 ro = Pad Output ~ Figure 8. Port 1 Configuration DS97KEY1501 PRELIMINARY 11Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller PIN FUNCTIONS (Continued) Zilog Port 2 (P27-P20). Port 2 is an 8-bit, CMOS-compatible | P20-P25 have 10.4K (+35%) pull-up resistors. P26-P27 Port with 4-bit input, 4-bit programmable I/O (Figure 9). have 2.4K (+25%) pull-up resistors. K 4 Input Z86KXX <P ttl] fi VO i __ <i] VCC (a) Ports P20-P23 Input 10.4K O <4 O Gr Pad vcc S 10.4 kOhm OEN Open-Drain (b) Ports P24-P25 Pad OUT 5 : vec 2.4K OEN Open-Drain (c) Ports P26-P27 Pad pg Figure 9. Port 2 Configuration yIL,TL_, WH 12 PRELIMINARY DS97KEY1501Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller Port 3 (P37-P30). Port 3 is an 8-bit, CMOS-compatible Port 3 is configured under software contro! to provide four four-fixed input (P33-P30) and four-fixed output (P37-P34) external interrupt request signals (IRQO-IRQ3). /O port. Port 3 inputs have 10.4 Kohm pull-up resistors. Outputs are capabie of directly driving LED. Z8eKxx [* \ Ports (a) Port 3 P34-P37 Output ++4 WwW Pad (b) Port 3 P30-P33 10.4 kOhms Pad Figure 10. Port 3 Configuration DS97KEY1501 PRELIMINARY 13Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller PIN FUNCTIONS (Continued) Program Memory. The 16-bit program counter addresses 4 KB of program memory space at internal locations (Fig- ure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations have six 16-bit vectors that correspond to the five available interrupts. Byte 12 to byte 4095 consists of on-chip, mask pro- grammed ROM. Addresses 4096 and greater are re- served. 65535 Reserved 4096 4095 4K Location of EPROM First Byte of Instruction NN HF ------------ Executed 12 a, After RESET Reserved 10 Reserved 9 IRQ4 8 IRQ4 IRQ3 Interrupt Q Vector 6 IRQ3 (Lower Byte) ~_] 5 ~~ IRQ2 4, IRQ2 interrupt ~] Q Vector 3 IRQ1 (Upper Byte) 2 IRQ1 1 IRQO 0 IRQO Figure 11. Program Memory Map R253 RP |D7}D6| D5| D4] D3| D2} D1} Do Reserved Working Register Group Default setting after RESET = 00000000 Figure 12. Register Pointer Register Zilog Register File. The register file (Figure 13) consists of four I/O port registers, 188 general-purpose registers (exclud- ing POO-PO3), and 11 control and status registers (R3-RO, R191-R4, and R255-R240, respectively). The instructions can access registers directly or indirectly through an 8-bit address field. This allows short, 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into nine working-register groups, each occu- pying 16 continuous locations. The Register Pointer ad- dresses the starting location of the active working-register group. LOCATION IDENTIFIERS R28 Stack Pointer (Bits 7-0) SPL R26 Reserved R253 Register Pointer RP R252 Program Control Flags FLAGS R251 Interrupt Mask Register IMR R250 interrupt Request Register IRQ R249 Interrupt Priority Register IPR R248 Reserved R247 Port 3 Mode P3M R246 Port 2 Mode P2M R245 TO Prescaler PREQ R244 Timer/Counter0 TO R243 Reserved R242 Reserved R241 Timer Mode TMR R240 Reserved Not Implemented R 191 General-Purpose Registers R4 R3 Port 3 P3 R2 Port 2 P2 Ri Port 1 Pi RO Port 0 PO Note:* Will not be reset with a STOP Mode Recovery. Figure 13. Register File Configuration 14 PRELIMINARY DS97KEY1501: Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller Z8 STANDARD CONTROL REGISTERS REGISTER POINTER 7L ef} 5] 4} shyt] | REGISTER . . . % FF SPL Working Register Reserved Register Group Pointer % FE Reserved % FD RP % FC FLAGS % FB IMR % FA IRQ % F9 IPR % FB Reserved * % F7 P3M * % FE P2M Z8 Reg. File %FF % FS PREO %FO % F4 TO %F3 Reserved Not % F2 Reserved available FI TMA %BF % FO Reserved oad %OF %00 REG. GROUP (0) PORT REGISTERS % (0) 03 P3 % (0) 02 P2 * % (0) 01 P1 Note: ~ Will not be reset with a STOP Mode Recovery % (0) 00 PO Figure 14, Register File Architecture DS97KEY1501 PRELIMINARY 15Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Zilog PIN FUNCTIONS (Continued) Counter/Timers. There is an 8-bit programmable counter/timer (TO) driven by its own 6-bit programmable prescaler (Figure 15). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. The pres- caler drives its counter, which decrements the value (1 to 256) on the prescaler overflow. When both the counter and prescaler reach the end of count, a timer interrupt request, IRQ4, is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counter can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode) The counter, but not the prescaler, is read at any time without disturbing its value or count mode. Internal Data Bus wy 1 Write | Lt Read {p PREO Initial Value Initial Value Current Value osc Register Register Register 6-Bit 8-bit i $$ tir Down meat Down Counter Counter > |IRQ4 Figure 15. Counter/Timers Block Diagram 16 PRELIMINARY DS97KEY 1501Zilog Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Interrupts. The Z86E15 has five different interrupts from five different sources. These interrupts are maskable and prioritized (Figure 16). The five sources are divided as fol- lows: four sources are claimed by Port 3 lines P33-P30, and the other is claimed by the counter/timer. The Interrupt Masked Register globally or individually enables or dis- ables the five interrupts requests. When more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the Interrupt Priority register. All interrupts are vectored through locations in the program memory. When an interrupt machine cycle is activated an interrupt request is granted. Thus, this disables all of the subsequent inter- rupts, saves the Program Counter and status flags, and then branches to the program memory vector location re- served for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service IRQO-IRQ4 : . : fy routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs IRQ are masked and the interrupt request register is polled to | 1 1 . determine which of the interrupt request needs service. eee RC Oscillator. The Z86E15 provides an internal capacitor | | | y1. to accommodate an RC oscillator configuration. A 1% pre- cision resistor is necessary to achieve t10% accurate fre- IMR quency oscillation. 5Y The Z86E15 also accepts external clock from (RCIN) with IPR 4 (AGND) connected to V,, (Figure 17). Global Interrupt Enable Lb Interrupt ~C | Priority VoG Request Logic 4 1% Vector Select Precision RCIN Figure 16. interrupt Block Diagram NC CLKOUT RC Oscillator RCIN VCC AGND External Clock Figure 17. RC Oscillator Configuration DS97KEY1501 PRELIMINARY 17Z86E15 OTP CMOS Z8@ 8-Bit OTP Keyboard Controller Zilog PIN FUNCTIONS (Continued) Watch-Dog Timer. The Watch-Dog Timer (WDT) is acti- vated automatically by power-on if it is enabled in the Mask Option. The WDT is a retriggerable one-shot timer that re- sets the Z8 if it reaches its terminal count. The WDT is driv- en by the system clock. It must be refreshed at least once during each time cycle by executing the WDT instruction. WDT can be enabled by Mask Option. (Figure 18) WDT Hot bit. Bit 7 of the Interrupt Request register (IRQ register FAH) determines whether a hot start or cold start occurred. A cold start is defined as reset occurring from VCC Internal YY \ Reset __ A ~<a POR | power-up of the Z86E15 (the default upon power-up is 0). A hot start occurs when a WDT time-out has occurred (bit 7 is set to 1). Bit 7 of the IRQ register is read-only and is automatically reset to 0 when read. 294912 Watch-Dog Timer . The WDT time-out is a . WDT During HALT (D5-R250). This bit determines wheth- er or not the WDT is active during HALT Mode. The default is 1, and a 1 indicates active during HALT. cc oe 18 Tpe [fo NL ad ' Reset . | Delay * Reset Delay = POR 147 ms +10% at 4 MHz. Figure 18. WDT Turn-On Timing After Reset 18 PRELIMINARY DS97KEY 1501Zilog Z86E15 OTP CMOS Z&@ 8-Bit OTP. Keyboard Controller Power-On-Reset (POR). A timer circuit is triggered by the system oscillator and is used for the Power-On Reset (POR) timer function. The POR time allows V,,, and the os- cillator circuit to stabilize before instruction execution be- gins. POR period is defined as: POR (ms) = 589824 f (Hz) The POR timer circuit is a one-shot timer triggered by one of two conditions: 1. Power fail to Power OK status 2. Stop-Mode Recovery The POR time is a nominal 147 ms +10%. At 4 MHz the POR timer is bypassed after Stop-Mode Recovery. HALT. HALT turns off the internal CPU clock, but not the RC oscillator. The counter/timer and external interrupts IRQO, IRQ1, IRQ2, and IRQ3 remain active. The Z86E15 is recovered by interrupts, either externally or internally (Figure 19). STOP. This instruction turns off the internal clock and os- cillator. It reduces the standby current to less than 10 pA. The STOP Mode is terminated by a reset only or external reset. This causes the processor to restart the application program at address 000C (HEX) or the active external in- terrupt vector. In order to enter STOP (or HALT) Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (Opcode=FFH) immediately be- fore the appropriate sleep instruction, such as: FF NOP ; Clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode P20-P26, P30-P33 | je R250 IRQ | 07] D6} ps} D4] D3] p2| 1} vo} IRQO = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input {RQ3 = P30 Input IRQ4 =TO WDT during HALT 0 OFF* 1 ON Stop Flag 0 PORMWDT* 1 Stop Recovery WDT Hot Bit (Read Only) 0 POR* 1 WOT Timeout * On RESET Figure 19. IRQ Register The Bit 6 of IRQ Registers are flags for Stop Mode Recov- ery (Figure 20). Cold or Warm Start (D6). This bit is set upon entering STOP Mode. A 0 (cold) indicates that the device is awak- ened by a POR/WDT RESET. A 1 (warm) indicates that the device is awakened by a SMR source. This bit is reset when read. Negative transition on any of the designated row input pins or host data line will recover Z86E15 from STOP Mode. To Internal RESET Figure 20. Stop-Mode Recovery Source DS97KEY 1501 PRELIMINARY 19Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Z8 CONTROL REGISTER DIAGRAMS R241 TMR D7} D6} D5] D4] D3} D2} 01] DO |_ 0 = No Function 1 = Load TO 0 = Disable TO Count 1 = Enable TO Count Reserved (Must be 0) Figure 21. Timer Mode Register (F1,: Read/Write) R244 TO D7 | D6 | D5] D4} D3] D2] Di | DO (When WRITE) (Range: 1-256 Decimal 01-00 HEX) TO Current Value (When READ) Counter/Timer 0 Register Figure 22. (F4,: Read/Write) R245 PREO D7{ D6] D5] D4] D3} D2] D1} DO L_ Count Mode 0 =Tg Single Pass 1 = Tg Modulo N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Prescaler 0 Register Figure 23. (F5,: Write Only) Zilog R246 P2M D7} D6} D5] D4} D3} D2] Di} DO Reserved P24-P27 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT Port 2 Mode Register Figure 24. (F6,: Write Only) R247 P3M D7] D6} DS} D4] D3} D2} 017 DO L_ 0 Port (24-27) Open-Drain 1 Port (24-27) Push-Pull Reserved (Must be 0) Port 2 Open Drain Mode Register Figure 25. (F7,,: Write Only) R249 IPR | b7| 08] 5} D4] 03] D2] D1 00] a Interrupt Group Priority Reserved = 000 C>A>B=001 A>B>C=010 A>C>B=0t1 B>C>A=100 C>B>Az 101 B>A>C=110 Reserved = 111 IRQ1, IRQ4 Priority (Group C) 0 =IRQt > IRQ4 1 =IRQ4>IRQ1 IRQO, IRQ2 Priority (Group B) 0 = IRQ2 > IRQO0 1 =IRQO >IRQ2 Reserved Reserved (Must be 0) Figure 26. Interrupt Priority Register (F9,: Write Only) 20 PRELIMINARY DS97KEY 1501Zilog Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller R250 IRQ pa| o1| DO D7} D6] DS4 D4] D wo IRQO = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P30 Input IRQ4 = TO Stop Delay 0 OFF* 1 ON Stop Flag 0 POR/WDT* 1 Stop Recovery WOT Hot Bit (Read Only) 0 POR* * On RESET 1 WDT Timeout Figure 27. Interrupt Request Register (FA,,: Read/Write) R251 IMR D7] D6} D5] D4} D3] D2y D1] DO 1 Enables [RQ0-IRQ4 (DO= IRQO) Reserved (Must be 0) 1 Enables Interrupts Figure 28. Interrupt Mask Register (FB,,: Read/Write) R252 Flags D7} D6] DS} D4] D3] D2; Di} DO L User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 29. Flag Register (FC,,: Read/Write) R253 RP D7] 06} D5} D4] 03] D2} D1} DO Working Registers r4 5 Register Pointer r6 7 Register Pointer Figure 30. (FD,,: Read/Write) R255 SPL D7] D6] D5] 04] D3} D2} D1] DO Stack Pointer Lower Byte (SP0-SP7) Stack Pointer Figure 31. (FF,,: Read/Write) DS97KEY1501 PRELIMINARY 21Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Zilog PROGRAMMING Signals Required for E15 EPROM The TEST1 pin will be used as a high voltage pin. The high voltage from this pin will be used to program the EPROM. It will also need to be at high voltage in order for any EPROM operation to be done. When this pin is at high voltage, then an internal signal V,,,, is generated from the high voltage detect circuitry and the signal being active will be used to multiplex the remaining pins that are required in all the EPROM operations. TEST1 (Vpp) This pin is designated a high voltage pin on the Z86E15. All EPROM operations will require a high voltage on this pin. The V,, supplies the high voltage for the programming of the EPROM. Note: The pins listed below are based on the condition that the V,, is in high voltage. P33 (Mode Latch) The Z86E15 utilizes this pin when high will be used to latch the mode. This condition will only happen when the V,,, is active. P32 (Oeb-Output Enable) This regular pin controls the direction of the data bus. The signal generated goes into the EPROM as the precharge signal. When this signal is low, the data is output from the EPROM. When the signal is high, data is input to the EPROM. When the signal is high, the EPROM is precharged. When the signal is low, the EPROM is evaluated. P31 (EPMH) This regular pin is used to read the option bits when the EPROM is protected. When the signal is high, during POR, the option bits can be read from the EPROM. P30 (Volt_Clamp) This regular pin used the signal to disable the voltage clamp circuit. When the signal is low, the voltage clamp circuit is en- abled. When the signal is high, the voltage clamp circuit is disabled and margin testing can be done. P20 (CEb) This regular pin on the Z86E15 is the chip enable signal for the EPROM. This signal will be input to the EPROM when Vpph is high. This is an active low signal. P21 (PGMb-Program Mode) This regular pin on the Z86E15 allows the EPROM to be programmed when the signal is logic low, and when the signal V,,, is high. The data on the databus will be pro- grammed into the location that is addressed by the internal counter that generates the address for the EPROM. P22 (epadr_clk) and P23 (epadr_rst) The address is generated by an internal address counter which is clocked through the signal epadr_clk. Each clock increments the counter by one. The counter can be reset to zero by the epadr_rst signal. Both epadr_clk and epadr_rst are external signals. The epadr_rst signal is an active high signal. Data to the EPROM The data to the EPROM are multiplexed with the pins as shown below in Figure 32: (Data <7.0>) Data Pin DO P34 D1 P35 D2 P36 D3 P37 D4 P27 D5 P26 D6 P25 D7 P24 Figure 32. Data Pin Assignments Option Bit Programming In order to program the option bits, the Mode 3 should be used. This can be done as follows: m The V,, pin is set to high voltage (device pin TEST1 is driven to high voltage). m The epadr_rst signal is driven high for one cycle to reset the address counter (device pin P23). m Three clocks are given on the epadr_clk pin (P22), which will advance the counter to the count of 3. m= The Mode Latch signal (P33) is driven high for one cycle to latch in the data into the Mode Register. m The address counter is again reset and the required data is programmed into location 0, which will program the 8 locations of the option bits. In the Z86E15, bits 0, 1 and 2 will be used as there are only 3 option bits for this device. 22 PRELIMINARY DS97KEY1501286E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller PACKAGE INFORMATION 20 { PO OOO oo eS Se eo ese SYMBOL MILLIMETER INCH MIN MAX MIN MAX Al 0.51 1.02 | .020 | .040 C 1 AZ 318 | 3.94 | .125 | .155 8 0.38 | 0.53 | .015 | .021 B1 1.02 | 1.52 | .o40 | .060 c 0.23 ] 0.38 | .oo9 | .015 FoococoMToeaoaoooooao D 2.07 | 52.58 | 2.050 2.070 15.24 | 15.75 | .600 | .620 D EI 13.59 | 14.22 | 535 | .560 2.54 TYP .100 TYP eA 15.49 | 16.76 | .610 | .660 a1 L 3.05 | 3.81 | .120 | .150 { Ql 1.52 | 1.91 7 .060 | .075 = = a2 S 1.52 | 2.29 | .060 .090 aks 4b 5 B CONTROLLING DIMENSIONS : INCH c fy L + y _t At b~-_ e4 _+ Figure 33. 40-Pin DIP Package Diagram TO CENTER OF RADII Le A D Al 45 " 026/.020 6 1 40 4 _ falalalatalalwialalal at tT B 7 D 39 _L & A 1219/1067 ul A 048/042 z ] Oo 4] 2 = me D El 9 A ue ; z aj a 17 P 29 L HS 18 28 p 1142064 045/.025 SYMBOL MILLIMETER INCH NOTES: MIN MAX MIN MAX LEAR ORIN Oy, Fa Paar Tase Tse ao 3. DIMENSION : _MM , Al 2.41 | 292 | .095 | us INCH D/E 17.40 17.65 685 695 DL/EL 16.51 16.66 650 656 De 15.24 16.00 600 630 iB 127 TYP 050 TYP Figure 34. 44-Pin PLCC Package Diagram DS97KEY1501 PRELIMINARY 23Z86E15 OTP CMOS Z8 8-Bit OTP Keyboard Controller Zilog HD > A2 Al SYMBOL MILLIMETER INCH MIN MAX MIN MAX Al 0.05 | 0.25 002 010 AZ 2.00 2.25 078 089 b 0.25 0.45 010 018 0.13 | 0.20 005 008 HD 13.70 | 14.15 539 557 D 9.90 | 10.10 390 398 HE 13.70 | 14.15 539 587 E 9.90 10.10 .390 398 al 0.80 TYP 0315 TYP L 0.60 1.20 .024 047 c NOTES: 1, CONTROLLING DIMENSIONS : MILLIMETER 2. LEAD COPLANARITY : MAX .10 004" Figure 35. 44-Pin QFP Package Diagram 24 PRELIMINARY DS97KEY 1501Z86E15 OTP Zilog CMOS Z8 8-Bit OTP Keyboard Controller ORDERING INFORMATION 5 MHz 5 MHz 5 MHz 40-Pin DIP 44-Pin PLCC 44-Pin QFP Z86E1505PSC Z86E1505VSC Z86E1505FSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Package Environmental P = Plastic DIP C = Plastic Standard V = Plastic Leaded Chip Carrier F = Quad Flat Pack Temperature S = 0C to +70C Speed + 05 = 5 MHz Example: Z 86E1505P SC is a Z86E15, 05 MHz, DIP, 0 to +70C, Plastic Standard Flow L_ Environmental Flow Temperature Package Speed Product Number Zilog Prefix DS97KEY1501 PRELIMINARY 25Zilog Preliminary Product Specification DS97KEY1501 Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems and delays. No production release is authorized or committed until the Customer and Zilog have agreed upon a Customer Procurement Specification for this project. Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non- conformance with some aspects of the CPS may be found, either by Zilog or its customers in the course of further application and characterization work. In addition, Zilog cautions that delivery may be uncertain at times, due to start-up yield issues. Low Margin: Customer is advised that this product does not meet Zilog's internal guardbanded test policies for the specification requested and is supplied on an exception basis. Customer is cautioned that delivery may be uncertain and that, in addition to all other limitations on Zilog liability stated on the front and back of the acknowledgement, Zilog makes no claim as to quality and reliability under the CPS. The product remains subject to standard warranty for replacement due to defects in materials and workmanship. 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilogs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com