1. General description
The 74HC132; 74HCT 132 is a quad 2-input NAND gate with Schmitt-tr igger input s. Input s
include clamp diodes. This enables the use of current limiting resistors to interface inputs
to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input
signals into sharply defined jitter-free output signals.
2. Features and benefits
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 20 0 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Rev. 4 — 1 December 2015 Product data sheet
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 2 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temper ature range Name Description Version
74HC132D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width
3.9 mm SOT108-1
74HCT132D
74HC132DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3 mm SOT337-1
74HCT132DB
74HC132PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74HCT132PW
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one
Schmitt trigger)
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 3 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Fig 4. Pin configuration SO1 4 an d (T)SSOP14
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Table 2. Pin de scription
Symbol Pin Description
1A to 4A 1, 4, 9, 12 data input
1B to 4B 2, 5, 10, 13 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
VCC 14 supply voltage
Table 3. Function table[1]
Input Output
nA nB nY
LLH
LHH
HLH
HHL
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 4 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -20 mA
IOoutput curren t 0.5 V < VO < VCC +0.5V - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation SO14, and (T)SSOP14 packages [2] -500mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC132 74HCT132 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 5 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max Min Max
74HC132
VOH HIGH-level
output voltage VI= VT+ or VT
IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI= VT+ or VT
IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =6.0V - - ±0.1 - ±1.0 - ±1.0 A
ICC supply current VI = VCC or GND; IO=0A;
VCC =6.0V --2.0- 20 - 40A
CIinput
capacitance -3.5- - - - -pF
74HCT132
VOH HIGH-level
output voltage VI= VT+ or VT; VCC = 4.5 V
IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V
IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI= VT+ or VT; VCC = 4.5 V
IO = 20 A; - 0 0.1 - 0.1 - 0.1 V
IO = 4.0 mA; - 0.15 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC =5.5V - - ±0.1 - ±1.0 - ±1.0 A
ICC supply current VI=V
CC or GND; IO = 0 A;
VCC =5.5V --2.0- 20 - 40A
ICC additional
supply current per input pin;
VI=V
CC 2.1 V; IO=0A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
- 30 108 - 135 - 147 A
CIinput
capacitance -3.5- - - - -pF
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 6 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD=C
PD VCC2fiN+ (CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
Table 7. Dynamic characteristics
GND = 0 V; CL= 50 pF; for load circuit see Figure 6.
Symbol Parameter Conditions 25 C40 C to +125 CUnit
Min Typ Max Max
(85 C) Max
(125 C)
74HC132
tpd propagation delay nA, nB to nY; see Figure 5 [1]
VCC = 2.0 V - 36 125 155 190 ns
VCC = 4.5 V - 13 25 31 38 ns
VCC = 5.0 V; CL=15pF - 11 - - - ns
VCC = 6.0 V - 10 21 26 32 ns
tttransition time see Figure 5 [2]
VCC = 2.0 V - 19 75 95 110 ns
VCC = 4.5 V - 7 15 19 22 ns
VCC = 6.0 V - 6 13 16 19 ns
CPD power dissipation
capacitance per package; VI=GNDtoV
CC [3] -24- - -pF
74HCT132
tpd propagation delay nA, nB to nY; see Figure 5 [1]
VCC = 4.5 V - 20 33 41 50 ns
VCC = 5.0 V; CL=15pF - 17 - - - ns
tttransition time VCC = 4.5 V; see Figure 5 [2] - 7 15 19 22 ns
CPD power dissipation
capacitance per package;
VI=GNDtoV
CC 1.5 V [3] -20- - -pF
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 7 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
12. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5. Input to output propagation delays
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Table 8. Measur ement points
Type Input Output
VMVMVXVY
74HC132 0.5VCC 0.5VCC 0.1VCC 0.9VCC
74HCT132 1.3 V 1.3 V 0.1VCC 0.9VCC
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 6. Test circuit for measuring switching times
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 8 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
13. Transfer characteristics
14. Transfer characteristics waveforms
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC132 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
74HCT132 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 7 and Figure 8.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ Max Min Max Min Max
74HC132
VT+ positive-going
threshold
voltage
VCC = 2.0 V 0.7 1.18 1.5 0.7 1.5 0.7 1.5 V
VCC = 4.5 V 1.7 2 .3 8 3.15 1.7 3.15 1.7 3.15 V
VCC = 6.0 V 2.1 3.14 4.2 2.1 4.2 2.1 4.2 V
VTnegative-going
threshold
voltage
VCC = 2.0 V 0.3 0.63 1.0 0.3 1.0 0.3 1.0 V
VCC = 4.5 V 0.9 1.67 2.2 0.9 2.2 0.9 2.2 V
VCC = 6.0 V 1.2 2.26 3.0 1.2 3.0 1.2 3.0 V
VHhysteresis
voltage VCC = 2.0 V 0.2 0.55 1.0 0.2 1.0 0.2 1.0 V
VCC = 4.5 V 0.4 0.71 1.4 0.4 1.4 0.4 1.4 V
VCC = 6.0 V 0.6 0.88 1.6 0.6 1.6 0.6 1.6 V
74HCT132
VT+ positive-going
threshold
voltage
VCC = 4.5 V 1.2 1.41 1.9 1.2 1.9 1.2 1.9 V
VCC = 5.5 V 1.4 1.59 2.1 1.4 2.1 1.4 2.1 V
VTnegative-going
threshold
voltage
VCC = 4.5 V 0.5 0.85 1.2 0.5 1.2 0.5 1.2 V
VCC = 5.5 V 0.6 0.99 1.4 0.6 1.4 0.6 1.4 V
VHhysteresis
voltage VCC = 4.5 V 0.4 0.56 - 0.4 - 0.4 - V
VCC = 5.5 V 0.4 0.60 - 0.4 - 0.4 - V
Fig 7. Transfer characteristics Fig 8. Transfer characteristics definitions
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 9 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
a. VCC =2.0V b. V
CC =4.5V
c. VCC =6.0V
Fig 9. Typical 74HC132 transfer characteristics
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 10 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd =f
i(trICC(AV) +t
fICC(AV))VCC where:
Padd = additional power dissipation (W);
fi= input frequency (MHz);
tr=rise time (ns); 10%to90%;
tf= fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 11
and Figure 12.
An example of a relaxation circuit using the 74HC132; 74HCT132 is shown in Figure 13.
a. VCC =4.5V b. V
CC =5.5V
Fig 10. Typica l 74HCT132 transfer character istics
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 11 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
(1) Positive-going edge.
(2) Negative-going edge.
Fig 11. Average additional supply current as a function of VCC for 74HC132; linear chan ge of VI between 0.1VCC
to 0.9VCC.
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(2) Negative-going edge.
Fig 12. Average addi tiona l su pply curren t as a fu ncti on of V CC for 74H CT13 2; linear change of VI betwe en 0.1V CC
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 12 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
For 74HC132 and 74HCT132:
For K-factor, see Figure 14
Fig 13. R el ax ation oscillator
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Fig 14. Typical K-factor for relaxation oscillator
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 13 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
16. Package outline
Fig 15. Package outline SOT108-1 (SO14)
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 14 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 15 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
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74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 16 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
17. Abbreviations
18. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT132 v.4 20151201 Product data sheet - 74HC_HCT132 v.3
Modifications: Type numbers 74HC132N and 74HC T132N (SOT27-1) removed.
74HC_HCT132 v.3 201208 30 Product data sheet - 74HC_HCT132_CNV v.2
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Figure 14 added (typical K-factor for relaxation oscillator).
74HC_HCT132_CNV v .2 19970826 Product specification - -
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 17 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental ,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support , life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for t he customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessa ry
testing for the customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or inte llectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
74HC_HCT132 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 1 December 2015 18 of 19
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qualif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
© NXP Semiconductors N.V. 2015. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 1 December 2015
Document identifier: 74HC_HCT132
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
21. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Transfer characteristics . . . . . . . . . . . . . . . . . . 8
14 Transfer characteristics waveforms. . . . . . . . . 8
15 Application information. . . . . . . . . . . . . . . . . . 10
16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
20 Contact information. . . . . . . . . . . . . . . . . . . . . 18
21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19