LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 LMC6041 CMOS Single Micropower Operational Amplifier Check for Samples: LMC6041 FEATURES DESCRIPTION 1 * * * * * 2 Low Supply Current: 14 A (Typ) Operates from 4.5V to 15.5V Single Supply Ultra Low Input Current: 2 fA (Typ) Rail-to-Rail Output Swing Input Common-Mode Range Includes Ground APPLICATIONS * * * * * * * Battery Monitoring and Power Conditioning Photodiode and Infrared Detector Preamplifier Silicon Based Transducer Systems Hand-Held Analytic Instruments pH Probe Buffer Amplifier Fire and Smoke Detection Systems Charge Amplifier for Piezoelectric Transducers Ultra-low power consumption and low input-leakage current are the hallmarks of the LMC6041. Providing input currents of only 2 fA typical, the LMC6041 can operate from a single supply, has output swing extending to each supply rail, and an input voltage range that includes ground. The LMC6041 is ideal for use in systems requiring ultra-low power consumption. In addition, the insensitivity to latch-up, high output drive, and output swing to ground without requiring external pull-down resistors make it ideal for single-supply batterypowered systems. Other applications for the LMC6041 include bar code reader amplifiers, magnetic and electric field detectors, and hand-held electrometers. This device is built with TI's advanced Double-Poly Silicon-Gate CMOS process. See the LMC6042 for a dual, and the LMC6044 for a quad amplifier with these features. Connection Diagrams Top View Figure 1. 8-Pin SOIC or PDIP Package See Package Number D0008A or P0008E Figure 2. Low-Leakage Sample and Hold 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1994-2013, Texas Instruments Incorporated LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) Differential Input Voltage Supply Voltage Supply Voltage (V+ - V-) 16V Output Short Circuit to V- See (3) Output Short Circuit to V+ See (4) Lead Temperature (Soldering, 10 sec.) 260C -65C to +150C Storage Temperature Range Junction Temperature 110C ESD Tolerance (5) 500V Current at Input Pin 5 mA Current at Output Pin 18 mA Current at Power Supply Pin 35 mA (V+) + 0.3V, (V-) - 0.3V Voltage at Input/Output Pin See (6) Power Dissipation (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 110C. Output currents in excess of 30 mA over long term may adversely affect reliability. Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. Human body model, 1.5 k in series with 100 pF. The maximum power dissipation is a function of TJ(max), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) - TA)/JA. Operating Ratings Temperature Range LMC6041AI, LMC6041I -40C TJ +85C 4.5V V+ 15.5V Supply Voltage See (1) Power Dissipation Thermal Resistance (JA) (1) (2) 2 (2) 8-Pin PDIP package 101C/W 8-Pin SOIC package 165C/W For operating at elevated temperatures the device must be derated based on the thermal resistance JA with PD = (TJ - TA)/JA. All numbers apply for packages soldered directly into a PC board. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 Electrical Characteristics Unless otherwise specified, all limits ensured for TA = TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified. Parameter VOS Test Conditions Typical (1) Input Offset Voltage 1 TCVOS Input Offset Voltage Average Drift IB Input Bias Current 0.002 IOS Input Offset Current 0.001 RIN Input Resistance CMRR Common Mode Rejection Ratio 0V VCM 12.0V V+ = 15V 75 Positive Power Supply Rejection Ratio 5V V+ 15V VO = 2.5V 75 -PSRR Negative Power Supply Rejection Ratio 0V V- -10V VO = 2.5V CMR Input Common-Mode Voltage Range V+ = 5V and 15V for CMRR 50 dB +PSRR LMC6041AI Limit (2) 3 6 mV 6.3 max V/C 4 4 pA max 2 2 pA max 68 62 dB 66 60 min 68 62 dB 66 60 min 94 84 74 dB 83 73 min -0.4 -0.1 -0.1 V 0 0 max V+ - 2.3V V+ - 2.3V V >10 Tera + Large Signal Voltage Gain RL = 100 k (3) Sourcing Sinking RL = 25 k (3) VO Output Swing 1000 500 + V - 2.5V V - 2.4V min 400 300 V/mV 300 200 min 180 90 V/mV 120 70 min 200 100 V/mV Sourcing 1000 160 80 min Sinking 250 100 50 V/mV 60 40 min 4.987 4.970 4.940 V 4.950 4.910 min 0.030 0.060 V 0.050 0.090 max 4.920 4.870 V 4.870 4.820 min 0.010 0.080 0.130 V 0.130 0.180 max 14.970 14.920 14.880 V 14.880 14.820 min 0.007 0.030 0.060 V 0.050 0.090 max 14.950 14.900 14.850 V 14.850 14.800 min 0.100 0.150 V 0.150 0.200 max V+ = 5V RL = 100 k to V+/2 0.004 V+ = 5V RL = 25 k to V+/2 V+ = 15V RL = 100 k to V+/2 V+ = 15V RL = 25 k to V+/2 4.980 0.022 (1) (2) (3) Units (Limit) 3.3 1.3 V+ - 1.9V AV LMC6041I Limit (2) Typical Values represent the most likely parametric norm. All limits are ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V VO 11.5V. For Sinking tests, 2.5V VO 7.5V. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 3 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TA = TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified. Parameter ISC Output Current V+ = 5V Test Conditions Typical (1) LMC6041AI Limit (2) LMC6041I Limit (2) 22 16 13 mA 10 8 min 16 13 mA 8 8 min 15 15 mA 10 10 min 21 mA min Sourcing, VO = 0V Sinking, VO = 5V ISC Output Current V+ = 15V IS Supply Current 21 Sourcing, VO = 0V 40 Sinking, VO = 13V (4) 39 24 8 8 VO = 1.5V 14 20 26 A 24 30 max 26 34 A 31 39 max V+ = 15V (4) Units (Limit) 18 Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. AC Electrical Characteristics Unless otherwise specified, all limits ensured for TA = TJ = 25C. Boldface limits apply at the temperature extremes. V+ = 5V, V- = 0V, VCM = 1.5V, VO = V+/2, and RL > 1M unless otherwise specified. Parameter SR Slew Rate Test Conditions See (3) Typ (1) 0.02 LMC6041AI LMC6041I Limit (2) Units (Limit) 0.015 0.010 V/s 0.010 0.007 min Limit (2) GBW Gain-Bandwidth Product 75 kHz m Phase Margin 60 Deg en Input-Referred Voltage Noise F = 1 kHz 83 nV/Hz in Input-Referred Current Noise F = 1 kHz 0.0002 pA/Hz THD Total Harmonic Distortion F = 1 kHz, AV = -5 RL = 100 k, VO = 2 Vpp 5V Supply 0.01 % (1) (2) (3) 4 Typical Values represent the most likely parametric norm. All limits are ensured at room temperature (standard type face) or at operating temperature extremes (bold face type). V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified in the slower of the positive and negative slew rates. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 Typical Performance Characteristics VS = 7.5V, TA = 25C unless otherwise specified Supply Current vs Supply Voltage Offset Voltage vs Temperature of Five Representative Units Figure 3. Figure 4. Input Bias Current vs Temperature Input Bias Current vs Input Common-Mode Voltage Figure 5. Figure 6. Input Common-Mode Voltage Range vs Temperature Output Characteristics Current Sinking Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 5 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 7.5V, TA = 25C unless otherwise specified 6 Output Characteristics Current Sourcing Input Voltage Noise vs Frequency Figure 9. Figure 10. Power Supply Rejection Ratio vs Frequency CMRR vs Frequency Figure 11. Figure 12. CMRR vs Temperature Open-Loop Voltage Gain vs Temperature Figure 13. Figure 14. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 7.5V, TA = 25C unless otherwise specified Open-Loop Frequency Response Gain and Phase Responses vs Load Capacitance Figure 15. Figure 16. Gain and Phase Responses vs Temperature Gain Error (VOS vs VOUT) Figure 17. Figure 18. Common-Mode Error vs Common-Mode Voltage of Three Representative Units Non-Inverting Slew Rate vs Temperature Figure 19. Figure 20. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 7 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = 7.5V, TA = 25C unless otherwise specified 8 Inverting Slew Rate vs Temperature Non-Inverting Large Signal Pulse Response (AV = +1) Figure 21. Figure 22. Non-Inverting Small Signal Pulse Response Inverting Large-Signal Pulse Response Figure 23. Figure 24. Inverting Small Signal Pulse Response Stability vs Capacitive Load (AV = +1) Figure 25. Figure 26. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = 7.5V, TA = 25C unless otherwise specified Stability vs Capacitive Load (AV = 10) Figure 27. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 9 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6041 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain stability over a wider range of operating conditions than traditional micropower op-amps. These features make the LMC6041 both easier to design with, and provide higher speed than products typically found in this ultra-low power class. COMPENSATING FOR INPUT CAPACITANCE It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the LMC6041. Although the LMC6041 is highly stable over a wide range of operating conditions, certain precautions must be met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce phase margins. When high input impedance are demanded, guarding of the LMC6041 is suggested. Guarding input lines will not only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High Impedance Work.) Figure 28. Cancelling the Effect of Input Capacitance The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, Cf, around the feedback resistor (as in Figure 28 ) such that: (1) or R1 CIN R2 Cf (2) Since it is often difficult to know the exact value of CIN, Cf can be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on compensating for input capacitance. CAPACITIVE LOAD TOLERANCE Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 29. 10 Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 Figure 29. LMC6041 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 29, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 30 ). Typically a pull up resistor conducting 10 A or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). Figure 30. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6041, typically less than 2fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6041's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's inputs, as in Figure 31. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the LMC6041's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 would cause only 0.05 pA of leakage current. See Figure 34 for typical connections of guard rings for standard op-amp configurations. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 11 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com Figure 31. Example of Guard Ring in P.C. Board Layout Figure 32. Inverting Amplifier Figure 33. Follower Non-Inverting Amplifier Figure 34. Typical Connections of Guard Rings The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 35. 12 Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) Figure 35. Air Wiring Typical Single-Supply Applications (V+ = 5.0 VDC) The extremely high input impedance, and low power consumption, of the LMC6041 make it ideal for applications that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure transducers. Figure 36. Two Op-Amp Instrumentation Amplifier The circuit in Figure 36 is recommended for applications where the common-mode input range is relatively low and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less than 28 A. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board layout an important part of the overall system design (see Printed-Circuit-Board Layout for High Impedance Work). Referring to Figure 36, the input voltages are represented as a common-mode input VCM plus a differential input VD. Rejection of the common-mode component of the input is accomplished by making the ratio of R1/R2 equal to R3/R4. So that where, (3) A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the gain equation can be simplified: (4) Due to the "zero-in, zero-out" performance of the LMC6041, and output swing rail-rail, the dynamic range is only limited to the input common-mode range of 0V to VS-2.3V, worst case at room temperature. This feature of the LMC6041 makes it an ideal choice for low-power instrumentation systems. Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 13 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 37. Provisions have been made for low sensitivity trimming of CMRR and gain. Figure 37. Low-Power Two-Op-Amp Instrumentation Amplifier Figure 38. Low-Leakage Sample and Hold Figure 39. Instrumentation Amplifier Figure 40. 1 Hz Square-Wave Oscillator 14 Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 LMC6041 www.ti.com SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 Figure 41. AC Coupled Power Amplifier Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 15 LMC6041 SNOS610E - DECEMBER 1994 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E * 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright (c) 1994-2013, Texas Instruments Incorporated Product Folder Links: LMC6041 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LMC6041AIM NRND SOIC D 8 95 Non-RoHS & Non-Green Call TI Call TI -40 to 85 LMC60 41AIM LMC6041AIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 41AIM LMC6041AIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 41AIM LMC6041IM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 41IM LMC6041IMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC60 41IM LMC6041IN/NOPB ACTIVE PDIP P 8 40 RoHS & Green SN Level-1-NA-UNLIM -40 to 85 LMC60 41IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6041AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6041IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6041AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6041IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 ) 4 5 B 8X .012-.020 [0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 [0.11-0.25] 0 -8 .016-.050 [0.41-1.27] DETAIL A (.041) [1.04] TYPICAL 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X METAL SOLDER MASK OPENING EXPOSED METAL .0028 MAX [0.07] ALL AROUND SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL .0028 MIN [0.07] ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] 6X (.050 ) [1.27] SYMM 5 4 (R.002 ) TYP [0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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