KA3882CDTF - Fairchild Semiconductor

www.fairchildsemi.com

Rev. 1.0.1

Features

• Low Start Current 0.2mA (Typ)

• Op erating Range Up To 500kHz

• Cycle by Cycle Current Limiting

• Under Voltage Lock Out With Hysteresis

• Short Shutdown Delay Time: Typ.100ns

• High Current Totem-Pole Output

• Outp ut S wing Limi t ing: 22 V

Description

The KA 3882C /KA3 883C i s a fi xed PWM co ntroll er f or Of f

Line and DC to DC converter applications. The internal

circuits include an UVLO, a low start up current circuit, a

temperature compensated reference, a high gain error

amplifier, a current sensing comparator , and the high current

totem - pole ou t pu t for dr i vin g a P OWER MOSFET. Also the

KA3882C/KA3883C provides low start-up current below

0.3mA and short shutdown delay time typ. 100ns. The

KA3882C has the UVLO threshold of 16V (on) and

10V(off). The KA3883C is 8.4V(on) and 7.6V(off). The

KA3882C a nd KA3883C can operate withi n 100% duty

cycle.

8-DIP

8-SOP

Internal Block Diagram

SET/

RESET

VREF

Internal

Bias Good LOGIC

OSCILLATOR

UVLO

29V

22V

1/3

Error Amp

1/2VREF

C.S

Comp. PWM

LATCH

VREF

VFB

COMP

C.S

RT/CT

OUTPUT

VCC

GND

PWR

GND

KA3882C/KA3883C

SMPS Controller

KA3882C/KA3883C

Absolute Maximum Ratings

Electrical Characteristics

(VCC = 15V, RT = 10kΩ, CT = 3.3nF, TA = 0°C to +70°C ,Unless otherwise specified)

Parameter Symbol Value Unit

Supply Voltage VCC 30 V

Output Current IO±1 A

Analog Inputs (pin 2, 3) VI(ANA) -0.3 to 6.3 V

Error Amp. Output Sink Current ISINK(EA) 10 mA

Power Dissipation PD1W

Thermal Resistance, Junction-to-Air (Note4)

8-SOP

8-DIP Rθja 280

95 °C/W

Storage Temperature Tstg -65 ~ 150 °C

Parameter Symbol Conditions Min. Typ. Max. Unit

REFERENCE SECTION

Output Voltage VREF TJ = 25°C, IO = 1mA 4.9 5.0 5.1 V

Line Regulation ∆VREF VCC = 12V to 25V - 6 20 mV

Load Regulation ∆VREF IO = 1mA to 20mA - 6 25 mV

Output Short Circuit ISC Ta = 25°C - -100 -180 mA

OSILLATOR SECTION

Initial Accuracy FOSC TJ = 25°C475257kHz

Voltage Stability STVVCC = 12V to 25V - 0.2 1 %

Amplitude VOSC VPIN4, Peak to Peak - 1.7 - V

Discharge Current IDISCHG TJ = 25°C, Pin4 = 2V 7.8 8.3 8.8 mA

CURRENT SENSE SECTION

Gain GV(Note2, 3) 2.85 3 3.15 V/V

Maximum Input Signal VI(MAX) VPIN1 = 5V(Note2) 0.9 1.0 1.1 V

PSRR PSRR VCC = 12V to 25V (Note1, 2) - 70 - dB

Input Bias Current IBIAS -- -2 -10 uA

Delay to Output TDVPIN3 = 0 V to 2V (Note1) - 100 200 ns

KA3882C/KA3883C

Electrical Characteristics (Continued)

(VCC = 15V, RT = 10kΩ, CT = 3.3nF, TA = 0°C to +70°C, Unless otherwise specified)

* Adjust VCC above the start threshold before setting at 15V

Notes :

1. These parameters, although guaranteed, are not 100% tested in production.

2. Parameter measured at trip point of latch with V2 = 0V.

3. Gain def ine d as: G V = ∆VPIN1∆VPIN3(VPIN3 = 0 to 0.8V)

4. Junction-to-air thermal resistance test enviroments.

-. PCB info rm at i on ;

Board thicknes s : 1.6mm , Boar d dime nsion : 76.2 X 114.3 m m2 , Ref. : EIA / JSED51-3 and EIA / JSED51-7

-. Board structure; Using the single layer PCB.

Parameter Symbol Conditions Min. Typ. Max. Unit

ERROR AMPLIFIER SECTION

Input Voltage VITPIN1 = 2.5V 2.42 2.50 2.58 V

Input Bias Current IBIAS - - -0.3 -2 uA

Open Loop Gain GVO VO = 2V to 4V (Note1) 65 90 - dB

Unity Gain Bandwidth GBW TJ= 25°C (Note1) 0.7 1 - MHz

PSRR PSRR VCC = 12V to 25V (Note1) 60 70 - dB

Output Sink Current ISINK VPIN2 = 2.7V, VPIN1 = 1.1V 2 6 - mA

Output Source Current ISOURCE VPIN2 = 2.3V, VPIN1 = 5.0V -0.5 -0.8 - mA

Output High Voltage VOH VPIN2 = 2.3V, R1 = 15kΩ to GND 5 6 - V

Output Low Voltage VOL VPIN2 = 2.7V, R1 = 15kΩ to Pin8 - 0.8 1.1 V

OUTPUT SECTION

Output Low Level VOL ISINK = 20mA - 0.1 0 .4 V

ISINK = 200mA - 1.5 2 .2 V

Output High Level VOH ISOURCE = 20mA 13 13.5 - V

ISOURCE = 200mA 12 13.5 - V

Rise Time tRTJ = 25°C, C1 = 1nF (Note1) - 40 100 ns

Fall Time tFTJ = 25°C, C1 = 1nF (Note1) - 40 100 ns

Output Voltage Swing Limit VOLIM VCC = 27V, C1 = 1nF - 22 - V

UNDER VOLTAGE LOCKOUT SECTION

Start Threshold VTH KA3882C 15 16 17 V

KA3883C 7.8 8.4 9.0 V

Min. Operating Voltage

( After turn on ) VTL KA3882C 9 10 11 V

KA3883C 7.0 7.6 8.2 V

PWM SECTION

Maximum Duty Cycle DMAX KA3882C/KA3883C 94 96 100 %

Minimum Duty Cycle DMIN ---0%

TOTAL STANDBY CURRENT

Start-Up Current IST --0.20.4mA

Operating Supply Current ICC VPIN2 = VPIN3 = 0V - 11 17 mA

VCC Zener Voltage VZICC = 25mA - 29 - V

KA3882C/KA3883C

Mechanical Dimensions

Package

6.40 ±0.20

3.30 ±0.30

0.130 ±0.012

3.40 ±0.20

0.134 ±0.008

#4 #5

0.252 ±0.008

9.20 ±0.20

0.79

2.54

0.100

0.031

()

0.46 ±0.10

0.018 ±0.004

0.060 ±0.004

1.524 ±0.10

0.362 ±0.008

9.60

0.378 MAX

5.08

0.200

0.33

0.013

7.62

0~15°

0.300

MAX

MIN

0.25 +0.10

–0.05

0.010+0.004

–0.002

8-DIP

KA3882C/KA3883C

Mechanical Dimensions (Continued)

Package

4.92 ±0.20

0.194 ±0.008

0.41 ±0.10

0.016 ±0.004

1.27

0.050

5.72

0.225

1.55 ±0.20

0.061 ±0.008

0.1~0.25

0.004~0.001

6.00 ±0.30

0.236 ±0.012

3.95 ±0.20

0.156 ±0.008

0.50 ±0.20

0.020 ±0.008

5.13

0.202 MAX

#4 #5

0~8°

0.56

0.022

()

1.80

0.071

MAX0.10

MAX0.004

MAX

MIN

+0.10

-0.05

0.15+0.004

-0.002

0.006

8-SOP

KA3882C/KA3883C

9/10/02 0.0m 001

Stock#DSxxxxxxxx

” 2002 Fairchi ld Semiconductor Corporation

LIFE SU PP ORT POL ICY

FAIRCHILD’S PRODUCTS AR E NOT AUTHORIZED FOR USE AS C RITICAL COMPONENTS I N LIFE S UPPORT DEVICE S

OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR

CORPORA TION. As used he rein :

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, and (c) whose failure to

perform when properly used in accordance with

instructions for use provided in the labeling, can be

reasonably expected to result in a significant injury of the

user.

2. A critical component in any component of a life support

device or syst em who se failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effec tiv ene ss.

www.fairchildsemi.com

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRO DUCTS HEREIN TO IMPROVE RELIABILITY, FUN C TION OR DESIGN . FAIRCHILD DO ES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER

DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIG HTS, NOR THE RIGHTS OF OTHERS.

Ordering Information

Product Number Package Operating Temperature

KA3882C 8-DIP

0 ~ +70°C

KA3882CD 8-SOP

KA3883C 8-DIP

KA3883CD 8-SOP