LX
ENBAT
V33
V33BD
CL33
GND
GND
VREG
V5D
NFAULT
NPOR
V5A
VBB
CP2
CP1
VCP
VREG11
GND
GND
ENB
CPOR
CLADJ
VADJBD
FB
VIN
H.V.
A8450
VADJ
CIN
D2
D1
L1
C8
C7
C10
C9
C4 C2
C3
COUT
C1
R1
R2
R3
Q2
Q1
R4
Description
The A8450 is a multioutput power supply intended for
automotive applications. The A8450 operates from a wide
input supply range and is designed to satisfy the requirements
of high ambient temperature environments.
Four regulated voltage outputs provide multiple options. The
3.3 V regulator and the 1.2 to 3.3 V adjustable regulator can be
used to power microcontroller or DSP cores, or for I/O, sensing,
and A-to-D conversion. Two 5 V outputs, one digital and the
other analog, feature output tracking within 0.5% of each other
over the operating temperature range. In addition, the analog
regulator is protected against short-to-battery conditions. All
four regulators feature foldback current limit protection.
The device can be enabled or disabled using two input pins.
The high voltage input, on the ENBAT pin, allows enable/
disable using an engine ignition or battery switch signal. The
logic-level input, on the ENB pin, allows enable/disable by
microcontroller or DSP signals.
When disabled, the A8450 draws less than 10 A of current.
A POR (power-on-reset) block monitors the supply voltages
and provides a reset signal, with an adjustable delay, for
A8450-DS, Rev. 8
Features and Benefits
6 V to 45 V input range
DC-to-DC buck converter with 5.7 V output
Overcurrent protection with foldback, and undervoltage
lockout (UVLO)
Dual 5 V outputs
Digital 5 V ±2%, 200 mA
Analog 5 V, 200 mA
Short-to-supply protection on analog regulator
Analog to digital regulator output tracking < 0.5%
throughout operating temperature range
Automotive Multioutput Voltage Regulator
Continued on the next page…
Package: 24 pin SOIC (suffix LB)
Typical Application
Not to scale
A8450
Continued on the next page…
Automotive Multioutput Voltage Regulator
A8450
2
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Absolute Maximum Ratings
Part Number Pb-free Packing Terminals Package
A8450KLBTR-T Yes 1000 pieces per 13-in. reel 24 SOIC-W surface mount, internally
fused power ground pins (6-7, 18-19)
Parameter Symbol Conditions Rating Units
Load Supply Voltage VBB VBB pin – 40 V
Analog Output V5A V5A pin –1 to 45 V
Logic Input Signal VENBAT ENBAT pin input –0.3 to 45 V
VENB ENB pin input –0.3 to 6.5 V
LX Voltage VLX LX pin –2 to VBB V
Operating Temperature Range TAK range –40 to 135 °C
Junction Temperature TJ(max)150 °C
Storage Temperature Range Tstg –55 to 150 °C
Description (continued)
microcontroller or DSP resets. A separate fault pin signals TSD
(thermal shutdown), 5 V analog short-to-supply, and 5 V analog or
digital undervoltage.
The A8450 is supplied in a 24-pin SOIC-W package (part number
suffix LB) with internally-fused power ground pins for enhanced
thermal performance. This provides an RJA of 35°C/W on a 4-layer
board (see chart on p. 5). The lead (Pb) free version has 100% matte
tin leadframe plating.
3.3 V linear regulator, with foldback current limit
Adjustable 1.2 V to 3.3 V linear regulator, adjustable foldback
current limit
Ignition switch enable; Sleep mode
100% duty cycle operation for low input voltages
Power OK output
–40°C to 135°C ambient operating temperature range
Features and Benefits (continued)
Automotive Multioutput Voltage Regulator
A8450
3
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
Internal
Reference
Adjustable
Delay
VREG11
VBB LX
Soft Start
V5D
VREG
C8 C7 D1
L1
COUT
C1
ENB
VIN
CLADJ
VADJBD
FB
Q2
C4
VREG
CL33
V33BD
V33
Q1
C3
R3
R4
VADJ
R1
R2
V5A
C2
Short-to-Supply
Protection
5V Analog
Linear Regulator
and V5D to V5A
Tracking Control
5 V Digital Linear
Regulator
Current
Limiting
1.2 V to 3.3 V
Adjustable Linear
Regulator Control
3.3 V Linear
Regulator Control
CIN
D2
Buck Converter with
Switching Regulator
High
Voltage
Switch CP2CP1 VCP
Charge Pump
C10
ENBAT High V
Protection
VREG
VBB
VREF
VUVLOREG
VUVLOADJ
VUVLO33
NPOR
C9
CPOR
NFAULT
POR Block
Fault V5A Short to Supply
UVLO V5D, V5A
TSD Warning
GND
CPOK
ID Characteristics Representative Device
C1, C2, C3, C4 1 μF, 25 V ceramic X7R
COUT 100 μF, 35 V low-ESR electrolytic UHC1V101M, Nichicon
CIN 47 μF, 63 V electrolytic
C7, C8 0.1 μF, 50 V ceramic X7R (for 14 V applications), or
0.1 μF, 100 V ceramic X7R (for 42 V applications)
C10 0.22 μF, 10 V X7R
D1, D2 1 A, 40 V Schottky (for 14 V applications) EKO4, Sanken
L1 100 μH, 1.2 A D03316HT, Coilcraft
Q1, Q2 pass transistors npn transistor, hFE > 50 MPSW06
Automotive Multioutput Voltage Regulator
A8450
4
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless otherwise noted
Continued on next page
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Supply Quiescent Current IBB
Enabled mode: VENBAT or VENB = HIGH,
IOUT = 0 mA: VBB = 14 V – 6 10 mA
Enabled mode: VENBAT or VENB = HIGH,
IOUT = 0 mA; VBB = 6 V –1015mA
Disabled mode: VENBAT and VENB = LOW – – 10 μA
Regulated Output Voltage VREG
ILOAD = 550 mA = ILOADV5D + ILOADV5A + ILOADV33
+ ILOADVADJ; VBB > 6.5 V 5.50 – 5.80 V
Dropout: 6 V ≤ VBB < 6.5 V 5.00 – 5.80 V
Buck Switch On-Resistance RDSON
TJ = 25°C – 415 500 mΩ
TJ = 135°C – 650 750 mΩ
Buck Switch Current Limit IDSLIM 1.0 1.2 2.2 A
DC-to-DC Fixed Off-Time tOFF VBB = 14 V – 4.75 – μs
Soft Start Time tSS VBB = 14 V 5 10 15 ms
Logic Inputs
ENBAT Logic Input Voltage VENBAT
HIGH input level 2.7 – 45 V
LOW input level –0.3 – 0.8 V
ENBAT Input Current IENBAT
HIGH input level, VENBAT = 45 V – – 300 μA
HIGH input level, VENBAT = 14 V – – 70 μA
LOW input level, VENBAT = 0.8 V –1 – 10 μA
ENB Logic Input Voltage VENB
HIGH input level 2.7 – 6.5 V
LOW input level –0.3 – 0.8 V
ENB Input Current IENB
HIGH input level, VENB ≥ 2.7 V – – 50 μA
LOW input level, VENB ≤ 0.8 V –1 – 10 μA
Linear Regulator Outputs*
V5D Output Voltage VOUTV5D 1 mA ≤ ILOADV5D ≤ 200 mA 4.9 5.0 5.1 V
V5A Output Voltage VOUTV5A 1 mA ≤ ILOADV5A ≤ 200 mA 4.9 5.0 5.1 V
V33 Output Voltage VOUTV33 3.234 3.300 3.366 V
V5A to V5D Tracking VTRACK
50 mA ≤ ILOADV5A, ILOADV5D ≤ 200mA;
VBB > 6.5 V –25 – 25 mV
V5D Current Limit IOUTV5DLIM 200 300 – mA
V5A Current Limit IOUTV5ALIM 200 300 – mA
Base Drive Output Current IBD 1 V ≤ VOUTVADJ, VOUTV33 ≤ 4 V 5.0 10.0 16.0 mA
Feedback Voltage VFB 1.16 1.20 1.24 V
Feedback Input Bias Current IFB –400 –100 100 nA
Automotive Multioutput Voltage Regulator
A8450
5
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Protection
NFAULT, NPOR Output Voltage VERRON
Fault asserted;
INFAULT, INPOR = 1 mA – – 400 mV
NFAULT, NPOR Leakage Current IERROFF VNFAULT, VNPOR = 5 V – – 1 μA
POR Delay tPOR C9 = 0.47 μF 65 100 135 ms
V33 Undervoltage Threshold VUVLOV33
V33 rising 2.80 2.95 3.10 V
V33 falling 2.75 2.90 3.05 V
V33 Hysteresis VHYSV33 –80–mV
V5A, V5D Undervoltage Threshold VUVLOV5
V5A, V5D rising 4.36 4.50 4.75 V
V5A, V5D falling 4.24 4.38 4.63 V
V5A, V5D Hysteresis VHYSV5 – 125 – mV
VADJ Undervoltage Threshold VUVLOVADJ
VFB rising 1.02 1.07 1.12 V
VFB falling 0.97 1.02 1.07 V
VADJ Hysteresis VHYSVADJ At FB pin – 70 – mV
VADJ, V33 Overcurrent Threshold VOC 175 200 225 mV
VREG Undervoltage Threshold VUVLOVREG 4.94 5.15 5.36 V
Thermal Warning Threshold TJTW TJ rising – 160 – °C
Thermal Shutdown Threshold TJTSD TJ rising – 175 – °C
Thermal Shutdown Hysteresis THYSTSD Recovery period = TJTSD – TJTW –15–°C
*Linear regulator output specifications are only valid when VREG is in regulation (VBB 6.5).
ELECTRICAL CHARACTERISTICS (continued) at TA = –40ºC to 135°C, VBB = 6 to 45 V, VENB = 5 V, unless
otherwise noted
Ambient Temperature (°C)
Power Dissipation, P
D
(W)
0.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
1.0
1.5
20 40 60 80 100 120 140 160
Power Dissipation Versus Ambient Temperature
4-Layer PCB*
(RθJA = 35 ºC/W)
*In still air; mounted on PCB based on JEDEC high-conductance standard PCB
(JESD51-7; High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages); data on other PCB types is provided on the Allegro Web site.
Automotive Multioutput Voltage Regulator
A8450
6
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VREG
VOUTV33
VOUTVADJ
VOUTVADJ
VENBAT
VENBAT
VENB
VENB
VNPOR
VNPOR
VNPOR
VBB
VREG
VOUTV33
VOUTV5A/V5D
VREG Monitor
VCP
VREG
VOUTV33
VOUTVADJ
VUVLOV33
tPOR
tPOR
tPOR
tPOR
VHYSV33
VUVLOV33
VBB > 6 V
VREG = 1.8 V
VUVLOVREG
VUVLOVADJ
VHYSVADJ
A B
POR event initiates
+7 V
Slope of VOUTV33 and VOUTVADJ from A to B determined by ILOAD and output capacitor (C3, C4).
ENBAT signals power-on
Charge pump ramping
Charge pump OK flag set
VUVLOV33 exceeded; VADJ enabled
VUVLO(33)
ENB signals power-off
V33 can sustain regulation with normal load by bulk capacitor (COUT) on VREG.
Slope of VREG (which controls VOUTV5A/V5D, VOUTV33, and VOUTVADJ) from A to B determined by ILOAD and COUT.
AB
tPOR
tSS
Timing Diagrams
Figure 1a. NPOR fault due to undervoltage lockout on the V33 or FB pins
Figure 1b. Power-off using VBB
Figure 1c. Power-on using ENBAT, followed by power-off using ENB
Automotive Multioutput Voltage Regulator
A8450
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Load Transients Diagrams
VIN = 12 V; ILOAD = 100 mA; TA = 25°C; ac-coupled; C1, C2, C3 and C4 = 1 μF
*For the adjustable regulator, the transient load response
is improved as the voltage is reduced. This is due to the
ability of the regulator to provide more base drive (VADJBD)
because of more available voltage. When the adjustable
regulator approaches 3.3 V, its transient load response is
equivalent to the response of the V33 regulator.
For all regulators, load transients can be improved by
increasing the output capacitance (C1, C2, C3, and C4).
In order to keep ESR down it is best to use ceramic type
capacitors. However, large values in ceramic type capacitors
are either not available or very expensive. If larger values are
needed, above 22 μF, electrolytic capacitors with low ESR
ratings can be used. Performance can be improved further
by adding a 1 μF ceramic in parallel with the electrolytic.
VOUT (50 mV / Div.)
t (50 μs/Div.)
Adjustable Regulator, at 1.8 V*
VOUT (50 mV / Div.)
t (50 μs/Div.)
V5D Regulator
VOUT (50 mV / Div.)
t (50 μs/Div.)
V5A Regulator
VOUT (50 mV / Div.)
t (50 μs/Div.)
3.3 V Regulator
ILOAD = 5 to 100 mA
ILOAD
t (0.2 μs/Div.)
10%
90%
tRISE
Automotive Multioutput Voltage Regulator
A8450
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Description
Buck Converter with Switching Regulator. A current-
mode, variable frequency buck DC-to-DC converter and switch-
ing regulator are integrated in the A8450, as shown in figure 2.
This feature allows the device to efficiently handle power over a
wide range of input supply levels. The DC-to-DC converter out-
puts 5.7 V typical, and has an overcurrent limit of 1.2 A typical.
The converter employs a soft-start feature. This ramps the con-
verter output voltage and limits the maximum demand on VREG
by controlling the inrush current required at power-on to charge
the external capacitor, COUT, and any DC load.
An internal charge pump provides gate drive for the
N-channel MOSFET buck switch. A 100% duty cycle is imple-
mented when using low VBB input voltages.
At VBB lower than 12 V, off-time, tOFF, is reduced, as shown in
figure 3. This reduction keeps the switching frequency, fPWM,
within a reasonable range and lowers the ripple current. Lowering
the ripple current at low VBB levels prevents degradation of linear
regulator headroom due to VREG ripple voltage.
5 V Linear Regulators. Two 5 V medium-power linear regulators
are provided. These low-dropout regulators feature foldback current
limiting for short-to-ground protection. When a direct short is applied
to the regulator output, either V5A or V5D, the current folds back
VBB LX
D1
L1
100 μH
COUT
100 μF
VREG
Switching
Regulator
Control
Clock
Counter
Soft Start
Ramp
Generation
Error
Bandgap
1.22 V
Clamp
tOFF
VCP
Compensation
1.2 A Limit IPEAK
IDEMAND
ENB
Buck Converter
Buck Switch
Figure 2. Buck converter with switching regulator
Figure 3. When VBB falls below 12 V, tOFF decreases
5.5
579111315
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
tOFF by VBB
VBB (V)
tOFF (μs)
4.75 μs
12 V
2.05 μs
11 V
0.58 μs
6.02 V
Automotive Multioutput Voltage Regulator
A8450
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
to 0 V at 50 mA, as shown in figure 4a. The voltage recovers to its
regulated output when the short is removed.
The V5A and V5D regulators track each other during power-on, and
when the device is enabled and ramped up out of disabled mode,
the regulators will start to track when VREG reaches approximately
1.8 V. These regulators are guaranteed to track to within 0.5% of
each other under normal operating conditions.
3.3 V and Adjustable Linear Regulators. Two additional
linear regulators, one that outputs at 3.3 V, and another that has a
1.2 V to 3.3 V adjustable output, can be implemented using external
npn pass transistors. The output voltage of the adjustable regulator,
VOUTVADJ (V), is set by the values of the output resistors, R1 and
R2 (). It can be calculated as
VOUTVADJ = VFB (1+R1 ⁄ R2)
where VFB (V) is the voltage on the feedback pin, FB.
Additional pins, CL33 and CLADJ, are provided for setting cur-
rent limits. These are used to protect the external pass transis-
tors from a short-to-ground condition. The current limit setting,
ICL (mA), is calculated using the formula
ICL = VOC ⁄ RRCL
where RCL () is the current-limiting resistor corresponding to
that regulator (R3 for the 3.3 V regulator, and R4 for the adjustable
regulator). When ICL is exceeded, the maximum load current through
that regulator is folded back to 40% of ICL ±10%, as shown in figure
4b. If current limiting is not needed, the CL33 and CLADJ pins
should be shorted to the VREG pin.
Disabled Mode. When the two input signal pins, ENBAT and
ENB, are pulled low, the A8450 enters disabled mode. This is a
sleep mode, in which all internal circuitry is disabled in order to
draw a minimal current from VBB. When either of these pins is
pulled high, the device is enabled. When emerging from disabled
mode, the buck converter switching regulator does not operate
until the charge pump has stabilized ( 300 s).
Enabled Mode. When one or both of the signal input pins,
ENBAT and ENB, are in the high state, the A8450 is enabled.
ENBAT is an edge-triggered enable (logic 1 2.7 V), which is
used to enable the A8450 in response to a high-voltage signal,
such as from an automobile ignition or battery switch. In this
capacity, ENBAT is used only as a momentary switch to wake up
the device. If there is no need for a high-voltage signal, ENBAT
can be pulled low continuously.
ENB is used to initiate the reset of the device. If ENBAT is pulled
6
0 50 100 150 200 250 300 1600
5
4
3
2
1
0
5V Regulators Overcurrent Foldback
IOUT (mA)
VOUT (V)
IOUTV5DLIM and IOUTV5ALIM
Figure 4a. Linear foldback to 50 mA. Foldback occurs at the typical
current limit for the 5 V regulator. Figure 4b. Linear foldback to a percentage of ICL . Foldback occurs at
the current limit setting for the regulator.
6
0
ICL
1600
5
4
3
2
1
0
3.3 V and Adjustable Regulators Overcurrent Foldback
IOUT (mA)
VOUT (V)
0.4 ICL ±10%
VOUTVADJ(min)
VOUTV33 and VOUTVADJ(max)
Automotive Multioutput Voltage Regulator
A8450
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
low, ENB acts as a single reset control.
Diagnostics. An open drain output, through the NFAULT pin, is
pulled low to signal to a DSP or microcontroller any of the follow-
ing fault conditions:
• V5A, the 5 V analog regulator output, is shorted to supply
• Either or both of the V5A and the V5D regulator outputs are
below their UVLO threshold, VUVLOV5
• Device junction temperature, TJ, exceeds the Thermal Warning
threshold, TJTW
Charge Pump. The charge pump generates a voltage above VBB in
order to provide adequate gate drive for the N-channel buck switch.
A 0.1 F ceramic monolithic capacitor, C7, should be connected
between the VCP pin and the VBB pin, to act as a reservoir to run
the buck converter switching regulator.
VCP
is internally monitored to ensure that the charge pump is disabled
in the case of a fault condition. In addition, a 0.1 F ceramic mono-
lithic capacitor, C8, should be connected between CP1 and CP2.
Power On Reset Delay. The POR block monitors the supply
voltages and provides a signal that can be used to reset a DSP or
microcontroller. A POR event is triggered by any of the following
conditions:
• Either V33 or VADJ is pulled below its UVLO threshold,
VUVLOV33 or VUVLOVADJ. This occurs if the current limit on either
regulator, VOC , is exceeded. It also occurs if the VREG voltage
falls below VREGMON, due to current exceeding IDSLIM.
• Both input signal pins, ENB and ENBAT, are pulled low.
This immediately pulls the NPOR pin low, indicating that the
device is beginning a power-off sequence. In addition, the buck
converter switching regulator is disabled, and the VREG supply
begins to ramp down. The rate at which VREG decays is depen-
dent on the total current draw, ILOAD, and value of the output
capacitors (C1, C2, C3, and C4).
• VREG drops below its UVLO threshold, VUVLOVREG.
• During any normal power-on, VOUTVADJ falls below
VUVLOVADJ, triggering a POR.
An open drain output, through the NPOR pin, is provided to signal a
POR event to the DSP or microcontroller. The reset occurs after an
adjustable delay, tPOR, set by an external capacitor, C9, connected
to the CPOR pin. The value of tPOR (ms) is calculated using the
following formula
tPOR = 2.13×105
×
CCPOR
where CCPOR (F) is the value of the C9 capacitor.
A POR can be forced without a significant drop in the supply volt-
age, VREG, by pulsing low both the ENB and the ENBAT pins.
However, pulse duration should be short enough so that VREG does
not drop significantly.
Thermal Shutdown. When the device junction temperature, TJ,
is sensed to be at TJTSD (15°C higher than the thermal warning
temperature, TJTW), a fault is indicated at the NFAULT pin. At the
same time, a thermal shutdown circuit disables the buck converter,
protecting the A8450 from damage.
Automotive Multioutput Voltage Regulator
A8450
11
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Component Selection
Output Inductor (L1). This inductor must be rated to handle the
total load current, ILOAD. In addition, the value chosen must keep
the ripple current to a reasonable level. A typical selection is a
power inductor rated at 100 H and 1.3 A.
The worse case ripple current, IRIPPLE(max) (mA), can be calcu-
lated as
IRIPPLE(max) = VL1OFF
×
tOFF ⁄ LL1
where LL1 (H) is the inductance for the selected component, and
VL1OFF is the voltage (V) through the inductor when the A8450 is
in the quiescent state
VL1OFF = VREG(max) + VD1 + (ILOAD
×
RL1)
where VD1 (V) is the voltage drop on diode D1, ILOAD (mA) is
the total load current, and RL1 is the specified DC resistence ()
for the selected inductor at its rated temperature.
The frequency, fPWM (Hz), of the switching regulator in the buck
converter can then be estimated by
fPWM = 1/(tON + tOFF)
where tON (s) is calculated as
tON = IRIPPLE(max)
×
LL1 ⁄ VL1ON
and VL1ON (V) as
V
L1ON = VBB – (ILOAD
×
RDSON(max))
– (ILOAD
×
RL1) – VREG(max)
Example
Given a typical application with VBB = 14 V, tOFF = 4.75 s, and
ILOAD = 550 mA. (Note that the value for tOFF is constant for VBB
> 12 V, as shown in figure 3.)
Given also a 100 H power inductor rated at 400 m for 125ºC.
(Note that temperature ratings for inductors may include self-
heating effects. If a 125ºC rating includes a self-heating tempera-
ture rise of 20ºC at maximum current, then the actual ambient
temperature, TA, cannot exceed 105ºC.)
VL1OFF = 5.8 + 0.8 + (0.550
×
0.400) = 6.821 V
IRIPPLE(max) = 6.821
×
4.75 ⁄ 100 = 0.324 A
VL1ON = 14 – (0.550
×
0.750) – (0.550
×
0.400)
– 5.8 = 7.56 V
tON = 0.324
×
100 ⁄ 7.56 = 4.3 s
fPWM = 1/(4.3 + 4.75) = 111 kHz
In the case of a shorted output, the buck converter could reach
its internal current limit, IDSLIM
, of 1.2 A typical. To ensure safe
operation, the ISAT rating for the selected inductor should be
greater than 1.4 A. However, if the external current limit resistors,
R3 and R4, selected for the 3.3 V and adjustable (1.2 V to 3.3 V)
regulators, are rated such that the total inductor current, ILOAD,
could never reach that internal current limit, then an inductor can
be selected that has an ISAT rating closer to the calculated output
current of the device, ILOAD, plus the maximum ripple current,
IRIPPLE(max).
Higher inductor values can be chosen to lower IRIPPLE. This may
be an option if it is desired to increase the total maximum current
that is drawn from the switching regulator. The maximum total
current available, ILOAD (mA), is calculated as
ILOAD = IDSLIM – (IRIPPLE(max) ⁄ 2)
Catch Diode (D1). The Schottky catch diode should be rated to
handle 1.2 times the maximum load current, ILOAD, because the
duty cycle at low input voltages, VBB, can be very close to 100%.
The voltage rating should be higher than the maximum input
voltage, VBB(max), expected during any operating condition.
VREG Output Capacitor (COUT). Voltage ripple in the
VREG output is the main consideration when selecting the
VREG output capacitor, COUT. The peak-to-peak output voltage
ripple, VRIPPLE(p-p) (mV), is calculated as
VRIPPLE(p-p) = IRIPPLE
×
ESRCOUT
with ESR in ohms. It is recommended that the maximum level of
VRIPPLE(p-p) be less than 200 mV.
For electrolytic output capacitors, a low-ESR type is recom-
Application Information
Automotive Multioutput Voltage Regulator
A8450
12
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
mended, with a minimum voltage rating of 10 V. However,
because ESR decreases with voltage, the most cost-effective
choice may be a capacitor with a higher voltage rating.
Regulator Output Capacitors (C3 and C4). The output
capacitors used with the 3.3 V regulator (C3) and the 1.2 V to 3.3
V adjustable regulator (C4), should be 1 F or greater X7R (5%
tolerance) ceramic or equivalent capacitors, with a maximum
capacitance change of ±15% over a temperature range of –55ºC
to 125ºC.
The ESR of these capacitors does not affect the outputs of the
corresponding regulators. If a greater capacitance is used, the
regulators have improved ripple rejection at frequencies greater
than 100 kHz.
Pass Transistors (Q1 and Q2). The pass transistors used to
implement the 3.3 V regulator and the 1.2 V to 3.3 V adjustable
regulator must ensure the following:
• Stable operation. The cutoff frequency for the control loops of
the regulators is 100 kHz. Transistors must be selected that have
gain bandwidth product, fT (kHz), and beta, hFE (A), ratings
such that
fT ⁄ hFE > 100 kHz
• Adequate base drive. It is acceptable to use a lower level of
current gain, hFE, for lower total load currents, ILOAD. The lower
limit for ILOAD is limited by the minimum base current for the
A8450, IBD(min), and the minimum hFE of the pass transistor,
such that
ILOAD = IBD(min)
×
hFE(min)
Note that hFE is dependant on operating temperature. Lower
temperatures decrease hFE, affecting the current capacity of the
transistor.
• Packaged for sufficient power dissipation. In order to ensure
appropriate thermal handling, the design of the application must
take into consideration the thermal characteristics of the PCB
where the A8450 and pass transistors are mounted, the ambient
temperature, and the power dissipation characteristics of the
transistor packages. In general, the power dissipation, PD (mW),
is estimated by
PD = (VREG – VOUT)
×
ILOAD
For a typical application where VREG = 5.8 V, VOUT = 2.5 V,
and ILOAD = 190 mA
PD = (5.8 – 2.5)
×
190 = 627 mW
Adjusting Pass Transistor Power Dissipation
Transistors are manufactured in a wide variety of package types,
and the thermal dissipation efficiencies of the packages can vary
greatly. In general, increasing thermal efficiency can also increase
cost substantially. Selecting the package to closely match operat-
ing conditions is important to optimizing application design and
cost.
Even when using a thermally-enhanced package, it remains dif-
ficult to provide high current to a load at high ambient operating
temperatures. Depending on the load requirements, using drop
resistors, as shown in figure 5, may be necessary to protect the
pass transistor from overheating.
The output current-limiting resistors, RCL (corresponding to R3
and R4), will drop between 175 mV and 225 mV at the highest
current output, ILOAD. Assuming no additional resistance, the
voltage dropped, VDROP (mV), on each pass transistor is
VDROP = VREG – VRCL – VOUT
This can be substituted into the power dissipation formula
PD = VDROP
×
ILOAD
Given a typical application where VREG = 5.8 V, VRCL = 0.175 V,
VOUT = 3.3 V, and ILOAD = 350 mA, then PD is approximately
814 mW.
Figure 5. Placement of drop resistors for thermal protection; example
shown is for the 3.3 V regulator.
VREG
CL33
V33BD
V33
VCE
RCL
VOUTV33
ILOAD
A8450
VDROP
Automotive Multioutput Voltage Regulator
A8450
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PD can be used to estimate the minimum required operating
temperature rating for the transistor. The ability of a package to
dissipate heat is approximated by the thermal resistance from
the die (junction) to the ambient environment, RJA (°C/W). This
includes the significant effect of dissipation through the package
leads and the PCB on which the transistor is mounted, and the
state of the ambient air. The typical rating for a DPAK package is
32˚C/W. The expected self-induced temperature rise in the pack-
age, TJ (°C), given PD = 0.814 W, is approximated as
∆TJ = PD
×
RJA= 26°C
In automotive applications, where under-the-hood ambient tem-
peratures can exceed 125˚C, the pass transistor would have to be
rated to provide the required beta at 151°C, plus a safe operat-
ing margin.
For a selected transistor, VCE can change depending on current,
temperature, and transistor beta. Typically, transistors are rated
at a minimum beta at a defined VCE. However, VCE should be
calculated with some margin so there is always enough headroom
to drive the device at the desired load.
To provide an operating margin, or if a lower-value RCL is
required, voltage drop resistors, RDROP, can be added to the
circuit, between the RCL and the transistor (figure 5). It is also
important to consider tolerances in resistance values and VREG.
The level of VREG(min) is 5.6 V, at which level PD is reduced, but
also the voltage available for VCE is reduced. Calculating maxi-
mum and minimum voltage drops is useful in determining the
values of the drop resistors.
The required drop resistor value, RRDROP
, can be determined in
terms of the voltage drops across each component of the circuit,
as shown in the following formula
VDROP VOUT
where
VDROP = VREG – VRCL – VRDROP – VCE
Assume that VREG(max) = 5.8 V and VOUT(max) = 3.3 V. Assume
also that TA = 125°C, and VCE = 1V (as specified for the
MPSW06 npn transistor, beta = 300 at 125˚C).
In order to determine the resistance values for the current-limiting
and drop resistors, VRCL and VDROP can be expressed in terms of
ILOAD(lim)
VRCL = (ILOAD(lim)
×
RCL)
VRDROP = (ILOAD(lim)
×
RRDROP)
Assume a typical ILOAD = 350 mA. However, under normal oper-
ating conditions, the current limit set by RCL would be higher
than the expected normal current, so assume ILOAD(lim) = 0.400 A
and RCL = 44 . Substituting to determine VRCL
VRCL = 0.400
×
0.44 = 0.176 V
We can now solve for RRDROP and then VDROP
VREG – VRCL – (ILOAD×
RRDROP) – VCE VOUT
5.8 – 0.176 – (0.4
×
RRDROP) – 1 3.30 V
therefore
RRDROP 3.31
and
VRDROP = 0.4
×
3.31 = 1.3 V
Using four 0.25 W resistors valued at 14.7 in parallel will drop
1.3 volts.
Using the drop resistors as calculated above, the power dissipa-
tion in the transistor, PD (W) is reduced to
PD = ILOAD(lim)
×
(VREG – VRCL – VRDROP – VOUT)
= 0.400×
(5.8 – 0.176 – 1.3 – 3.3) = 0.410 W
and
∆TJ = PD
×
RJA= 13°C
The power dissipated in the transistor is significantly reduced. A
transistor in a power package with an RJA of 32˚C/W at 400 mA
(a 50 mA margin) undergoes a temperature rise of 13˚C with the
drop resistors, as opposed to a similar transistor at 350 mA rising
26˚C without drop resistors. At high output currents, properly
selected drop resistors can protect the external pass transitor from
overheating.
A8450 Power Dissipation. The A8450 is designed to operate
in applications with high ambient temperatures. The total power
dissipated in the device must be considered in conjunction with
the thermal dissipation capabilities of the PCB where the A8450
is mounted, as well as the capabilities of the device package
itself.
The ability of a package to dissipate heat is approximated by
the thermal resistance from the die (junction) to the ambient
environment, RJA (°C/W). This includes the significant effect
of dissipation through the package leads and the PCB on which
the package is mounted, and the temperature of the ambient air.
Automotive Multioutput Voltage Regulator
A8450
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Test results for this 24-lead SOIC are approximately 35 °C/W
when mounted on a high-thermally conductive PCB (based on
the JEDEC standard PCB, having four layers with buried copper
areas).
The total power that can be applied to the device, PD(lim) (W), is
affected by the maximum allowable device junction temperature,
TJ(max) (°C), RJA , and the ambient air temperature, TA (°C), as
shown in the following formula
PD(lim) = (TJ(max) – TA) ⁄ RJA
PD(lim) can be estimated based on several parameters, using the
following formula
P
D(lim) = PD(Ibias) + PD(V5A) + PD(V5D) + PD(buckdc)
+ PD(buckac) + PD(BD)
where
P
D(Ibias) = VBB
×
IBB
P
D(V5A) = (VREG – 5 V)
×
ILOAD(V5A)
P
D(V5D) = (VREG – 5 V)
×
ILOAD(V5D)
P
D(buckdc)= ILOAD2
×
RDSON(TJmax)
×
DC
P
D(buckac)= ILOAD
×
[VBB(
5 ns ⁄ 14 V)
×
VBB]
×0.5
fPWM
P
D(BD) = IV33BD(max)
×
(VREG – 4 V) + IVADJBD(max)
×
(VREG
– VADJ – 0.7 V)
and
I
LOAD = ILOAD(V33) + ILOAD(VADJ) + ILOAD(V5D) + ILOAD(V5A)
RDSON is a function of TJ. For the purposes of estimating PD(lim),
the relationship can be assumed to be linear throughout the
practical TJ operating range (see test conditions for RDSON in the
Electrical Characteristics table).
DC (duty cycle) is a function of VBB and VREG. This can be
calculated precisely as
DC = VREG(off) ⁄ (VREG(on) + VREG(off)
)
A rough estimate for DC is
DC = (VREG + VLX) ⁄ VBB
IV33BD(max) is the maximum current drawn on the V33BD pin. It
is dependent on IOUTV33 and the hFE of the pass transistor.
IADJBD(max) is the maximum current drawn on the VADJBD pin.
It is dependent on IOUTVADJ and the hFE of the pass transistor.
Overcurrent Protection
The current supplied by the 3.3 V and the 1.2 to 3.3 V adjust-
able regulators is limited to ICL. Current above ICL is folded back
linearly, as shown in figure 4b. In the case of a shorted load,
the collector current is reduced to 40% of ICL ±10% , to ensure
protection of the pass transistors. After the short is removed, the
voltage recovers to its regulated level.
The maximum power dissipated in the transistor during a shorted
load condition is:
PD (VREG – VOUT)
×
(0.4
×
ICL)
where VOUT = 0 V.
Low Input Voltage Operation
When the charge pump has ramped enough to enhance the buck
switch, the buck converter switching regulator is enabled. This
occurs at VBB 5.7 V. At that point, the duty cycle, DC, of the
A8450 can be forced to 100% until VIN is high enough to allow
the switch to begin operating normally. The point at which nor-
mal switching begins is dependent on ambient temperature, TA.
Increases in TA cause RDSON to increase. Other significant factors
are ILOAD, VREG, the ESR of the output inductor (L1), and the
forward biasing voltage for the output Schottky diode (D1).
Regulator Bypass
Some applications may not require the use of all four regulators
provided in the A8450. For the regulators that are not used, the
corresponding external components are not needed.
If either or both of the two 5 V regulators are not required by the
application, bypass an unused regulator by not connecting its
output terminal, V5D or V5A. Also, the corresponding output
capacitor, C1 or C2, is not used.
For the 3.3 V regulator and the 1.2 V to 3.3 V adjustable regula-
tor, if either or both are not needed, the corresponding external
components are not used. In addition, if the 3.3 V regulator is not
used, CL33 and V33 are not connected. If the adjustable regula-
tor is not used, CLADJ and FB are not connected. However, to
ensure stability of the A8450, the base drive pin, V33BD or VAD-
JBD, of any unused regulator must be shorted to VREG.
Automotive Multioutput Voltage Regulator
A8450
15
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Terminal List Table
Name Description Number
VBB Supply input 1
CP2 Charge pump capacitor, positive side 2
CP1 Charge pump capacitor, negative side 3
VCP Charge pump output used to drive N-channel buck converter
transistor 4
VREG11 Internal reference 5
GND Power ground 6
GND Power ground 7
ENB Logic control 8
CPOR Connection for POR adjustment 9
CLADJ Current limit for adjustable regulator 10
VADJBD Base drive for adjustable regulator pass transistor 11
FB Feedback for adjustable regulator 12
V5A 5 V analog regulator output 13
NPOR Power on Reset logic output 14
NFAULT Diagnostic output; open drain; low during fault condition 15
V5D 5 V digital regulator output 16
VREG DC-to-DC converter supply output 17
GND Power ground 18
GND Power ground 19
CL33 Current limit for 3.3 V regulator 20
V33BD Base drive for 3.3 V regulator pass transistor 21
V33 3.3 V regulator output 22
ENBAT High voltage logic control 23
LX Buck converter switching regulator output 24
Pin-Out Diagram
3
4
5
6
7
8
2
1
22
21
20
19
18
17
23
24
10
9
11
15
14
13
16
12
VBB
CP2
CP1
VCP
VREG11
GND
GND
ENB
LX
ENBAT
V33
V33BD
CL33
GND
GND
VREG
CPOR
CLADJ
VADJBD
FB
V5D
NFAULT
NPOR
V5A
1.2 V to
3.3 V
Lin Reg
Control
5 V
Dig/Anlg
Lin Reg
5 V Reg
Track
Control
3.3 V
Lin Reg
Control
Charge
Pump
Buck
Converter
Soft
Start
Automotive Multioutput Voltage Regulator
A8450
16
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LB, 24-Pin SOICW
Leads 6 and 7, and 18 and 19 are internally fused ground leads, for enhanced
thermal dissipation.
1.27
0.25
BReference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
0.20 ±0.10
0.41 ±0.10
2.20
0.65
9.60
1.27
21
24
A
15.40±0.20
2.65 MAX
10.30±0.33
7.50±0.10
C
SEATING
PLANE
C0.10
24X
For reference only
Pins 6 and 7, and 18 and 19 internally fused
Dimensions in millimeters
(Reference JEDEC MS-013 AD)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
GAUGE PLANE
SEATING PLANE PCB Layout Reference View
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
21
24
Automotive Multioutput Voltage Regulator
A8450
17
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2004-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Revision History
Revision Revision Date Description of Revision
Rev. 8 January 30, 2012 Update product availability
