IS41LV82052-60JI - Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774 1

Rev. A

12/19/00

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

IS41C82052

IS41LV82052 ISSI®

FEATURES

• Fast Page Mode Access Cycle

• TTL compatible inputs and outputs

• Refresh Interval:

-- 2,048 cycles/32 ms

• Refresh Mode: RAS-Only,

CAS-before-RAS (CBR), and Hidden

• Single power supply:

5V±10% or 3.3V ± 10%

• Byte Write and Byte Read operation via two CAS

• Industrial temperature range -40°C to 85°C

DESCRIPTION

The

ISSI

IS41C82052 and IS41LV82052 are 2,097,152 x 8-bit

high-performance CMOS Dynamic Random Access

Memory. The Fast Page Mode allows 2,048 random

accesses within a single row with access cycle time as

short as 20 ns per 4-bit word.

These features make the IS41C82052 and IS41LV82052

ideally suited for high-bandwidth graphics, digital signal

processing, high-performance computing systems, and

peripheral applications.

The IS41C82052 and IS41LV82052 are packaged in 28-pin

300-mil SOJ and 28-pin TSOP (Type II) with JEDEC

standard pinouts.

2M x 8 (16-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE NOVEMBER 2000

KEY TIMING PARAMETERS

Parameter -50 -60 Unit

RAS Access Time (tRAC)5060ns

CAS Access Time (tCAC)1315ns

Column Address Access Time (tAA)

25 30 ns

Fast Page Mode Cycle Time (tPC)

20 25 ns

Read/Write Cycle Time (tRC) 84 104 ns

PRODUCT SERIES OVERVIEW

Part No. Refresh Voltage

IS41C82052 2K 5V ± 10%

IS41LV82052 2K 3.3V ± 10%

VCC

I/O0

I/O1

I/O2

I/O3

RAS

A10

VCC

GND

I/O7

I/O6

I/O5

I/O4

CAS

GND

PIN DESCRIPTIONS

A0-A10 Address Inputs

I/O0-7 Data Inputs/Outputs

WE Write Enable

OE Output Enable

RAS Row Address Strobe

CAS Column Address Strobe

Vcc Power

GND Ground

NC No Connection

PIN CONFIGURATION

28 Pin SOJ, TSOP (Type II)

2Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

FUNCTIONAL BLOCK DIAGRAM

CAS CAS WE

DATA I/O BUS

COLUMN DECODER

SENSE AMPLIFIERS

MEMORY ARRAY

2,097,152 x 8

ROW DECODER

DATA I/O BUFFERS

CAS

CONTROL

LOGIC

CONTROL

LOGIC

CONTROL

LOGIC

I/O0-I/O7

RAS

A0-A10

RAS

CLOCK

GENERATOR

REFRESH

COUNTER

ADDRESS

BUFFERS

TRUTH TABLE

Function RAS CAS WE OE Address tR/tCI/O

Standby H H X X X High-Z

Read L L H L ROW/COL DOUT

Write: Word (Early Write) L L L X ROW/COL DIN

Read-Write L L H→LL→H ROW/COL DOUT, DIN

Hidden Refresh Read L→H→L L H L ROW/COL DOUT

Write(1) L→H→L L L X ROW/COL DOUT

RAS-Only Refresh L H X X ROW/NA High-Z

CBR Refresh H→L L X X X High-Z

Note:

1. EARLY WRITE only.

Integrated Silicon Solution, Inc. — 1-800-379-4774 3

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

Functional Description

The IS41C82052 and IS41LV82052 are CMOS DRAMs

optimized for

high-speed bandwidth, low power applications.

During READ or WRITE cycles, each bit is uniquely

addressed through the 11 address bits. These are entered

11 bits (A0-A10) at a time. The row address is latched by

the Row Address Strobe (RAS). The column address is

latched by the Column Address Strobe (CAS). RAS is

used to latch the first nine bits and CAS is used the latter

ten bits.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum tRAS time has expired. A new

cycle must not be initiated until the minimum precharge

time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time specified

by tAR. Data Out becomes valid only when tRAC, tAA, tCAC

and tOEA are all satisfied. As a result, the access time is

dependent on the timing relationships between these

parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and

WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever

occurs last.

Auto Refresh Cycle

To retain data, 2,048 refresh cycles are required in each

32 ms period. There are two ways to refresh the memory:

1. By clocking each of the 2,048 row addresses (A0

through A10) with RAS at least once every 32 ms. Any

read, write,

read-modify-write

o r

RAS-only

cycle refreshes

the addressed row.

2. Using a

CAS-before-RAS

refresh cycle.

CAS-before-RAS

refresh is activated by the falling edge of RAS, while

holding CAS LOW. In CAS-before-RAS refresh cycle,

an internal 9-bit counter provides the row addresses

and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Power-On

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight

initialization cycles (any combination of cycles contain-

ing a RAS signal).

During power-on, it is recommended that RAS track with

VCC or be held at a valid VIH to avoid current surges.

4Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameters Rating Unit

VTVoltage on Any Pin Relative to GND 5V –1.0 to +7.0 V

3.3V –0.5 to +4.6

VCC Supply Voltage 5V –1.0 to +7.0 V

3.3V –0.5 to +4.6

IOUT Output Current 50 mA

PDPower Dissipation 1 W

TACommercial Operation Temperature 0 to +70 °C

Industrial Operation Temperature -40 to +85

TSTG Storage Temperature –55 to +125 °C

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 5V 4.5 5.0 5.5 V

3.3V 3.0 3.3 3.6

VIH Input High Voltage 5V 2.4 — VCC + 1.0 V

3.3V 2.0 — VCC + 0.3

VIL Input Low Voltage 5V –1.0 — 0.8 V

3.3V –0.3 — 0.8

TACommercial Ambient Temperature 0 — 70 °C

Industrial Ambient Temperature -40 — 85 °C

CAPACITANCE(1,2)

Symbol Parameter Max. Unit

CIN1Input Capacitance: A0-A10(A11) 5 pF

CIN2Input Capacitance: RAS, CAS, WE, OE 7pF

CIO Data Input/Output Capacitance: I/O0-I/O3 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25°C, f = 1 MHz.

Integrated Silicon Solution, Inc. — 1-800-379-4774 5

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter Test Condition VCC Speed Min. Max. Unit

IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –5 5 µA

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) –5 5 µA

0V ≤ VOUT ≤ Vcc

VOH

Output High Voltage Level

IOH = –5.0 mA, Vcc = 5V 2.4 — V

IOH = –2.0 mA, Vcc = 3.3V

VOL

Output Low Voltage Level

IOL = 4.2 mA, Vcc = 5V — 0.4 V

IOL = 2 mA, Vcc = 3.3V

ICC1Standby Current: TTL RAS, CAS ≥ VIH

Commercial

5V 2 mA

3.3V — 0.5

Industrial

5V — 3

3.3V — 2

ICC2Standby Current: CMOS RAS, CAS ≥ VCC – 0.2V 5V — 1 mA

3.3V — 0.5

ICC3Operating Current: RAS, CAS, -50 — 120 mA

Random Read/Write(2,3)

Address Cycling, tRC = tRC (min.)

-60 — 110

Average Power Supply Current

ICC4Operating Current: RAS= VIL, CAS ≥ VIH -50 — 90 mA

Fast Page Mode(2,3,4) tRC = tRC (min.) -60 — 80

Average Power Supply Current

ICC5Refresh Current: RAS Cycling, CAS ≥ VIH -50 — 120 mA

RAS-Only(2,3) tRC = tRC (min.) -60 — 110

Average Power Supply Current

ICC6Refresh Current: RAS, CAS Cycling -50 — 120 mA

CBR(2,3,5) tRC = tRC (min.) -60 — 110

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each Fast Page cycle.

5. Enables on-chip refresh and address counters.

6Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

AC CHARACTERISTICS(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50 -60

Symbol Parameter Min. Max. Min. Max. Units

tRC Random READ or WRITE Cycle Time 84 — 104 — ns

tRAC Access Time from RAS(6, 7) —50 —60 ns

tCAC Access Time from CAS(6, 8, 15) —13 —15 ns

tAA Access Time from Column-Address(6) —25 —30 ns

tRAS RAS Pulse Width 50 10K 60 10K ns

tRP RAS Precharge Time 30 — 40 — ns

tCAS CAS Pulse Width(23) 8 10K 10 10K ns

tCP CAS Precharge Time(9) 9— 9— ns

tCSH CAS Hold Time (21) 38 — 40 — ns

tRCD RAS to CAS Delay Time(10, 20) 12 37 14 45 ns

tASR Row-Address Setup Time 0 — 0 — ns

tRAH Row-Address Hold Time 8 — 10 — ns

tASC Column-Address Setup Time(20) 0— 0— ns

tCAH Column-Address Hold Time(20) 8— 10— ns

tAR Column-Address Hold Time 30 — 40 — ns

(referenced to RAS)

tRAD RAS to Column-Address Delay Time(11) 10 25 12 30 ns

tRAL Column-Address to RAS Lead Time 25 — 30 — ns

tRPC RAS to CAS Precharge Time 5 — 5 — ns

tRSH RAS Hold Time 8 — 10 — ns

tRHCP RAS Hold Time from CAS Precharge 30 — 35 — ns

tCLZ CAS to Output in Low-Z(15, 24) 0— 0— ns

tCRP CAS to RAS Precharge Time(21) 5— 5— ns

tOD Output Disable Time(19, 24) 315 315 ns

tOE Output Enable Time(15, 16) —12 —15 ns

tOED Output Enable Data Delay (Write) 12 — 15 — ns

tOEHC OE HIGH Hold Time from CAS HIGH 5 — 5 — ns

tOEP OE HIGH Pulse Width 10 — 10 — ns

tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns

tRCS Read Command Setup Time(17, 20) 0— 0— ns

tRRH Read Command Hold Time 0 — 0 — ns

(referenced to RAS)(12)

tRCH Read Command Hold Time 0 — 0 — ns

(referenced to CAS)(12, 17, 21)

tWCH Write Command Hold Time(17) 8— 10— ns

tWCR Write Command Hold Time 40 — 50 — ns

(referenced to RAS)(17)

tWP Write Command Pulse Width(17) 8— 10— ns

tWPZ WE Pulse Widths to Disable Outputs 7 — 7 — ns

Integrated Silicon Solution, Inc. — 1-800-379-4774 7

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50 -60

Symbol Parameter Min. Max. Min. Max. Units

tRWL Write Command to RAS Lead Time(17) 13 — 15 — ns

tCWL Write Command to CAS Lead Time(17, 21) 8— 10— ns

tWCS Write Command Setup Time(14, 17, 20) 0— 0— ns

tDHR Data-in Hold Time (referenced to RAS)39— 39— ns

tACH Column-Address Setup Time to CAS 15 — 15 — ns

Precharge during WRITE Cycle

tOEH OE Hold Time from WE during 8 — 10 — ns

READ-MODIFY-WRITE cycle(18)

tDS Data-In Setup Time(15, 22) 0— 0— ns

tDH Data-In Hold Time(15, 22) 8— 10— ns

tRWC READ-MODIFY-WRITE Cycle Time 108 — 133 — ns

tRWD RAS to WE Delay Time during 64 — 77 — ns

READ-MODIFY-WRITE Cycle(14)

tCWD CAS to WE Delay Time(14, 20) 26 — 32 — ns

tAWD Column-Address to WE Delay Time(14) 39 — 47 — ns

tPC Fast Page Mode READ or WRITE 20 — 25 — ns

Cycle Time

tRASP RAS Pulse Width 50 100K 60 100K ns

tCPA Access Time from CAS Precharge(15) —30 —35 ns

tPRWC READ-WRITE Cycle Time(24) 56 — 68 — ns

tCOH Data Output Hold after CAS LOW 5— 5— ns

tOFF Output Buffer Turn-Off Delay from 0 12 0 15 ns

CAS or RAS(13,15,19, 24)

tWHZ Output Disable Delay from WE 310 310 ns

tCSR CAS Setup Time (CBR REFRESH)(20, 25) 5— 5— ns

tCHR CAS Hold Time (CBR REFRESH)( 21, 25) 8— 10— ns

tORD OE Setup Time prior to RAS during 0 — 0 — ns

HIDDEN REFRESH Cycle

tREF Auto Refresh Period 2,048 Cycles — 32 — 32 ms

tTTransition Time (Rise or Fall)(2, 3) 150 150 ns

AC TEST CONDITIONS

Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)

One TTL Load and 50 pF (Vcc = 3.3V ±10%)

Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%);

VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%)

Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)

8Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and

VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

4. If CAS and RAS = VIH, data output is High-Z.

5. If CAS = VIL, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.

7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the

amount that tRCD exceeds the value shown.

8. Assumes that tRCD • tRCD (MAX).

9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data

output buffer, CAS and RAS must be pulsed for tCP.

10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is

greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.

11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is

greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.

12. Either tRCH or tRRH must be satisfied for a READ cycle.

13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.

14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS

(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • tRWD (MIN),

tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected

cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is

indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.

15. Output parameter (I/O) is referenced to corresponding CAS input.

16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as WE going low.

18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and

OE is taken back to LOW after tOEH is met.

19. The I/Os are in open during READ cycles once tOD or tOFF occur.

20. Determined by falling edge of CAS.

21. Determined by rising edge of CAS.

22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or

READ-MODIFY-WRITE cycles.

23. CAS must meet minimum pulse width.

24. The 3 ns minimum is a parameter guaranteed by design.

25. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. — 1-800-379-4774 9

Rev. A

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IS41C82052

IS41LV82052 ISSI

READ CYCLE

tRAS

tRC

tRP

tAR

tCAH

tASC

tRAD tRAL

I/O

ADDRESS

CAS

RAS

Row Column

Open Open

Valid Data

tCSH

tCAS

tRSH

tCRP tCLCH

tRCD

tRAHtASR

tRRH

tRCHtRCS

tAA

tCAC tOFF(1)

tRAC

tCLC

tOES

tOE tOD

Row

Don’t Care

Note:

1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.

10 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)

RAS

RWC

CAH

ASC

RAD

RAL

ACH

ADDRESS

CAS

RAS

Row Column

CSH

CAS

RSH

CRP

CLCH

RCD

RAH

ASR

RWD

CWL

CWD

RWL

AWD

RCS

CAC

CLZ

OEH

RAC

I/O Open Open

Valid D

OUT

Valid D

Row

Don’t Care

Integrated Silicon Solution, Inc. — 1-800-379-4774 11

Rev. A

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IS41C82052

IS41LV82052 ISSI

EARLY WRITE CYCLE (OE = DON'T CARE)

tRAS

tRC

tRP

tAR

tCAH

tASC

tRAD tRAL

tACH

I/O

ADDRESS

CAS

RAS

Row Column

tCSH

tCAS

tRSH

tCRP tCLCH

tRCD

tRAHtASR

tCWL

tWCR

tWCH

tRWL

tWP

tWCS

tDH

tDS

tDHR

Valid Data

Row

Don’t Care

12 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

FAST-PAGE-MODE READ CYCLE

OUT

I/O

ADDRESS

CAS

RAS

Row Column Column Column

CSH

CAS

RASP

RSH

PRWC

RCD

CRP

ASR

RAD

RCS

ASC

RAL

CAH

CAC

CLZ

RAC

CLZ

CAC

OUT

OED

CLZ

RAH

CPWD

CAH

CRP

Integrated Silicon Solution, Inc. — 1-800-379-4774 13

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

FAST-PAGE-MODE READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)

OUT

RWD

AWD

I/O

ADDRESS

CAS

RAS

Row Column Column Column

CSH

CAS

RASP

RSH

PRWC

RCD

CWD

CRP

ASR

RAD

RCS

ASC

RAL

CAH

AWD

CAC

CLZ

RAC

OEA

CLZ

CAC

OEA

CAC

OEA

OUT

OUT ININ IN

OEZ

OED

OEZ

OED

CLZ

RAH

CWL

RWL

CPWD

CAH

CRP

Don’t Care

14 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

FAST PAGE MODE EARLY WRITE CYCLE

tAR

I/O

ADDRESS

CAS

RAS

Row Column Column Column

tAR

tCWL

tWCR

tDHR

tCSH

tCAS tCAS tCAS

tRASP

tRSH

tRHCP

tPC

tRCD

tCRP

tASR

tWCS

tDS

tRAD

tASC tASC tASC

tRAL

tCAH

tWCH

tDH tDS tDS

tDH tDH

tCP tCP

tRP

tCAH

tRAH tCAH

tCRP

tCWL

tWCS tWCS

tWCH

tWP tWP

tCWL

tWCH

tWP

Valid DIN Valid DIN

Valid DIN

Don’t Care

Integrated Silicon Solution, Inc. — 1-800-379-4774 15

Rev. A

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IS41C82052

IS41LV82052 ISSI

RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)

RAS

I/O

ADDRESS

CAS

RAS

Row

Open

CRP

RAH

ASR

RPC

Row

Don’t Care

16 Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)

CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)

tRAS tRAStRP tRP

I/O

CAS

RAS

Open

tCP

tRPC

tCSR

tCHR tRPC

tCSR

tCHR

tRAS tRAS

tRP

CAS

RAS

tCRP tRCD tRSH tCHR

tAR

tASC

tRAD

ADDRESS Row Column

tRAHtASR

tRAL

tCAH

I/O Open Open

Valid Data

tAA

tCAC

tRAC

tCLZ

tOFF(2)

tOE

tORD

tOD

Don’t Care

Integrated Silicon Solution, Inc. — 1-800-379-4774 17

Rev. A

12/19/00

IS41C82052

IS41LV82052 ISSI

ORDERING INFORMATION

Industrial Range: -40°°

°°

°C to 85°C

Voltage: 5V

Speed (ns) Order Part No. Package

50 IS41C82052-50JI 300-mil SOJ

50 IS41C82052-50TI TSOP (Type II)

60 IS41C82052-60JI 300-mil SOJ

60 IS41C82052-60TI TSOP (Type II)

Voltage: 3.3V

Speed (ns) Order Part No. Package

50 IS41LV82052-50JI 300-mil SOJ

50 IS41LV82052-50TI TSOP (Type II)

60 IS41LV82052-60JI 300-mil SOJ

60 IS41LV82052-60TI TSOP (Type II)

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774

Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°°

°°

°C to 70°°

°°

°C

Voltage: 5V

Speed (ns) Order Part No. Package

50 IS41C82052-50J 300-mil SOJ

50 IS41C82052-50T TSOP (Type II)

60 IS41C82052-60J 300-mil SOJ

60 IS41C82052-60T TSOP (Type II)

Voltage: 3.3V

Speed (ns) Order Part No. Package

50 IS41LV82052-50J 300-mil SOJ

50 IS41LV82052-50T TSOP (Type II)

60 IS41LV82052-60J 300-mil SOJ

60 IS41LV82052-60T TSOP (Type II)