Rev.2.00, Feb.18.2005, page 1 of 10
HD74LS161A
Synchronous 4-bit Binary Counter (direct clear) REJ03D0445–0200
Rev.2.00
Feb.18.2005
This synchronous 4-bit bin ary counter features an internal carry look-ahead for application in high-speed counting
designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes
coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation
eliminates the output cou nting spikes that are normally associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This
counter is fully programmable; th at is, the output may be preset to either level. As presetting is synchronous, setting up
a low level at the load input disables th e counter and causes the outputs to agree with the setup data after the next clock
pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load inpu t should be avoided when the
clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low leve l
at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The
carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional getting.
Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable
inputs (P and T) must be high to coun t, and input T is fed forward to enable the ripple carry output. The ripple carry
output thus enabled will produced a high-level output pulse with a duration approximately equal to the high-level
portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages.
High-to-low-level transitions at the enable P or T inputs should occur only when the clock inpu t is high.
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS161AP DILP-16 pin PRDP0016AE-B
(DP-16FV) P —
HD74LS161AFPEL SOP-16 pin (JEITA) PRSP0016DH-B
(FP-16DAV) FP EL (2,000 pcs/reel)
HD74LS161ARPEL SOP-16 pin (JEDEC) PRSP0016DG-A
(FP-16DNV) RP EL (2,500 pcs/reel)
Note: Please consult the sales office for the above packa ge availability.
HD74LS161A
Rev.2.00, Feb.18.2005, page 2 of 10
Pin Arrangement
(Top view)
V
CC
GND
15
161
2
3
4
5
6
7
14
89
10
11
12
13
CLR
CK
PLoad
D
B
A
Ripple
Carry
T
Q
D
Q
B
Q
A
Clear
Clock
A
B
C
D
Enable P
Load
Enable T
Q
D
Q
C
Q
B
Q
A
Ripple
Carry Output
CQ
C
Outputs
Data
Inputs
Block Diagram
Output
Q
A
Output
Q
B
Output
Q
C
Output
Q
D
Ripple
Carry
Output
Enable
Data
Inputs
P
T
A
B
C
D
Clock
Clear
Load CK
CLR
Q
DQ
CK
CLR
Q
DQ
CK
CLR
Q
DQ
CK
CLR
Q
DQ
HD74LS161A
Rev.2.00, Feb.18.2005, page 3 of 10
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
Clock frequency ƒclock 0 — 25 MHz
Clock pulse width tw (clock) 25 — — ns
Clear pulse width tw (clear) 20 — — ns
A, B, C, D 20 — — ns
Enable P, T 20 — — ns
Setup time Load tsu 20 — — ns
Hold time th 3 — — ns
Typical Clear, Preset, and Inhibit Sequence
Count
Preset
(Load)
Inhibit
Load
Data
Inputs
A
B
C
D
QA
QD
QC
QB
Clock
Enable T
Carry
Enable P
Clear
Clear
Outputs
12 13 1514 012
HD74LS161A
Rev.2.00, Feb.18.2005, page 4 of 10
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
VOH 2.7 — — V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
— — 0.4 IOL = 4 mA
Output voltage VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
Data, Enable P — — 20
Load, Clock, Enable T — — 40
Clear IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V
Data, Enable P — — –0.4
Load, Clock, Enable T — — –0.8
Clear IIL — –0.4
mA VCC = 5.25 V, VI = 0.4 V
Data, Enable P — — 0.1
Load, Clock, Enable T — — 0.2
Input
current
Clear II — — 0.1
mA VCC = 5.25 V, VI = 7 V
Short-circuit output current IOS –20 — –100 mA VCC = 5.25 V
ICCH — 18 31 mA VCC = 5.25 V
Supply current** ICCL — 19 32 mA VCC = 5.25 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICCH is measured with the load input high, then again with the load input low, with all other inputs hi gh and all
outputs open. ICCL is measured with the clock input high, then again with the clock input low, with all other
inputs low and all outputs open.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Outputs min. typ. max. Unit Condition
Maximum clock frequency ƒmax Clock QA to QD 25 32 — MHz
tPLH — 20 35 ns
tPHL Clock Ripple
Carry — 18 35 ns
tPLH — 13 24 ns
tPHL Clock
(Load = “H”) QA to QD — 18 27 ns
tPLH — 13 24 ns
tPHL Clock
(Load = “L”) QA to QD — 18 27 ns
tPLH — 9 14 ns
tPHL Enable T Ripple
Carry — 9 14 ns
Propagation delay time
tPHL Clear QA to QD — 20 28 ns
CL = 15 pF,
RL = 2 kΩ
HD74LS161A
Rev.2.00, Feb.18.2005, page 5 of 10
Timing Method
Enable
P or T
Load
Clock
Data
Outputs
A to D
1.3V 1.3V
1.3V 1.3V
1.3V 1.3V
1.3V 1.3V
1.3V
t
su
t
w (CK)
t
h
t
su
t
h
t
su
t
h
0V
3V
0V
3V
0V
3V
0V
3V
Testing Method
Test Circuit
4.5V
Q
A
Load circuit 1
Q
A
V
CC
R
L
C
L
Input
P.G.
Z
out
= 50Ω
Input
P.G.
Z
out
= 50Ω
See Testing Table
A
B
C
D
CK
P
T
CLR
Load
Q
C
Q
D
Q
B
Same as Load Circuit 1.
Q
B
Same as Load Circuit 1.
Q
C
Same as Load Circuit 1.
Q
D
Ripple
Carry
Ripple
Carry
Same as Load Circuit 1.
Notes: 1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
HD74LS161A
Rev.2.00, Feb.18.2005, page 6 of 10
Testing Table
Inputs
Enable Data
Item From input to
output Clear Load P T
Clock A B C D
ƒmax 4.5V 4.5V 4.5V 4.5V IN GND GND GND GND
CK
→ Ripply
Carry 4.5V 4.5V 4.5V 4.5V IN GND GND GND GND
CK → Q 4.5V 4.5V 4.5V 4.5V IN GND GND GND GND
CK → Q 4.5V GND GND GND IN IN* IN* IN* IN*
Enable
T → Ripple
Carry 4.5V GND 4.5V IN IN* 4.5V 4.5V 4.5V 4.5V
tPLH
tPHL
CLR → Q IN GND GND GND IN* 4.5V 4.5V 4.5V 4.5V
Notes: *. For initialized
Outputs
Item From input to output QA Q
B Q
C Q
D Ripple Carry
ƒmax OUT OUT OUT OUT OUT
CK→Ripple Carry — — — — OUT
CK→Q OUT OUT OUT OUT —
CK→Q OUT OUT OUT OUT —
Enable T→Ripple Carry — — — — OUT
tPLH
tPHL
CLR→Q OUT OUT OUT OUT —
HD74LS161A
Rev.2.00, Feb.18.2005, page 7 of 10
Waveforms 1
ƒmax, tPLH, tPHL, (Clock→Q, Ripple Carry)
(Measure at t
n
+ 16)
(Measure at
t
n
+ 16)
(Measure at
t
n
+ 1)
(Measure at t
n
+ 8)
(Measure at t
n
+ 4)
(Measure at t
n
+ 2)
Ripple
Carry
Clock 1.3V 1.3V 1.3V
1.3V 1.3V
1.3V1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
1.3V
Q
A
Q
B
Q
C
Q
D
t
TLH
t
PLH
t
PLH
(Measure at
t
n
+ 15)
t
PLH
(Measure at t
n
+ 2)
t
PLH
(Measure at t
n
+ 4)
t
PLH
(Measure at t
n
+ 8)
t
PHL
t
PHL
t
PHL
t
PHL
t
PHL
t
w (CK)
t
THL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
0V
3V
10% 10%
90% 90%
Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
and : ƒmax tTLH = tTHL ≤ 2.5 ns.
tn is reference bit time when all outputs are low.
HD74LS161A
Rev.2.00, Feb.18.2005, page 8 of 10
Waveforms 2
tPLH, tPHL, (Clock→Q)
Clock
Data Inputs
A, B, C or D
Outputs
QA, QB, QC or QD
1.3V
1.3V 1.3V
1.3V
tTHL
tTLH
tTHL
tTLH
tPLH tPHL
VOH
VOL
0V
3V
0V
3V
10% 10%
90%
10% 10%
90%
90% 90%
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input: PRR = 1 MHz, duty cycle 50%,
Data input: PRR = 500 kHz, duty cycle 50%
Waveforms 3
tPLH, tPHL, (Enable T→Ripple Carry)
t
PLH
t
PHL
V
OH
V
OH
0 V
3 V
1.3 V
1.3 V 1.3 V
1.3 V
Enable T
Carry
Output
10 %
90 %
t
TLH
t
THL
10 %
90 %
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz
Waveforms 4
tPHL, (Clear→Q)
Clear
QA to QD
1.3V
1.3V
1.3V
tTHL tTLH
tPHL
tw (CLR) ≥ 20ns
VOH
VOL
0V
3V
10%10%
90% 90%
Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns
HD74LS161A
Rev.2.00, Feb.18.2005, page 9 of 10
Package Dimensions
7.62
DP-16FV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
19.2
6.3
5.06
MASS[Typ.]
1.05g
A
Z
b
D
E
A
b
c
θ
e
L
1
1
p
3
e
0.51
0.56
1.30
0.19 0.25 0.31
2.29 2.54 2.79
0
°
15
°
PRDP0016AE-BP-DIP16-6.3x19.2-2.54
20.32
7.4
0.40 0.48
1.12
2.54
1
p
1
3
1 8
16 9
e
b
A
LA
Z
e c
E
D
b
0.89
θ
( Ni/Pd/Au plating )
0.80
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-16DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.24g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP16-5.5x10.06-1.27 PRSP0016DH-B
*1
*2
E
81
16 9
xM
p
*3
y
F
Index mark
b
D
E
H
Z
A
Terminal cross section
( Ni/Pd/Au plating )
p
c
b
1
1
Detail F
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
HD74LS161A
Rev.2.00, Feb.18.2005, page 10 of 10
0.635
0.15
1.27
5.80 6.20
0.400.34
p
A
1
10.30
FP-16DNV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
1.75
1.270.600.40
3.95
0.250.140.10
0.46
0.250.200.15
6.10
8
°
0
°
0.25
1.08
9.90
0.15g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
e
L
A
P-SOP16-3.95x9.9-1.27 PRSP0016DG-A
Index mark
E
1
y
xM
p
*3
*2
*1
F
8
916
E
H
D
A
Zb
Terminal cross section
( Ni/Pd/Au plating )
p
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
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