1
®
FN7111.4
EL5127, EL5227, EL5327, EL5427
2.5MHz 4-, 8-, 10- and 12-Channel Rail-to-
Rail Buffers
The EL5127, EL5227, EL5327, and EL5427 are low power,
high voltage rail-to-rail input/output buffers designed for use
in reference voltage buffering applications in small LCD
displays. They are available in qua d (EL5127), octal
(EL5227), 10-Channel (EL5327), and 12-Channel (EL5427)
topologies. All buffers feature a -3dB bandwidth of 2.5MHz
and operate from just 133µA per buffer. This family also
features a continuous output drive capability of 30mA (sink
and source).
The quad channel EL5127 is available in the 10 Ld MSOP
package. The 8-Channel EL5227 is available in both the
20 Ld TSSOP and 24 Ld QFN packages, the 10-Channel
EL5327 in the 24 Ld TSSOP and 24 Ld QFN packages, and
the 12-Channel EL5427 in the 28 Ld TSSOP and 32 Ld QFN
packages. All buffers are specified for operation over the full
-40°C to +85°C temperature range.
Features
• 2.5MHz -3dB bandwidth
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 133µA
• High slew rate = 2.2V/µs
• Rail-to-rail input/output swing
• Ultra-small packages
• Pb-free plus anneal available (RoHS compliant)
Applications
• TFT-LCD drive circuits
• Electronic games
• Touch-screen displays
• Personal communication devices
• Personal digital assistants (PDAs)
• Portable instrumentation
Data Sheet May 4, 2007
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN7111.4
May 4, 2007
Ordering Information
PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. #
EL5127CY R - 10 Ld MSOP (3.0mm) MDP0043
EL5127CY-T7 R 7” 10 Ld MSOP (3.0mm) MDP0043
EL5127CY-T13 R 13” 10 Ld MSOP (3.0mm) MDP0043
EL5127CYZ (Note) BAAAH - 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043
EL5127CYZ-T7 (Note) BAAAH 7” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043
EL5127CYZ-T13 (Note) BAAAH 13” 10 Ld MSOP (3.0mm) (Pb-Free) MDP0043
EL5227CL 5227CL - 24 Ld QFN (4mmx5mm) MDP0046
EL5227CL-T7 5227CL 7” 24 Ld QFN (4mmx5mm) MDP0046
EL5227CL-T13 5227CL 13” 24 Ld QFN (4mmx5mm) MDP0046
EL5227CLZ (Note) 5227CLZ - 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046
EL5227CLZ-T7 (Note) 5227CLZ 7” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046
EL5227CLZ-T13 (Note) 5227CLZ 13” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046
EL5227CR 5227CR - 20 Ld TSSOP (4.4mm) MDP0044
EL5227CR-T7 5227CR 7” 20 Ld TSSOP (4.4mm) MDP0044
EL5227CR-T13 5227CR 13” 20 Ld TSSOP (4.4mm) MDP0044
EL5227CRZ (Note) 5227CRZ - 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173
EL5227CRZ-T7 (Note) 5227CRZ 7” 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173
EL5227CRZ-T13 (Note) 5227CRZ 13” 20 Ld TSSOP (4.4mm) (Pb-Free) M20.173
EL5327CL 5327CL - 24 Ld QFN (4mmx5mm) MDP0046
EL5327CL-T7 5327CL 7” 24 Ld QFN (4mmx5mm) MDP0046
EL5327CL-T13 5327CL 13” 24 Ld QFN (4mmx5mm) MDP0046
EL5327CLZ (Note) 5327CLZ - 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046
EL5327CLZ-T7 (Note) 5327CLZ 7” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046
EL5327CLZ-T13 (Note) 5327CLZ 13” 24 Ld QFN (4mmx5mm) (Pb-Free) MDP0046
EL5327CR 5327CR - 24 Ld TSSOP (4.4mm) MDP0044
EL5327CR-T7 5327CR 7” 24 Ld TSSOP (4.4mm) MDP0044
EL5327CR-T13 5327CR 13” 24 Ld TSSOP (4.4mm) MDP0044
EL5327CRZ (Note) 5327CRZ - 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044
EL5327CRZ-T7 (Note) 5327CRZ 7” 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044
EL5327CRZ-T13 (Note) 5327CRZ 13” 24 Ld TSSOP (4.4mm) (Pb-Free) MDP0044
EL5427CL 5427CL - 32 Ld QFN (5mmx6mm) MDP0046
EL5427CL-T7 5427CL 7” 32 Ld QFN (5mmx6mm) MDP0046
EL5427CL-T13 5427CL 13” 32 Ld QFN (5mmx6mm) MDP0046
EL5427CLZ (Note) 5427CLZ - 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046
EL5427CLZ-T7 (Note) 5427CLZ 7” 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046
EL5127, EL5227, EL5327, EL5427
3FN7111.4
May 4, 2007
EL5427CLZ-T13 (Note) 5427CLZ 13” 32 Ld QFN (5mmx6mm) (Pb-Free) MDP0046
EL5427CR 5427CR - 28 Ld TSSOP (4.4mm) MDP0044
EL5427CR-T13 5427CR 13” 28 Ld TSSOP (4.4mm) MDP0044
EL5427CRZ (Note) 5427CRZ - 28 Ld TSSOP (4.4mm) (Pb-Free) MDP0044
EL5427CRZ-T7 (Note) 5427CRZ 7” 28 Ld TSSOP (4.4mm) (Pb-Free) MDP0044
EL5427CRZ-T13 (Note) 5427CRZ 13” 28 Ld TSSOP (4.4mm) (Pb-Free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Ordering Information (Continued)
PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. #
EL5127, EL5227, EL5327, EL5427
4FN7111.4
May 4, 2007
Pinouts EL5127
(10 LD MSOP)
TOP VIEW
EL5227
(20 LD TSSOP)
TOP VIEW
EL5327
(24 LD TSSOP)
TOP VIEW
EL5427
(28 LD TSSOP)
TOP VIEW
EL5227, EL5327
(24 LD QFN)
TOP VIEW
EL5427
(32 LD QFN)
TOP VIEW
1
2
3
4
10
9
8
7
5 6
VIN1
VIN2
VS+
VIN3
VIN4
VOUT1
VOUT2
VOUT3
VOUT4
VS-
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
VIN1
VIN2
VIN3
VIN4
VS+
VOUT1
VOUT2
VOUT4
VS-
VOUT3
VS+
VIN5
VIN6
VIN7
VIN8
VS-
VOUT5
VOUT7
VOUT8
VOUT6
1
2
3
4
16
15
14
13
5
6
7
12
11
9
8
10
20
19
18
17
24
23
22
21
VIN1
VIN2
VIN3
VIN4
VIN5
VOUT1
VOUT2
VOUT4
VOUT5
VOUT3
VS+
VS+
VIN6
VIN7
VIN8
VS-
VS-
VOUT7
VOUT8
VOUT6
VIN9
VIN10
VOUT9
VOUT10
1
2
3
4
28
27
26
25
5
6
7
24
23
22
821
9
10
20
19
11
12
13
18
17
16
14 15
VIN1
VIN2
VIN3
VIN4
VIN5
VOUT1
VOUT2
VOUT4
VOUT5
VOUT3
VIN6
VS+
VS+
VIN7
VIN8
VOUT6
VS-
VOUT7
VOUT8
VS-
VIN9
VIN10
VIN11
VIN12
VOUT9
VOUT11
VOUT12
VOUT10
VIN3
VIN4
VIN5
VS+
VIN6
VIN7
VIN8
VOUT3
VOUT4
VOUT5
VS-
VOUT6
VOUT7
VOUT8
VIN2
VIN1*
NC
VOUT1*
VOUT2
VIN9
CVIN10*
NC
VOUT10*
VOUT9
19
18
17
16
15
14
13
24
23
22
21
20
8
9
10
11
12
1
2
3
4
5
6
7
THERMAL
PAD
* NOT AVAILABLE IN EL5227
THERMAL
PAD
25
24
23
22
21
20
19
32
31
30
29
28
10
11
12
13
14
1
2
3
4
5
6
7
VIN3
VIN4
VIN5
VIN6
VS+
VIN7
VIN8
VOUT3
VOUT4
VOUT5
VOUT6
VS-
VOUT7
VOUT8
VIN2
VIN1
NC
NC
NC
VIN11
VIN12
NC
NC
NC
8
9
18
17
15 27
16 26
VOUT9
VOUT10
VOUT12
VOUT11
VIN9
VIN10
VOUT1
VOUT2
EL5127, EL5227, EL5327, EL5427
5FN7111.4
May 4, 2007
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage Between VS+ and VS-. . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .VS- -0.5V, VS +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
ESD Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.
Electrical Specifications VS+ = +5V, VS- = -5V, RL = 10kΩ, CL = 10pF to 0V, TA = +25°C, Unless Otherwise Specified.
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VOS Input Offset Voltage VCM = 0V 1 15 mV
TCVOS Average Offset Voltage Drift (Note 1) 5 µV/°C
IBInput Bias Current VCM = 0V 2 50 nA
RIN Input Impedance 1GΩ
CIN Input Capacitance 1.35 pF
AVVoltage Gain -4.5V ≤ VOUT ≤ 4.5V 0.99 1.01 V/V
OUTPUT CHARACTERISTICS
VOL Output Swing Low IL = -5mA -4.95 -4.85 V
VOH Output Swing High IL = +5mA 4.85 4.95 V
IOUT (max) Max Output Current (Note 2 ) RL = 10Ω100 ±120 mA
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio VS is moved from ±2.25V to ±7.75V 55 80 dB
ISSupply Current No load (EL5127) 0.7 0.9 mA
No load (EL5227) 1.2 1.4 mA
No load (EL5327) 1.4 2 mA
No load (EL5427) 1.6 2.2 mA
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3) -4.0V ≤ VOUT ≤ 4.0V, 20% to 80% 0.9 2.2 V/µs
tSSettling to +0.1% (AV = +1) (AV = +1), VO = 2V step 900 ns
BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz
CS Channel Separation f = 100kHz 75 dB
NOTES:
1. Measured over operating temperature range.
2. Instantaneous peak current.
3. Slew rate is measured on rising and falling edges.
EL5127, EL5227, EL5327, EL5427
6FN7111.4
May 4, 2007
Electrical Specifications VS+ = +5V, VS- = 0V, RL = 10kΩ, CL = 10pF to 2.5V, TA = +25°C, Unless Otherwise Specified.
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VOS Input Offset Voltage VCM = 2.5V 1 15 mV
TCVOS Average Offset Voltage Drift (Note 4) 5 µV/°C
IBInput Bias Current VCM = 2.5V 2 50 nA
RIN Input Impedance 1GΩ
CIN Input Capacitance 1.35 pF
AVVoltage Gain 0.5V ≤ VOUT ≤ 4.5V 0.99 1.01 V/V
OUTPUT CHARACTERISTICS
VOL Output Swing Low IL = -5mA 80 150 mV
VOH Output Swing High IL = +5mA 4.85 4.95 V
IOUT (max) Output Current (Note 5) RL = 10Ω100 ±120 mA
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 55 80 dB
ISSupply Current No load (EL5127) 0.7 0.9 mA
No load (EL5227) 1.1 1.35 mA
No load (EL5327) 1.35 1.9 mA
No load (EL5427) 1.5 2.05 mA
DYNAMIC PERFORMANCE
SR Slew Rate (Note 6) 1V ≤ VOUT ≤ 4V, 20% to 80% 0.9 1.5 V/µs
tSSettling to +0.1% (AV = +1) (AV = +1), VO = 2V step 1000 ns
BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz
CS Channel Separation f = 5MHz 75 dB
NOTES:
4. Measured over operating temperature range.
5. Instantaneous peak current.
6. Slew rate is measured on rising and falling edges.
EL5127, EL5227, EL5327, EL5427
7FN7111.4
May 4, 2007
Electrical Specifications VS+ = +15V, VS- = 0V, RL = 10kΩ, CL = 10pF to 7.5V, TA = +25°C, Unless Otherwise Specified.
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VOS Input Offset Voltage VCM = 7.5V 1 18 mV
TCVOS Average Offset Voltage Drift (Note 7) 5 µV/°C
IBInput Bias Current VCM = 7.5V 2 50 nA
RIN Input Impedance 1GΩ
CIN Input Capacitance 1.35 pF
AV Voltage Gain 0.5V ≤ VOUT ≤ 14.5V 0.99 1.01 V/V
OUTPUT CHARACTERISTICS
VOL Output Swing Low IL = -5mA 50 150 mV
VOH Output Swing High IL = +5mA 14.85 14.95 V
IOUT (max) Output Current (Note 8) RL = 10Ω100 ±120 mA
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio VS is moved from 4.5V to 15.5V 55 80 dB
ISSupply Current No load (EL5127) 0.75 0.95 mA
No load (EL5227) 1.3 1.55 mA
No load (EL5327) 1.5 2.1 mA
No load (EL5427) 1.6 2.4 mA
DYNAMIC PERFORMANCE
SR Slew Rate (Note 9) 1V ≤ VOUT ≤ 14V, 20% to 80% 0.9 2.2 V/µs
tSSettling to +0.1% (AV = +1) (AV = +1), VO = 2V step 900 ns
BW -3dB Bandwidth RL = 10kΩ, CL = 10pF 2.5 MHz
CS Channel Separation f = 5MHz 75 dB
NOTES:
7. Measured over operating temperature range.
8. Instantaneous peak current.
9. Slew rate is measured on rising and falling edges.
EL5127, EL5227, EL5327, EL5427
8FN7111.4
May 4, 2007
Typical Performance Curves
FIGURE 1. FREQEUNCY RESPONSE FOR VARIOUS RLFIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 3. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 4. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 5. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY FIGURE 6. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
20
10
0
-10
-20
-30
1K 10K 100K 1M 10M
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
1kΩ10kΩ
562Ω
150Ω
CL=10pF
VS=±5V
20
10
0
-10
-20
-30
1K 10K 100K 1M 10M
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
47pF
12pF
1nF
100pF
RL=10kΩ
VS=±5V
2000
1600
1200
800
400
0
1K 10K 100K 1M
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
TA=25°C
VS=±5V
12
10
8
6
4
0
10K 100K 1M 10M
FREQUENCY (Hz)
MAXIMUM OUTPUT SWING (VP-P)
2
VS=±5V
RL=10kΩ
CL=12pF
TA=25°C
300
100
10
1K 10K 100K 10M 100M
FREQUENCY (Hz)
VOLTAGE NOISE (nV/√Hz)
1M
0.12
0.1
0.08
0.06
0.04
0.02
0
1K 10K 100K
FREQUENCY (Hz)
THD + NOISE (%)
EL5127, EL5227, EL5327, EL5427
9FN7111.4
May 4, 2007
FIGURE 7. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE FIGURE 8. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 9. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 10. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FIGURE 11. OUTPUT LOW VOLTAGE vs TEMPERATURE FIGURE 12. VOLTAGE GAIN vs TEMPERATURE
Typical Performance Curves
100
30
20
010 100 1K
CAPACITANCE (pF)
OVERSHOOT (%)
90
70
50
80
60
40
VS=±5V
RL=10kΩ
VIN=±50mV
TA=25°C
18
16
14
12
10
8
6
4
2
0
-10
-8
-6
-4
-2
0
2
4
6
8
10
INPUT OFFSET VOLTAGE (mV)
% OF BUFFERS
3.5
3
2.5
2
1.5
185
TEMPERATURE (°C)
INPUT BIAS CURRENT (nA)
-35 -15 5 25 45 65
VS=±5V 4.955
4.95
4.945
4.94
4.935
4.925 85
TEMPERATURE (°C)
OUTPUT HIGH VOLTAGE (V)
-35-155 254565
4.93
VS=±5V
IOUT=5mA
-4.938
-4.958 85
TEMPERATURE (°C)
OUTPUT LOW VOLTAGE (V)
-35-155 254565
-4.942
-4.946
-4.95
-4.954
VS=±5V
IOUT=-5mA
1.0045
1.004
1.003
1.0025
1.002
1.001 85
TEMPERATURE (°C)
VOLTAGE GAIN (V/V)
-35 -15 5 25 45 65
1.0015
1.0035
VS=±5V
EL5127, EL5227, EL5327, EL5427
10 FN7111.4
May 4, 2007
FIGURE 13. SLEW RATE vs TEMPERATURE FIGURE 14. SUPPLY CURRENT PER CHANNEL vs
TEMPERATURE
FIGURE 15. SUPPLY CURRENT PER CHANNEL vs SUPPLY
VOLTAGE FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 18. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE
Typical Performance Curves
2.255
2.245
2.235
2.225
2.215 80
TEMPERATURE (°C)
SLEW RATE (V/µs)
-40 400-20 6020
VS=±5V
0.185
0.18
0.175
0.17
0.16 85
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
-35 -15 5 25 45 65
0.165
VS=±5V
0.195
0.19
0.185
0.175
0.165 18
SUPPLY VOLTAG E (V)
SUPPLY CURRENT (mA)
4 6 8 12 14 16
0.17
0.18
10
TA=25°C
4µs/DIV
1V/DIV
1µs/DIV
20mV/DIV
3
2.5
2
1.5
1
0.5
00 25 50 75 100 125 15085
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
2.703W
2.857W
QFN32
θJA=35°C/W
QFN24
θJA=37°C/W
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
870mW
MSOP10
θJA=115°C/W
EL5127, EL5227, EL5327, EL5427
11 FN7111.4
May 4, 2007
Applications Information
Product Descr iption
The EL5127, EL5227, EL5327, and EL5427 unity gain
buffers are fabricated using a high voltage CMOS process. It
exhibits rail-to-rail input and output capability and has low
power consumption (120µA per buffer). These features
make the EL5127, EL5227, EL5327, and EL5427 ideal for a
wide range of general-purpose applica tio ns. When driving a
load of 10kΩ and 12pF, the EL5127, EL5227, EL5327, and
EL5427 have a -3dB bandwidth of 2.5MHz and exhibits
2.2V/µs slew rate.
Operating Voltage, Input, and Output
The EL5127, EL5227, EL5327, and EL5427 are specified
with a single nominal supply voltage from 5V to 15V or a split
supply with its total range from 5V to 15V. Correct operation
is guaranteed for a supply range of 4.5V to 16.5V. Most
EL5127, EL5227, EL5327, and EL5427 specifications are
stable over both the full supply range and operating
temperatures of -40°C to +85°C. Parameter variations with
operating voltage and/or temperature are shown in the
typical performance curves.
The output swings of the EL5127, EL5227, EL5327, and
EL5427 typically extend to within 80mV of positive and
negative supply rails with load currents of 5mA. Decreasing
load currents will extend the output voltage range even
closer to the supply rai ls. Figure 22 shows the input and
output waveforms for the device. Operation is from ±5V
supply with a 10kΩ load connected to GND. The input is a
10VP-P sinusoid. The output voltage is approximately
9.985VP-P.
FIGURE 19. P ACKAGE POWER DISSIPA TION vs AMBIENT
TEMPERATURE FIGURE 20. P ACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
0
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
1.2
1
0.8
0.6
0.4
0.2
025 50 75 100 12585
1.111W
1.333W
1.176W
TSSOP28
θJA=75°C/W
TSSOP24
θJA=85°C/W
TSSOP20
θJA=90°C/W
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00 255075 125150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
10085
714mW
758mW
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
QFN32
θJA=132°C/W
486mW
MSOP10
θJA=206°C/W
QFN24
θJA=140°C/W
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00 255075100125
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
85
714mW
833mW 781mW
TSSOP28
θJA=120°C/W
TSSOP24
θJA=128°C/W
TSSOP20
θJA=140°C/W
EL5127, EL5227, EL5327, EL5427
12 FN7111.4
May 4, 2007
FIGURE 22. OPERA TION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short Circuit Current Limit
The EL5127, EL5227, EL5327, and EL5427 will limit the
short circuit current to ±120mA if the outp u t is di re ctl y
shorted to the positive or the negative supply. If an output is
shorted indefinitely, the power dissipation could easily
increase such that the device may be damaged. Maximum
reliability is maintained if the output continuous current never
exceeds ±30mA. This limit is set by the design of the internal
metal interconnects.
Output Phase Reversal
The EL5127, EL5227, EL5327, and EL5427 are immune to
phase reversal as long as the input voltage is limited from
VS- -0.5V to VS+ +0.5V. Figure 23 shows a photo of the
output of the device with the input voltage driven beyond the
supply rails. Although the device's outp ut will not change
phase, the input's overvoltage should be avoided. If an input
voltage exceeds supply voltage by more than 0.6V,
electrostatic protection diodes placed in the input stage of
the device begin to conduct and overvoltage damage could
occur.
FIGURE 23. OPERATION WITH BEYOND -THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5127, EL5227,
EL5327, and EL5427 buffer, it is possible to exceed the
+125°C “absolute-maximum junction temperature” under
certain load current conditions. Therefore, it is important to
calculate the maximum junction temperature for the
application to determine if load conditions need to be
modified for the buffer to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temper at ure
θJA = Thermal resistance of the package
PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
when sourcing, and:
when sinking.
where:
i = 1 to Total number of buffers
VS = Total supply voltage
ISMAX = Maximum quiescent current per channel
VOUTi = Maximum output voltage of the application
ILOADi = Load current
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. The package
power dissipation curves provide a convenient way to see if
the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
equation, it is a simple matter to see if PDMAX exceeds the
device's power derating curves.
Unused Buff ers
It is recommended that any unused buffer have the input tied
to the ground plane.
OUTPUT INPUT
5V
VS=±5V
TA=25°C
VIN=10VP-P
5V
10µs
1V
VS=±2.5V
TA=25°C
VIN=6VP-P
1V
10µs
PDMAX TJMAX - TAMAX
ΘJA
---------------------------------------------
=
PDMAX ΣiV[SISMAX VS+( - VOUTi)ILOADi]×+×=
PDMAX ΣiV[SISMAX V(OUTi - VS-)ILOADi×+×]=
EL5127, EL5227, EL5327, EL5427
13 FN7111.4
May 4, 2007
Driving Capacitive Loads
The EL5127, EL5227, EL5327, and EL5427 can drive a wide
range of capacitive loads. As load capacitance increases,
however , the -3dB bandwidth of the device will decrease and
the peaking increase. The bu ffers drive 10pF loads in
parallel with 10kΩ with just 1.5dB of peaking, and 100pF
with 6.4dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5Ω and
50Ω) can be placed in series with the output. However, this
will obviously reduce the gain sligh tly. Another meth od of
reducing peaking is to add a “snubber” ci rcuit at the output.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. Values of 150Ω and 10nF are typical. The
advantage of a snubber is that it does not draw any DC load
current or reduce the gain.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillati on. For
normal single supply operati on, where the VS- pin is
connected to ground, a 0.1µF cera mic capacitor should be
placed from VS+ pin to VS- pin. A 4.7µF tantalum capacitor
should then be connected from VS+ pin to ground. One
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
EL5127, EL5227, EL5327, EL5427
14 FN7111.4
May 4, 2007
EL5127, EL5227, EL5327, EL5427
Mini SO Package Family (MSOP)
1(N/2)
(N/2)+1
N
PLANE
SEATING
N LEADS
0.10 C
PIN #1
I.D.
E1E
b
DETAIL X
3° ±3°
GAUGE
PLANE
SEE DETAIL "X"
c
A
0.25
A2
A1 L
0.25 C A B
D
A
M
B
e
C
0.08 C A B
M
H
L1
MDP0043
MINI SO PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE NOTESMSOP8 MSOP10
A1.101.10 Max. -
A1 0.10 0.10 ±0.05 -
A2 0.86 0.86 ±0.09 -
b 0.33 0.23 +0.07/-0.08 -
c0.180.18 ±0.05 -
D 3.00 3.00 ±0.10 1, 3
E4.904.90 ±0.15 -
E1 3.00 3.00 ±0.10 2, 3
e0.650.50 Basic -
L0.550.55 ±0.15 -
L1 0.95 0.95 Basic -
N 8 10 Reference -
Rev. D 2/07
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
15 FN7111.4
May 4, 2007
EL5127, EL5227, EL5327, EL5427
QFN (Quad Flat No-Lead) Package Family
PIN #1
I.D. MARK
2
1
3
(N-2)
(N-1)
N
(N/2)
2X
0.075
TOP VI EW
(N/2)
NE
2
3
1
PIN #1 I.D.
(N-2)
(N-1)
N
b
L
N LEADS
BOTTOM VIEW
DETAIL X
PLANE
SEATING
N LEADS
C
SEE DETAIL "X"
A1 (L)
N LEADS
& EXPOSED PAD
0.10
SIDE VIEW
0.10 BA
MC
C
B
A
E
2X
0.075 C
D
3
5
7
(E2)
(D2)
e
0.08 C
C
(c)
A2
C
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY
(COMPLIANT TO JEDEC MO-220)
SYMBOL
MILLIMETERS
TOLERANCE NOTESQFN44 QFN3 QFN32
A 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 +0.03/-0.02 -
b 0.25 0.25 0.23 0.22 ±0.02 -
c 0.20 0.20 0.20 0.20 Reference -
D 7.00 5.00 8.00 5.00 Basic -
D2 5.10 3.80 5.80 3.60/2.48 Reference 8
E 7.00 7.00 8.00 6.00 Basic -
E2 5.10 5.80 5.80 4.60/3.40 Reference 8
e 0.50 0.50 0.80 0.50 Basic -
L 0.55 0.40 0.53 0.50 ±0.05 -
N 44 38 32 32 Reference 4
ND 11 7 8 7 Reference 6
NE 11 12 8 9 Reference 5
SYMBOL
MILLIMETERS TOLER-
ANCE NOTESQFN28 QFN2 QFN20 QFN16
A 0.90 0.90 0.90 0.90 0.90 ±0.10 -
A1 0.02 0.02 0.02 0.02 0.02 +0.03/
-0.02 -
b 0.25 0.25 0.30 0.25 0.33 ±0.02 -
c 0.20 0.20 0.20 0.20 0.20 Reference -
D 4.00 4.00 5.00 4.00 4.00 Basic -
D2 2.65 2.80 3.70 2.70 2.40 Reference -
E 5.00 5.00 5.00 4.00 4.00 Basic -
E2 3.65 3.80 3.70 2.70 2.40 Reference -
e 0.50 0.50 0.65 0.50 0.65 Basic -
L 0.40 0.40 0.40 0.40 0.60 ±0.05 -
N 28 24 20 20 16 Reference 4
ND 6 5 5 5 4 Reference 6
NE 8 7 5 5 4 Reference 5
Rev 11 2/07
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with radius
(b/2) as shown.
8. If two values are listed, multiple exposed pad options are available.
Refer to device-specific datasheet.
16 FN7111.4
May 4, 2007
EL5127, EL5227, EL5327, EL5427
Thin Shrink Small Outline Package Family (TSSOP)
N(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL
MILLIMETERS
TOLERANCE14 LD 16 LD 20 LD 24 LD 28 LD
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
17
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7111.4
May 4, 2007
EL5127, EL5227, EL5327, EL5427
Thin Shrink Small Outline Plastic Packages (TSSOP)
α
INDEX
AREA E1
D
N
123
-B-
0.10(0.004) C AMBS
e
-A-
b
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
c
E0.25(0.010) BM M
L
0.25
0.010
GAUGE
PLANE
A2
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
0.05(0.002)
M20.173
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.047 - 1.20 -
A1 0.002 0.006 0.05 0.15 -
A2 0.031 0.051 0.80 1.05 -
b 0.0075 0.0118 0.19 0.30 9
c 0.0035 0.0079 0.09 0.20 -
D 0.252 0.260 6.40 6.60 3
E1 0.169 0.177 4.30 4.50 4
e 0.026 BSC 0.65 BSC -
E 0.246 0.256 6.25 6.50 -
L 0.0177 0.0295 0.45 0.75 6
N20 207
α0o8o0o8o-
Rev. 1 6/98
