1/22
L6227
September 2003
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■2.8A OUTPUT PEAK CURRENT (1.4A DC)
■RDS(ON) 0.73Ω TYP. VALU E @ Tj = 25 °C
■OPERA TING FREQUENCY UP T O 100KHz
■NON DISSIPATIVE OVERCURRENT
PROTECTION
■DUAL INDEPENDENT CONSTANT tOFF PW M
CURRENT CONTROLLE RS
■SLOW DECAY SYNCHRONOUS
RECTIFICATION
■CROSS CONDUCTION PROTECTION
■THERMAL SHUTDOWN
■UNDER VOLTAG E LOCKOUT
■
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■BIPOLAR STEPPER MOTOR
■DUAL DC MOTOR
DESCRIPTION
The L6227 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar c ircuits on
the same chip. The device also includes two inde-
pendent constant off time PWM Current Controllers
that performs the chopping regulation. Available in
PowerDIP24 (20+2+2), PowerSO36 and SO24
(20+2+2) packages, the L6227 features a non-dissi-
pative overcurrent protection on the high side Power
MOSFETs and thermal shutdown.
BLOCK DIAGRAM
D99IN1085A
GATE
LOGIC
OCD
A
OCD
B
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
VREF
A
V
BOOT
5V10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR ONE SHOT
MONOSTABLE MASKING
TIME
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
SENSE
COMPARATOR
BRIDGE B
RC
A
+
-
SENSE
B
VREF
B
RC
B
PWM
ORDERING NUMBERS:
L6227N (PowerDIP24)
L6227PD (PowerSO36)
L6227D (SO24)
PowerDIP24
(20+2+2) PowerSO36 SO24
(20+2+2)
DMOS DUAL FULL BRIDGE DRIVER
WITH PWM CURRENT CONTROLLER
L6227
2/22
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test conditions Value Unit
VSSupply Voltage
V
SA
=
VSB =
VS60 V
VOD Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS = 60V;
V
SENSEA
= V
SENSEB = GND 60 V
VBOOT Bootstrap Peak Vol tage
V
SA
=
VSB =
VSVS + 10 V
VIN,VEN Input and Enable Voltage Range -0.3 to +7 V
VREFA,
VREFB Voltage Range at pins VREFA
and VREFB -0.3 to +7 V
VRCA, VRCB Voltage Range at pins RCA and
RCB-0.3 to +7 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB -1 to +4 V
IS(peak) Pulsed Supply Current (for each
VS pin), internally limited by the
overcurrent protection
V
SA
=
VSB =
VS;
tPULSE < 1ms 3.55 A
ISRMS Supply Current (for each
VS pin)
V
SA
=
VSB =
VS1.4 A
Tstg, TOP Storage and Operating
Temperature Range -40 to 150 °C
Symbol Parameter Test Conditions MIN MAX Unit
VSSupply Voltage
V
SA
=
VSB =
VS852V
V
OD Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS;
V
SENSEA
= V
SENSEB 52 V
VREFA,
VREFB Voltage Range at pins VREFA
and VREFB -0.1 5 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB(pulsed tW < trr)
(DC) -6
-1 6
1V
V
IOUT RMS Output Current 1.4 A
TjOperating Junction Temperature -25 +125 °C
fsw Switching Frequency 100 KHz
3/22
L6227
THE RMAL DA TA
PIN CONNECTIONS (Top View)
(5) The slug is internally connected to pins 1, 18,19 and 36 (GND pins).
Symbol Description PowerDIP24 SO24 PowerSO36 Unit
Rth-j-pins Maximum Thermal Resistance Junction-Pins 19 15 - °C/W
Rth-j-case Maximum Thermal Resistance Junction-Case - - 2 °C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 1
(1) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the bot tom side of 6cm2 (with a thickness of 35µm).
44 52 - °C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2
(2) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the top side of 6cm2 (with a thicknes s of 35µm).
--36°C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 3
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes
and a ground l ayer.
--16°C/W
Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4
(4) Mounted on a m ul ti-layer FR4 PCB without any heat s i nking surf ace on th e board.
59 78 63 °C/W
PowerDIP24/SO24 PowerSO 36 (5)
GND
GND
OUT1
B
RC
B
SENSE
B
IN2
B
IN1
B
1
3
2
4
5
6
7
8
9
VREF
B
VBOOT
EN
B
OUT2
B
VS
B
GND
GND19
18
17
16
15
13
14
D02IN1346
10
11
12
24
23
22
21
20
IN1
A
IN2
A
SENSE
A
RC
A
OUT1
A
VS
A
OUT2
A
VCP
EN
A
VREF
A
GND
N.C.
N.C.
VS
A
RC
A
OUT1
A
N.C.
N.C.
N.C. N.C.
N.C.
OUT1
B
RC
B
N.C.
VS
B
N.C.
N.C.
GND
18
16
17
15
6
5
4
3
2
21
22
31
32
33
35
34
36
20
1
19
GND GND
D02IN1347
IN1
A
SENSE
A
IN2
A
SENSE
B
IN2
B
IN1
B
9
8
7
28
29
30
VREF
A
VREF
B
10 27
OUT2
A
EN
A
VCP
EN
B
OUT2
B
VBOOT
14
12
11
23
25
26
N.C. N.C.
13 24
L6227
4/22
PIN DESCRIPTION
PACKAGE
Name Type Function
SO24/
PowerDIP24
PowerSO36
PIN # PIN #
1 10 IN1ALogic input Bridge A Logic Input 1.
2 11 IN2ALogic input Bridge A Logic Input 2.
3 12 SENSEAPower Supply Bridge A Source Pin. This pin must be connected to Po wer
Ground through a sensing power resistor.
413RC
ARC Pin RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
5 15 OUT1APower Output Bridge A Output 1.
6, 7,
18, 19 1, 18,
19, 36 GND GND Signal Ground terminals. In Power DIP and SO packages,
these pins are also used for heat dissipation toward the
PCB.
8 22 OUT1BPower Output Bridge B Output 1.
924RC
BRC Pin RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
10 25 SENSEBP ower Supply Bridge B Source Pin. This pin must be connected to Po wer
Ground through a sensing power resistor.
11 26 IN1BLogic Input Bridge B Input 1
12 27 IN2BLogic Input Bridge B Input 2
13 28 VREFBAnalog Input Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
14 29 ENBLogic Input (6) Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
15 30 VBOOT Supply
Voltage Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
16 32 OUT2BPower Output Bridge B Output 2.
17 33 VSBPower Supply Bridge B Power Supply Voltage. It must be connected to
the supply voltage together with pin VSA.
20 4 VSAPower Supply Bridge A Power Supply Voltage. It must be connected to
the supply voltage together with pin VSB.
21 5 OUT2APower Output Bridge A Output 2.
22 7 VCP Output Charge Pump Oscillator Output.
5/22
L6227
(6) Also connected at the output drain o f the Over current an d T herma l protecti on MOSF ET. Therefor e, it has to be driven putting in
seri es a resistor with a value in the range of 2. 2KΩ - 180K Ω, rec om m end e d 100K Ω.
23 8 ENALogic Input (6) Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
24 9 VREFAAnalog Input Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
VSth(ON) Turn-on Threshold 5.8 6.3 6.8 V
VSth(OFF) Turn-off Threshold 5 5.5 6 V
ISQuiescent Supply Current All Bridges OFF;
Tj = -25°C to 125°C (7) 510mA
T
j(OFF) Thermal Shutdown Temperature 165 °C
Output DMOS Tra nsist ors
RDS(ON) High-Side +Low-Side Switch ON
Resistance Tj = 25 °C 1.47 1.69 Ω
Tj =125 °C (7) 2.35 2.7 Ω
IDSS Leakage Current EN = Low; OUT = VS2mA
EN = Low; OUT = GND -0.3 mA
Source Drain Diodes
VSD Forward ON Voltage ISD = 1.4A, EN = LOW 1.15 1.3 V
trr Reverse Recover y Time If = 1.4A 300 ns
tfr Forward Recovery Time 200 ns
Logic Input
VIL Low level logic input voltage -0.3 0.8 V
VIH High level logic input voltage 2 7 V
IIL Low Level Logic Input Current GND Logic Input Voltage -10 µA
IIH High Level Logic Input Current 7V Logic Input Voltage 10 µA
Vth(ON) Turn-on Input Threshold 1.8 2.0 V
Vth(OFF) Turn-off Input Threshold 0.8 1.3 V
Vth(HYS) Input Threshold Hysteresis 0.25 0.5 V
Switching Characteristics
tD(on)EN
Enable to out turn O N delay tim e
(8)
ILOAD =1.4A, Resistive Load 500 800 ns
PIN DESCRIPTION
(continued)
L6227
6/22
(7) Tested at 25°C in a restricted range and guaranteed by characterization.
(8) See Fig. 1.
(9) Measure d applying a volta ge of 1V to pi n S EN SE and a voltage drop from 2V to 0V to pin VR E F .
(10) See Fig. 2.
tD(on)IN Input to out turn ON delay time ILOAD =1.4A, Resistive Load
(dead time included) 1.9 µs
tRISE Output rise time(8) ILOAD =1.4A, Resistive Load 40 250 ns
tD(off)EN
Enable to out turn OFF delay time
(8)
ILOAD =1.4A, Resistive Load 500 800 1000 ns
tD(off)IN
Input to out turn OFF delay time
ILOA D =1.4A, Resistive Load 500 800 1000 ns
tFALL Output Fall Time (8) ILOAD =1.4A, Resistive Load 40 250 ns
tdt Dead Time Protection 0.5 1 µs
fCP Charge pump frequency -25°C<Tj <125°C 0.6 1 MHz
PWM Comparator and Monostable
I
RCA,
I
RCB
Source Current at pins RC
A
and
RC
B
VRCA = VRCB = 2.5V 3.5 5.5 mA
Voffset Offset Voltage on Sense
Comparator VREFA, VREFB = 0.5V ±5 mV
tPROP Turn OFF Propagation Delay (9) 500 ns
tBLANK Internal Blanking Time on
SENSE pins 1µs
t
ON(MIN) Minimum On Time 2.5 3 µs
tOFF PWM Recirculation Time ROFF = 20KΩ; COFF = 1nF
13
µs
ROFF = 100KΩ; COFF = 1nF
61
µs
IBIAS Input Bias Current at pins VREF A
and VREFB 10 µA
Over Current Protection
ISOVER Input Supply Overcurrent
Protection Threshold Tj = -25°C to 125°C (7) 2 2.8 3.55 A
ROPDR Open Drain ON Resistance I = 4mA 40 60 Ω
tOCD(ON) OCD Turn-on Delay Time (10) I = 4mA; CEN < 100pF 200 ns
tOCD(OFF) OCD Turn-off Delay Time (10) I = 4mA; CEN < 100pF 100 ns
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25 °C, Vs = 48V, unless otherwise spe cified)
Symbol Parameter Test Conditions Min Typ Max Unit
7/22
L6227
Figure 1. Switching Characteristi c Definition
Figu re 2. Overcurre nt D et ect i on Tim i ng Defi ni tio n
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
ISOVER
90%
10%
IOUT
VEN
tOCD(OFF)
tOCD(ON)
D02IN1399
ON
OFF
BRIDGE
L6227
8/22
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6227 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rdson =
0.73ohm (typical value @ 25°C), with intrinsic fast
freewheeling diode. Cross conduction protection is
achieved using a dead time (td = 1
µ
s typical) be-
tween the switch off and switch on of two Pow er MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive vol tage above
the power supply voltage. The Bootstrapped
(VBOO T) supply is obtained through an internal Os-
cillator and few external components to realize a
charge pump circuit as shown in Figure 3. The oscil-
lator output (VCP) is a square wave at 600kHz (typi-
cal) with 10V amplitude. Recommended values/part
numbers for the charge pump circuit are shown in
Table1.
Table 1. Charge Pump External Components
Values
Figu re 3. Charge Pum p Circ u it
LOGIC INPUTS
Pins IN1
A
, IN2
B
, IN1
B
and IN2
B
are TTL/CMOS and
uC compatible logic inputs. The internal structure is
shown in Fi g. 4. Typical value for turn- on and turn-off
thresholds are respectively Vthon = 1.8V and Vthoff
= 1.3V.
Pins EN
A
and EN
B
have id entical input structure w ith
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) ar e also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The EN
A
and EN
B
in-
puts may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
(collector) structure, a pull-up resistor R
EN
and a ca-
pacitor C
EN
are connected as shown in Fig. 5. If the
driver is a standard Push-Pull structure the resistor
R
EN
and the capacitor C
EN
are connected as shown
in Fig. 6. The resistor R
EN
should be chosen in the
range from 2.2k
Ω
to 180K
Ω
. Recommended values
for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figu re 4. Lo gi c Inp uts I nte rn al S truc ture
Figure 5. EN
A
and EN
B
Pins Open Collector
Driving
Figure 6. EN
A
and EN
B
Pins Push-Pull Driving
CBOOT 220nF
CP10nF
RP100Ω
D1 1N4148
D2 1N4148
D2 CBOOT
D1
RP
CP
VS
VSA
VCP VBOOT VSB
D01IN1328
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
REN
CEN
ENA or ENB
D02IN134
9
5V
PUSH-PULL
OUTPUT
REN
CEN
ENA or ENB
D02IN135
0
9/22
L6227
TRUTH TABLE
X = Don't care
High Z = High Impedance Output
GND (Vs) = GND during Ton, Vs during Toff
(*) Valid only in case of load connected between OUT1 and OUT2
PWM CURRENT CONTROL
The L6227 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be-
tween the source of the two lower power MOS transistors and ground, as show n in Figure 7. As the current in
the load builds up the voltag e across the sens e r esistor incr eases proportionally . W hen the vo ltage drop ac ross
the sense resistor becomes greater than the voltage at the reference input (VREF
A
or VREF
B
) the sense com-
parator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 7. PWM Current Controller S impl ified Schemati c
Figur e 8 shows the typical operating waveforms of the output current, the voltage drop acr oss the sensing re-
sistor, the R C pin voltage and the status of the bridge. Immediately after the low-side P ower MOS turns on, a
high peak current flow s through the sen sing resistor due to the rev ers e recovery of the freewheeling diodes . The
L622 7 provides a 1
µ
s Blank ing Time t
BLANK
that inhibits the compar ator output so that thi s current spik e cannot
prematurely re-trigger the monostable.
INPUTS OUTPUTS Description (*)
EN IN1 IN2 OUT1 OUT2
L X X High Z High Z Disable
H L L GND GND Brake Mode (Lower Path)
H H L Vs GND (Vs) Forward
H L H GND (Vs) Vs Reverse
H H H Vs Vs Brake Mode (Upper Path)
DRIVERS
+
DEAD TIME
S
Q
RDRIVERS
+
DEAD TIME
2H 1H
2L 1L
OUT2A(or B)
SENSEA(or B)
RSENSE
D02IN1352
RCA(or B)
R
C
VREFA(or B)
IOUT
OUT1A(or B)
+
+
-
-
1µs
5mA
BLANKER
SENSE
COMPARATOR
COMPARATOR
OUTPUT
MONOSTABLE
RESET
2.5V
5V
FROM THE
LOW-SIDE
GATE DRIVERS
LOAD
A
(or
B
)
BLANKING TIME
MONOSTABLE
VS
A
(or B)
TO GATE LOGIC
(0) (1)
L6227
10/22
Figure 8. Output Current Regulation Wavefo rms
Figure 9 shows the magnitude of the Off Time t
OFF
versus C
OFF
and R
OFF
values. It can be approximately cal-
culated from the equations:
t
RCFALL
= 0.6 · R
OFF
· C
OFF
t
OFF
= t
RCFALL
+ t
DT
= 0.6 · R
OFF
· C
OFF
+ t
DT
where R
OFF
and C
OFF
are the external component values and t
DT
is the internally generated Dead Time with:
20K
Ω
≤
R
OFF
≤
100K
Ω
0.47nF
≤
C
OFF
≤
100nF
t
DT
= 1µs (typical value)
Therefore:
t
OFF(MIN)
= 6.6µs
t
OFF(MAX)
= 6ms
These values allow a sufficient range of t
OFF
to implement the drive circuit for most motors.
The capacitor value chosen for C
OFF
also affects the Rise Time t
RCRISE
of the voltage at the pin RCOFF. The
Rise Time t
RCRISE
will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time t
ON
, which depends by motors and supply parameters, has to
OFF BCDDA
t
ON tOFF
BC
ON
2.5V
0Slow Decay Slow Decay
1µs tBLANK
tRCRISE tRCRISE
SYNCHRONOUS RECTIFICATION
1µs tBLANK
5V
VRC
VSENSE
VREF
IOUT
VREF
RSENSE
D02IN1351
tOFF
1µs tDT 1µs tDT
tRCFALL tRCFALL
11/22
L6227
be bigger than t
RCRISE
for allowing a good current regulation by the PWM stage. Furthermore, the on time t
ON
can not be smaller than the minimum on time t
ON(MIN)
.
t
RCRISE
= 600 · C
OFF
Figure 10 shows the lower limit for the on time t
ON
for having a good PWM current regulation capac ity. It has to
be said that t
ON
is always bigger than t
ON(MIN)
because the device imposes this condition, but it can be smaller
than t
RCRISE
- t
DT
. In this last case the device continues to work but the off time t
OFF
is not more constant.
So, small C
OFF
value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for C
OFF
, the more influential will be the noises on the circuit
performance.
Figure 9. tOFF versus COFF and ROFF
tON tON MIN()
>2.5µs (typ. value)=
tON tRCRISE tDT
–>
0.1 1 10 100
1
10
100
1.103
1.104
Coff [nF]
toff [µs]
Roff = 100kΩ
Roff = 47kΩ
Roff = 20kΩ
L6227
12/22
Figure 10. Area where tON can vary maintaining the PWM regulation.
SLOW DECAY MODE
Figu re 11 s hows the operation of the bridge i n the Sl ow De cay mode. At the start of the off ti me, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage acr oss
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the s ynchro-
nous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 11. Slow Decay Mo de Output Stage Config urations
0.1 1 10 100
1
10
100
Coff [nF]
ton(min) [µs]
1.5µs (typ. value)
A) ON TIME B) 1µs DEAD TIME C) SYNCHRONOUS
RECTIFICATION D) 1µs DEAD TIME
D01IN1336
13/22
L6227
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6227 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
cir cuit to gr ound or between two phases of the br idge. With this internal over current detection, the external cur -
rent sense resistor normally used and its associated power dissipation are eliminated. Figure 12 shows a sim-
plified schematic of the overcurrent detection circuit.
To implement the over current detection, a sens ing element that deli vers a small but preci se fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current in one bridge reaches the detection threshold (typically 2.8A) the relative
OCD compar ator signals a fault condi tion. When a fault condition is detec ted, the EN pin is pulled belo w the tur n
off threshold (1.3V typical) by an internal open drain MOS with a pull dow n capability of 4mA . B y using an ex-
ternal R-C on the EN pin, the off time before recovering normal operation can be easil y program med by m eans
of the accurate thresholds of the logic inputs.
Figure 12. Overcu rrent Pro tection Simplified Schematic
Figure 13 shows the Overcurrent Detection operation. The Disable Time t
DISABLE
before recovering normal oper-
ation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
C
EN
and R
EN
values and its magnitude is reported in Figure 14. The Delay Time t
DELAY
before turning off the
bridge when an overcurrent has been detected depends only by C
EN
value. Its magnitude is reported in Figure 15.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be c hosen as big as possi ble acc or ding to the maximum tolerable D elay Time and th e R
EN
value should
be chosen according to the desired Disable Time.
The res istor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Recom mended val ues for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF that allow obtaining 200
µ
s Disable Time.
+
OVER TEMPERATURE
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
EN
R
EN
EN
A
+5V
µC or LOGIC
D02IN1353
L6227
14/22
Figure 13. Overcur rent Protecti on Waveforms
ISOVER
IOUT
Vth(ON)
Vth(OFF) VEN(LOW)
VDD
tOCD(ON) tD(ON)EN
tEN(FALL) tEN(RISE)
tDISABLE
tDELAY
tOCD(OFF)
tD(OFF)EN
VEN
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1400
15/22
L6227
Figure 14. tDISABLE versu s C EN and REN (VDD = 5V ).
Figure 15. tDELAY versus CEN (VDD = 5V ).
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6227 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
110100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
110100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
1 10 100
0.1
1
10
Cen [n F]
tdelay [µs]
L6227
16/22
APPLICATION INFORMATION
A typical application using L6227 is shown in Fig. 16. Typical component values for the application are shown
in Table 3. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins ( VS
A
and VS
B
) and ground near the L6227 to improve the high frequenc y fil ter ing on the power supply and
reduc e high frequency transients ge nerate d by the switchi ng. The capaci tors connected from the EN
A
and EN
B
inputs to ground set the shut down time for the BrgidgeA and BridgeB respectively when an over current is de-
tected (see Overcurrent Protection). The two current sensing inputs (SENSE
A
and SENSE
B
) s hould be c onnect-
ed to the sensing resistors w ith a trace length as short as possible in the layout. The sense resistors should be
non-i nductive resis tor s to minimize the di/dt transients across the r esistor. To increase noise immuni ty, unused
logic pins (except EN
A
and EN
B
) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see
pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Valu es for Typ ical Application
Figure 16. Typical Appli cation
C1100uF D11N4148
C2100nF D21N4148
CA1nF RA39KΩ
CB1nF RB39KΩ
CBOOT 220nF RENA 100KΩ
CP10nF RENB 100KΩ
CENA 5.6nF RP100Ω
CENB 5.6nF RSENSEA 0.6Ω
CREFA 68nF RSENSEB 0.6Ω
CREFB 68nF
OUT1
A
LOAD
A
LOAD
B
VREF
A
VREF
B
1
5
21
18
19
8
16
OUT2
A
GND
GND
GND
GND
RC
A
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
24VS
B
VCP
VBOOT
C
P
C
BOOT
R
P
D
2
D
1
C
1
C
2
SENSE
A
R
SENSEA
20
IN1
A
IN2
A
IN1
A
IN2
A
2
6
7
13
EN
A
EN
B
C
ENB
R
ENB
R
ENA
EN
A
EN
B
V
REFA
= 0-1V
V
REFB
= 0-1V
23
IN2
B
12
IN1
B
IN2
B
IN1
B
11
14
4
17
3
15
22
SENSE
B
R
SENSEB
C
A
R
A
10
C
REFA
C
REFB
C
ENA
RC
B
9
C
B
R
B
D02IN1343
17/22
L6227
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fi g. 17 and Fig. 18 are show n the approxi mate relation between th e output curr ent and the IC power dis sipa-
tion using PWM current control driving two loads, for two different driving types:
– One Full Bridge ON at a time (Fig.17) in which only one load at a t i me is energized.
– Two Full Bridges ON at the sam e time (Fig.18) in which two loads at the sam e time are energize d.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125°C maximum).
Figure 17. IC Power Dis sipation versu s Outp ut Current wi th One Full Bridge ON at a tim e.
Figure 18. IC P ower Dissipation versus Ou tput Curren t wi th Two Full Bridges ON at the same time.
THERMAL MANAGEMENT
In m ost applications the power dissi pation in the IC is the m ain f actor that sets the maximum current that can be de-
livered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besi des
the availab le space on the PCB, t he right package should be chose n considering the power di ssipati on. Heat sinki ng
can be achieved using copper on the PCB with proper area and t hickness. Figures 20, 21 and 22 show the Junction-
to- A m bie nt Ther m al Resistance values for the PowerS O3 6, PowerD IP24 and SO24 packages.
For instance, using a PowerS O package with copper slug soldered on a 1.5 mm copper thickness F R4 board
with 6cm
2
dissipati ng footpr int (cop per thicknes s of 35µ m), the R
th j-amb
is about 35° C/W. Fig. 19 shows mount-
ing methods for this pack age. Using a multi-layer board wi th vias to a ground plane, thermal impeda nce can be
reduced dow n to 15°C/W.
No PWM
fSW = 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
IA
IB
IOUT
IOUT
ONE FULL BRIDGE ON AT A TIME
PD [W]
IOUT [A]
0 0.25 0.5 0.75 1 1.25 1.5
0
2
4
6
8
10
No PWM
fSW = 30 kHz (slow decay)
Test Conditi ons:
Supply Voltage = 24 V
IA
IB
IOUT
IOUT
PD [W]
IOUT [A]
TWO FULL BRIDGES ON AT THE SAME TIME
0 0.25 0.5 0.75 1 1.25 1.5
0
2
4
6
8
10
L6227
18/22
Figure 19. Mou nting the PowerS O pack age.
Figure 20. Pow erSO36 Junction-Am bient thermal resistance versus on -board co pp er area.
Figure 21. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
Figure 22. SO24 Ju nction -Am bient thermal resistance ve rsus on -board co pp er area.
Sl ug soldered
to PC B with
dissipating area
Sl ug soldered
to PC B with
dissipating area
plus grou nd l ayer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
13
18
23
28
33
38
43
12345678910111213
Without Ground Layer
With Ground Layer
With Ground Layer+16 via
Holes
sq. cm
ºC / W
On-Board Copper Area
39
40
41
42
43
44
45
46
47
48
49
1 2 3 4 5 6 7 8 9 101112
Copper Area is on Bottom
Side
Copper Are a is on To p Side
sq . cm
ºC / W On-Board Copper Area
48
50
52
54
56
58
60
62
64
66
68
123456789101112
Copper Area is on Top Side
sq. cm
ºC / W On-Board Copper Area
19/22
L6227
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.60 0.141
a1 0.10 0.30 0.004 0.012
a2 3.30 0.130
a3 0 0.10 0 0.004
b 0.22 0.38 0.008 0.015
c 0.23 0.32 0.009 0.012
D (1) 15.80 16.00 0.622 0.630
D1 9.40 9.80 0.370 0.385
E 13.90 14.50 0.547 0.570
e 0.65 0.0256
e3 11.05 0.435
E1 (1) 10.90 11.10 0.429 0.437
E2 2.90 0.114
E3 5.80 6.20 0.228 0.244
E4 2.90 3.20 0.114 0.126
G 0 0.10 0 0.004
H 15.50 15.90 0.610 0.626
h 1.10 0.043
L 0.80 1.10 0.031 0.043
N10°(max.)
S8°(max.)
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
PowerSO36
e
a2 A
Ea1
PSO36MEC
DETAIL A
D
118
1936
E1
E2
h x 45˚
DETAIL A
lead
slug
a3
S
Gage Plane 0.35
L
DETAIL B
DETAIL B
(COPLANARITY)
GC
- C -
SEATING PLANE
e3
c
NN
⊕
M
0.12 AB
b
B
A
H
E3
D1
BOTTOM VIEW
OUTLINE AND
MECHANICAL DATA
L6227
20/22
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.320 0.170
A1 0.380 0.015
A2 3.300 0.130
B 0.410 0.460 0.510 0.016 0.018 0.020
B1 1.400 1.520 1.650 0.055 0.060 0.065
c 0.200 0.250 0.300 0.008 0.010 0.012
D 31.62 31.75 31.88 1.245 1.250 1.255
E 7.620 8.260 0.300 0.325
e 2.54 0.100
E1 6.350 6.600 6.860 0.250 0.260 0.270
e1 7.620 0.300
L 3.180 3.430 0.125 0.135
M 0˚ min, 15˚ max.
Powerdip 24
A1
B eB1
D
13
12
24
1
L
A
e1
A2
c
E1
SDIP24L
M
OUTLINE AND
MECHANICAL DAT A
21/22
L6227
OUTLINE AN D
M E CHANICAL DA T A
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
C 0.23 0.32 0.009 0.013
D
(1)
15.20 15.60 0.598 0.614
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0;75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0˚ (min.), 8˚ (max.)
ddd 0.10 0.004
(1) “ D” d i m e nsion does not i nclude mold f l ash, prot u s ion s or ga te
bur rs . Mo ld f lash, p rotus ion s or g ate b ur rs sh all no t exce ed
0.15mm per side.
SO24
0070769 C
Weight: 0.60gr
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no r esponsibility for the consequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise under any pat ent or paten t rights of STMi croelectronic s. Specifications m entioned in this publicati on are subject
to change without notice. This publication supersedes and replaces all information previous ly supplied. STMicroelectronics products ar e not
authorized f or use as c ri tical com ponents in lif e support devices or systems wi t hout exp ress writ ten approval of STM i croelectronics.
Th e ST logo is a register ed tradem ark of STM i croel ectronic s.
All o th er names are the propert y of their re spectiv e owners
© 2003 STMi croelect ronics - A l l ri ghts reserved
STMicroelectronics GROUP OF COMPANIES
Aus tralia - B el gium - B razil - Canada - China - C zech Rep ublic - Fi nl and - France - Ger m any - Hong Kong - I ndi a - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
22/22
L6227
