IDT74LVC1G32A 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE WITH 5 VOLT TOLERANT I/O DESCRIPTION: FEATURES: - - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.65mm pitch PSOP package Extended commercial range of - 40C to +85C VCC = 3.3V 0.3V, Normal Range VCC = 1.65V to 3.6V, Extended Range VCC = 2.5V 0.2V CMOS power levels (0.4 W typ. static) Rail-to-Rail output swing for increased noise margin All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion - - - - - - - - - This single 2-input positive-OR gate is built using advanced dual metal CMOS technology. The LVC1G32A is designed for 1.65V to 3.6V VCC operation and performs the Boolean function Y = A + B or Y = A * B in positive logic. The LVC1G32A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. APPLICATIONS: Drive Features for LVC1G32A: - High Output Drivers: 24mA - Reduced system switching noise * 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems FUNCTIONAL BLOCK DIAGRAM A PIN CONFIGURATION 1 4 B IDT74LVC1G32A Y A 1 B 2 SO5-1 5 V CC 4 Y 2 GN D 3 PSOP TOP VIEW FUNCTION TABLE PIN DESCRIPTION (1) Pin Names A, B Data Inputs A Inputs B Output Y Y Data Output H X H X H H L L L Description NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care EXTENDED COMMERCIAL TEMPERATURE RANGE APRIL 1999 1 c 1999 Integrated Device Technology, Inc. DSC-4761/- IDT74LVC1G32A 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol VTERM(2) Description Terminal Voltage with Respect to GND VTERM(3) TSTG Terminal Voltage with Respect to GND -0.5 to +6.5 V Storage Temperature - 65 to + 150 C IOUT DC Output Current - 50 to + 50 mA IIK IOK Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND - 50 mA ICC ISS Max. - 0.5 to + 6.5 CAPACITANCE (TA = +25C, f = 1.0MHZ) Unit V 100 Symbol CIN Parameter(1) Input Capacitance Conditions VIN = 0V Typ. 4.5 Max. 6 Unit pF COUT Output Capacitance I/O Port Capacitance VOUT = 0V 5.5 8 pF VIN = 0V 6.5 8 pF CI/O LVC 1G Link NOTE: 1. As applicable to the device type. mA LVC 1G Link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = - 40C To +85C Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ Input Leakage Current ICC Quiescent Power Supply Current Variation High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC VCC VCC VCC VCC VCC VCC Test Conditions = 1.65V to 1.95V = 2.3V to 2.7V = 2.7V to 3.6V = 1.65V to 1.95V = 2.3V to 2.7V = 2.7V to 3.6V = 3.6V VI = 0 to 5.5V VCC = 3.6V VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V One input at VCC - 0.6V, other inputs at VCC or GND Min. Typ.(1) Max. 0.65 x VCC -- -- 1.7 -- -- 2 -- -- -- -- 0.35 x VCC -- -- 0.7 -- -- 0.8 -- -- 5 Unit V V V A VI = 0 to 5.5V -- -- 10 A VIN = GND or VCC -- -- -- - 0.7 100 -- - 1.2 -- 10 V mV A 3.6 < Vin < 5.5V (2) -- -- 10 -- -- 500 A LVC 1G Link NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies to 3-state outputs in the disabled state only. c 1998 Integrated Device Technology, Inc. 2 DSC-123456 IDT74LVC1G32A 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC Test Conditions(1) = 1.65V to 3.6V IOH = - 0.1mA Min. VCC - 0.2 Max. -- VCC = 1.65V IOH = - 4mA 1.2 -- VCC = 2.3V IOH = - 8mA 1.7 -- VCC = 2.7V IOH = - 12mA 2.2 -- VCC = 3.0V VOL Output LOW Voltage 2.4 -- VCC = 3.0V IOH = - 24mA 2.2 -- VCC = 1.65V to 3.6V IOL = 0.1mA -- 0.2 VCC = 1.65V IOL = 4mA -- 0.45 VCC = 2.3V IOL = 8mA -- 0.7 VCC = 2.7V IOL = 12mA -- 0.4 VCC = 3.0V IOL = 24mA -- 0.55 Unit V V LVC 1G Link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to +85C. OPERATING CHARACTERISTICS, TA = 25oC Symbol CPD Parameter Power Dissipation Capacitance VCC = 2.5V0.2V VCC = 3.3V0.3V Typical -- Typical -- Typical -- Test Conditions CL = 0pF, f = 10Mhz SWITCHING CHARACTERISTICS Symbol Parameter tPLH Propagation Delay A or B to Y tPHL VCC = 1.8V0.15V Unit pF (1) VCC = 1.8V0.15V VCC = 2.5V0.2V Min. 1 Min. 1 Max. 10 NOTE: 1. See test circuits and waveforms. TA = - 40C to + 85C. 3 Max. 5.4 VCC = 2.7V Min. -- Max. 4.4 VCC = 3.3V0.3V Min. 1.5 Max. 3.8 Unit ns IDT74LVC1G32A 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY TEST CONDITIONS Symbol VLOAD VCC(1)= 3.3V0.3V VCC(1)= 2.7V VCC(2)= 2.5V0.2V 6 6 2 x Vcc Unit V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 V IH VT 0V SAME PHASE INPUT TRANSITION tPLH tPHL tPLH tPHL V OH VT V OL OUTPUT V IH VT 0V OPPOSITE PHASE INPUT TRANSITION pF LVC 1G Link LVC 1G Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC Open 500 (1, 2) V IN CONTROL INPUT GND tPZL V OUT Pulse Generator OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH D.U.T. 500 RT CL LVC 1G Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 0V V LOAD/2 V LOAD/2 VT V OL + V LZ V OL tPHZ VT V OH V OH -V LZ 0V 0V LVC 1G Link SET-UP, HOLD, AND RELEASE TIMES Switch VLOAD DATA INPUT tSU tH TIMING INPUT GND tREM ASYNCHRONOUS CONTROL Open SYNCHRONOUS CONTROL LVC 1G Link PULSE WIDTH tSU tH V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V LVC 1G Link LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE tPLZ V IH VT NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests DISABLE ENABLE VT LVC 1G Link 4 IDT74LVC1G32A 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE 1.8V 0.15V TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC (1) = 1.8V 0.15V 2 x Vcc Unit V VIH Vcc V VT VCC / 2 V VLZ 150 mV VHZ 150 mV CL 30 pF V IH VT 0V SAM E PHAS E INPUT TRANSITION tPLH t PHL t PLH t PHL V OH VT V OL O UTPUT V IH VT 0V O PPO SITE PHASE INPUT TRANSITION LVC 1G Link LVC 1G Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 1000 (1) V IN CO NTRO L INPUT GND t PZL D.U.T. RT CL O UTPUT SW ITCH NO RM ALLY CLOSED LO W t PZH O UTPUT SW ITCH NO RM ALLY OP EN HIGH 1000 t PLZ 0V V LOAD/2 V LOAD/2 VT V OL + V LZ V OL t PHZ V OH V OH - V HZ VT 0V 0V NOTE: LVC 1G Link 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. LVC 1G Link DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests V IH VT V OUT Pulse G enerator DISABLE ENABLE O pen Switch VLOAD ASYNCHRONOUS CO NTRO L V IH VT 0V V IH VT 0V V IH VT 0V SYNC HRONOUS CO NTRO L V IH VT 0V DATA INPUT tSU tH TIM ING INPUT GND t REM Open LVC 1G Link PULSE WIDTH tSU tH LVC 1G Link LO W -H IG H -LO W PULSE VT tW HIGH -LOW -HIGH PULSE VT LVC 1G Link 5 IDT74LVC1G32A 3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX Temp. Range LVC XXX XX Device Type Package DY Plastic Small Outline Package (SO5-1) 1G32A Single 2-Input Positive-OR Gate with 5 Volt Tolerant I/O, 24m A 74 - 40C to +85C PICOGATE-LOGIC (DY) PACKAGES Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDT's 5-pin PSOP (DY) packaged devices utilize a three-symbol name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol denotes a wafer fab/assembly site code for internal tracking. EXAMPLES: 1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A. 2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04. PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES TECHNOLOGY ALVC ALVCH LVC LVCH(1) CODE G J L FUNCTION 00 02 04 U04 06 07 08 14 32 79 86 125 126 132 CODE A B C D T V E F G R H M N Y NOTE: 1. Code to be determined. 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