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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC1G32A
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
APRIL 1999
1999 Integrated Device Technology, Inc. DSC-4761/-c
IDT74LVC1G32A
EXTENDED COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
This single 2-input positive-OR gate is built using advanced dual metal
CMOS technology. The LVC1G32A is designed for 1.65V to 3.6V VCC
operation and performs the Boolean function Y = A + B or Y = A • B in positive
logic.
The LVC1G32A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
FUNCTIONAL BLOCK DIAGRAM
PSOP
TOP VIEW
3.3V CMOS
SINGLE 2-INPUT
POSITIVE-OR GATE
WITH 5 VOLT TOLERANT I/O
FEATURES:
– 0.5 MICRON CMOS Technology
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.65mm pitch PSOP package
– Extended commercial range of – 40°C to +85°C
–V
CC = 3.3V ±0.3V, Normal Range
–V
CC = 1.65V to 3.6V, Extended Range
–V
CC = 2.5V ±0.2V
– CMOS power levels (0.4µW typ. static)
– Rail-to-Rail output swing for increased noise margin
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
A
B
1
2
Y
4
GND
2
34
5
1
B
VCC
A
Y
SO5-1
PIN DESCRIPTION
Pin Names Description
A, B Data Inputs
Y Data Output
FUNCTION TABLE (1)
Inputs Output
ABY
HXH
XHH
LLL
NOTE:
1. H
=
HIGH V olta
g
e Level
L
=
LOW Volta
g
e Level
X
=
Don’t Ca re
Drive Features for LVC1G32A:
– High Output Drivers: ±24mA
– Reduced system switching noise
PIN CONFIGURATION
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC1G32A
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
1998 Integrated Device Technology, Inc. DSC-123456c
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Description Max. Unit
V
TERM(2) Terminal Voltage with Respect to GND – 0.5 to + 6.5 V
VTERM(3) Terminal Voltage with Respect to GND –0.5 to +6.5 V
TSTG Storage Temperature – 65 to + 150 °C
IOUT DC Output Current – 50 to + 50 mA
IIK
IOK Continuous Clamp Current,
VI < 0 or VO < 0 – 50 mA
ICC
ISS Continuous Current through
each VCC or GND ±100 mA
LVC 1G Link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other c onditions above t hose indicated in the operational s ections
of this specification is not implied. Exposure to absolute maximum
rating condit i ons for extended periods may affec t reliability.
2. VCC terminals.
3. All terminals except VCC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C To +85°C
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Level VCC = 1.65V to 1.95V 0.65 x VCC ——V
V
CC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
VIL Input LOW Voltage Level VCC = 1.65V to 1.95V — — 0.35 x VCC
VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH
IIL Input Leakage Current VCC = 3.6V VI = 0 to 5.5V — — ±5 µA
IOZH
IOZL High Impedance Output Current
(3-State Output pins) VCC = 3.6V VI = 0 to 5.5V — — ±10 µA
VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V
VHInput Hysteresis VCC = 3.3V — 100 — mV
ICCL
ICCH Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC ——10µA
I
CCZ 3.6 < Vin < 5.5V (2) ——10
∆I
CC Quiescent Power Supply
Current Variation One input at VCC − 0.6V,
other inputs at VCC or GND — — 500 µA
LVC 1G Lin
k
NOTE:
1. Typical v al ues are at VCC = 3.3V, +25°C am bi ent .
2. This applies to 3-st ate outputs in the di s abl ed state onl y.
CAPACITANCE (TA = +25°C, f = 1.0MH Z)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 4.5 6 pF
COUT Output
Capacitance VOUT = 0V 5.5 8 pF
CI/O I/O Port
Capacitance VIN = 0V 6.5 8 pF
LVC 1G Link
NOTE:
1. As appl i cable to the devi ce type.
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC1G32A
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions(1) Min. Max. Unit
VOH Output HIGH Voltage VCC = 1.65V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
VCC = 1.65V IOH = – 4mA 1.2 —
VCC = 2.3V IOH = – 8mA 1.7 —
VCC = 2.7V IOH = – 12mA 2.2 —
VCC = 3.0V 2.4 —
VCC = 3.0V IOH = – 24mA 2.2 —
VOL Output LOW Voltage VCC = 1.65V to 3.6V IOL = 0.1mA — 0.2 V
VCC = 1.65V IOL = 4mA — 0.45
VCC = 2.3V IOL = 8mA — 0.7
VCC = 2.7V IOL = 12mA — 0.4
VCC = 3.0V IOL = 24mA — 0.55 LVC 1G Link
NOTE:
1. VIH and VIL must be within the min. or max . range shown in the DC ELECTRICAL CHARACTERI STICS OVER OPERATING RANGE table for the
appropriate VCC range. T A = – 40° C t o +85° C.
OPERATING CHARACTERISTICS, TA = 25oC
VCC = 1.8V±0.15V VCC = 2.5V±0.2V VCC = 3.3V±0.3V
Symbol Parameter Test Conditions Typical Typical Typical Unit
CPD Power Dissipation Capacitance CL = 0pF, f = 10Mhz — — — pF
SWITCHING CHARACTERISTICS (1)
VCC = 1.8V±0.15V VCC = 2.5V±0.2V VCC = 2.7V VCC = 3.3V±0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPLH
tPHL Propagation Delay
A or B to Y 1 10 1 5.4 — 4.4 1.5 3.8 ns
NOTE:
1. See test ci rcuits and waveforms. TA = – 40°C t o + 85° C.
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC1G32A
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
Open
VLOAD
GND
VCC
Pulse
Generator D.U.T.
500Ω
500Ω
CL
RT
VIN VOUT
(1, 2)
LVC 1G Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
LVC 1G Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
0V
VOL +VLZ
VOH
VT
VT
tPZL
VLOAD/2 VLOAD/2
VIH
VT
VOL
VOH -VLZ
LVC 1G Link
LVC 1G Link
LVC 1G Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
PULSE WIDTH
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
VLOAD 662 x VccV
V
IH 2.7 2.7 Vcc V
VT1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
CL50 50 30 pF
LVC 1G Link
Test Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High GND
All Other tests Open LVC 1G Lin
k
DEFINITIONS:
CL= Load capacitanc e: i ncludes j i g and probe capac i t ance.
RT = Termination resistance: should be equal to Z OUT of the Puls e
Generator.
NOTES:
1. Puls e Generator f or A l l Pulses : Rate ≤ 10MHz ; tF ≤ 2.5ns ; tR ≤ 2.5ns.
2. Puls e Generator f or A l l Pulses : Rate ≤ 10MHz ; tF ≤ 2ns; t R ≤ 2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC1G32A
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
Open
VLOAD
GND
VCC
Pulse
Generator
1000Ω
1000Ω
CL
RT
VIN VOUT
(1)
LVC 1G Link
DATA
INPUT 0V
0V
0V
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU tH
tSU tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
VOH
VOL
tPLH tPHL
tPHL
tPLH
OUTPUT
VIH
VT
VT
VIH
VT
CONTROL
INPUT tPLZ 0V
OUTPUT
NORMALLY
LOW tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE DISABLE
SWITCH
OPEN
tPHZ
VT
VT
tPZL
VLOAD/2
VIH
VT
0V
VOL + VLZ
VOH
VLOAD/2
VOL
LVC 1 G Link
VOH – VHZ
LVC 1 G Link
LVC 1 G Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
VT
LVC 1 G Link
D.U.T.
TEST CONDITIONS PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
PULSE WIDTH
1.8V ± 0.15V TEST CIRCUITS AND WAVEFORMS
Symbol VCC (1) = 1.8V ± 0.15V Unit
VLOAD 2 x Vcc V
VIH Vcc V
VTVCC / 2 V
VLZ 150 mV
VHZ 150 mV
CL30 pF
LVC 1G Lin
k
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistanc e: should be equal to ZOUT of the Pulse
Generator.
NOTE:
1. Pul se Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Test Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High GND
All Other tests Open LVC 1G Lin
k
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EXTENDED COMMERCIAL TEMPERATURE RANGE
IDT74LVC1G32A
3.3V CMOS SINGLE 2-INPUT POSITIVE-OR GATE
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
IDT XX LVC XXX XX
Package
Device Type
Temp. Range
DY
74
Plastic Sm all Ou tline Package (SO5-1)
Single 2-Input Positive-OR G ate w ith 5 Volt Tolerant I/O, ±24m A
– 40°C to +85°C
1G32A
PICOGATE-LOGIC (DY) PACKAGES
Due to their small size, PicoGate-Logic packages require more complex symbolization guidelines. IDT’s 5-pin PSOP (DY) packaged devices utilize a three-symbol
name rule. The first symbol denotes device technology, the second symbol denotes device function, and the third symbol denotes a wafer fab/assembly site code for
internal tracking.
EXAMPLES:
1. A PicoGate-Logic device with package code LR* is an IDT74LVC1G79A.
2. A PicoGate-Logic device with package code GC* is an IDT74ALVC1G04.
PICOGATE-LOGIC (DY) PACKAGE SYMBOLIZATION GUIDELINES
NOTE:
1. Code to be determ i ned.
TECHNOLOGY CODE
ALVC G
ALVCH J
LVC L
LVCH(1)
FUNCTION CODE
00 A
02 B
04 C
U04 D
06 T
07 V
08 E
14 F
32 G
79 R
86 H
125 M
126 N
132 Y
