1
®CA3260, CA3260A
4MHz, BiMOS Operational Amplifier with
MOSFET Input/CMOS Output
CA3260A and CA3260 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA3260 series
circuits are dual versions of the popular CA3160 series.
Gate protected P-Channel MOSFET (PMOS) transistors are
used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common mode input voltage capability
down to 0.5V below the negative supply terminal, an
important attribute in single supply applications.
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA3260 Series circuits operate at supply voltages
ranging from 4V to 16V, or ±2V to ±8V when using split
supplies. The CA3260A offers superior input characteristics
over those of the CA3260.
Features
• MOSFET Input Stage provides
- Very High ZI = 1.5TΩ (1.5 x 1012Ω) (Typ)
- Very Low II . . . . . . . . . . . . 5pA (Typ) at 15V Operation
. . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation
• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be Swung 0.5V
Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(Or Both) Supply Rails
• Pb-Free Available (RoHS Compliant)
Applications
• Ground Refere nced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• Ideal Interface with Digital CMOS
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g. Follower for Single Supply D/A
Converter)
• Voltage Regulators (Permits Control of Output V oltage
Down to 0V)
• Wien Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers
Pinout
CA3260, CA3260A
(8 LD PDIP)
TOP VIEW
Ordering Information
PART
NUMBER PART
MARKING TEMP.
RANGE (°C) PACKAGE PKG.
DWG. #
CA3260E CA3260E -55 to +125 8 Ld PDIP E8.3
CA3260EZ
(Note) CA3260EZ -55 to +125 8 Ld PDIP*
(Pb-free) E8.3
CA3260AE CA3260AE -55 to +125 8 Ld PDIP E8.3
CA3260AEZ
(Note) 3260AEZ -55 to +125 8 Ld PDIP*
(Pb-free) E8.3
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020. NON INV. INPUT (A)
V-
1
2
3
8
7
6
5
V+
OUTPUT (B)
INV. INPUT (B)
NON INV. INPUT (B)
OUTPUT (A)
A
4
B
+-
+
-
INV. INPUT (A)
Data Sheet December 10, 2009 FN1266.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005, 2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN1266.7
December 10, 2009
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (V+ to V-) . . . . . . . . . . . . . . . . . . . . . . . . . . 16V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Thermal Resistance (Typical, Note 2) θJA (°C/W) θJC (°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . 100 N/A
Maximum Junction Temperature (Plastic Package) . . . . . . .+150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = +25°C, Typical Values Intended Only for Design Guidance.
PARAMETER SYMBOL TEST CONDITIONS
TYPICAL VALUES
UNITSCA3260A CA3260
Input Resistance RIVS = ±7.5V 1.5 1.5 TΩ
Input Capacitance CIf = 1MHz, VS = ±7.5V 4.3 4.3 pF
Unity Gain Crossover Frequency fTVS = ±7.5V 4 4 MHz
Slew Rate SR VS = ±7.5V 10 10 V/μs
Transient Response Rise Time trCL = 25pF, RL = 2kΩ, AV = +1,
VS = ±7.5V
0.09 0.09 µs
Overshoot OS 10 10 %
Settling Time (to <0.1%, VIN = 4VP-P)t
SCL = 25pF, RL = 2kΩ, AV = +1,
VS = ±7.5V
1.8 1.8 μs
Input Offset Voltage VIO V+ = 5V, V- = 0V 2 6 mV
Input Offset Current IIO V+ = 5V, V- = 0V 0.1 0.1 pA
Input Current IIV+ = 5V, V- = 0V 2 2 pA
Common Mode Rejection Ratio CMRR V+ = 5V, V- = 0V 70 60 dB
Large Signal Voltage Gain AOL VO = 4VP-P, RL = 20kΩ,
V+ = 5V, V- = 0V 100 100 kV/V
100 100 dB
Common Mode Input Voltage Range VICR V+ = 5V, V- = 0V 0 to 2.5 0 to 2.5 V
Supply Current I+ VO = 5V, RL = ∞, V+ = 5V, V- = 0V 1 1 mA
VO = 2.5V, RL = ∞, V+ = 5V, V- = 0V 1.2 1.2 mA
Power Supply Rejection Ratio PSRR ΔVIO/ΔV+, V+ = 5V, V- = 0V 200 200 µV/V
Electrical Specifications For Each Amplifier at TA = +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified.
PARAMETER SYMBOL TEST
CONDITIONS
CA3260A CA3260
UNITSMIN TYP MAX MIN TYP MAX
Input Offset Voltage |VIO|V
S = ±7.5V - 2 5 - 6 15 mV
Input Offset Current |IIO|V
S = ±7.5V - 0.5 20 - 0.5 30 pA
Input Current IIVS = ±7.5V - 5 30 - 5 50 pA
Large Signal Voltage Gain AOL VO = 10VP-P,
RL = 10kΩ
50 320 - 50 320 - kV/V
94 110 - 94 110 - dB
Common Mode Rejection Ratio CMRR 80 95 - 70 90 - dB
CA3260, CA3260A
3FN1266.7
December 10, 2009
Schematic Diagram
Common Mode Input Voltage
Range VlCR 0-0.5 to
12 10 0 -0.5 to
12 10 V
Power Supply Rejection Ratio PSRR ΔVIO/ΔV+
V+ = 17.5V - 32 150 - 32 320 µV/V
Maximum Output Voltage VOM+R
L = 10kΩ11 13.3 - 11 13.3 - V
VOM- - 0.002 0.01 - 0.002 0.01 V
VOM+R
L = ∞14.99 15 - 14.99 15 - V
VOM- - 00.01- 00.01V
Maximum Output Current IOM+ Source VO = 0V 12 22 45 12 22 45 mA
IOM- Sink VO = 15V 12 20 45 12 20 45 mA
Total Supply Current I+ RL = ∞
VO (Amplifier A) = 7.5V
VO (Amplifier B) = 7.5V
- 9 15.5 - 9 15.5 mA
VO (Amplifier A) = 0V
VO (Amplifier B) = 0V
-1.23 -1.23mA
VO (Amplifier A) = 0V
VO (Amplifier B) = 7.5V
-58.5-58.5mA
Input Offset Voltage
Temperature Drift ΔVIO/ΔT-6--8-µV/°C
Crosstalk f = 1kHz - 120 - - 120 - dB
Electrical Specifications For Each Amplifier at TA = +25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified. (Continued)
PARAMETER SYMBOL TEST
CONDITIONS
CA3260A CA3260
UNITSMIN TYP MAX MIN TYP MAX
R6
200kR7
300k
Q12
Q11 Q10
D2D3
D4
D1
Q1Q2
Q6
R4
1k
R2
1k
R1
1k
R3
1k
Q13
Q14
Q3Q4
C1
30pF
R5
2K
Q7
Q9
3 2 1
Q5
Q8
AMPLIFIER A
R13
200k
R14
300Ω
Q26
Q25
Q24
D7
D6
D5D8
Q15
Q16
Q20
R11
1k
R9
1k R8
1k
R10
1kQ27 Q28
Q17
Q18
C2
30pF
R12
2k
Q21
Q23
567
Q19
Q22
AMPLIFIER B
4
8V+
CA3260, CA3260A
4
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent righ t s of Int ersi l or it s sub sidi ari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN1266.7
December 10, 2009
CA3260, CA3260A
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed 0.010
inch (0.25mm).
6. E and are measured with the leads constrained to be
perpendicular to datum .
7. eB and eC are measured at the lead tips with the leads
unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 -5.33 4
A1 0.015 -0.39 -4
A2 0.115 0.195 2.93 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C0.008 0.014 0.204 0.355 -
D0.355 0.400 9.01 10.16 5
D1 0.005 -0.13 -5
E0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB-0.430 -10.92 7
L0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
