Wireless Sense & Control
Data Sheet
Revision 1.1, 2010-06-18
TDA7210V
ASK/FSK Single Conversion Receiver
Edition 2010-06-18
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TDA7210V
Data Sheet 3 Revision 1.1, 2010-06-18
Trademarks of Infineon Technologies AG
A-GOLD™, BlueMoon™, COMNEON™, CONVERGATE™, COSIC™, C166™, CROSSAVE™, CanPAK™,
CIPOS™, CoolMOS™, CoolSET™, CONVERPATH™, CORECONTROL™, DAVE™, DUALFALC™, DUSLIC™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, E-GOLD™, EiceDRIVER™,
EUPEC™, ELIC™, EPIC™, FALC™, FCOS™, FLEXISLIC™, GEMINAX™, GOLDMOS™, HITFET™,
HybridPACK™, INCA™, ISAC™, ISOFACE™, IsoPACK™, IWORX™, M-GOLD™, MIPAQ™, ModSTACK™,
MUSLIC™, my-d™, NovalithIC™, OCTALFALC™, OCTAT™, OmniTune™, OmniVia™, OptiMOS™,
OPTIVERSE™, ORIGA™, PROFET™, PRO-SIL™, PrimePACK™, QUADFALC™, RASIC™, ReverSave™,
SatRIC™, SCEPTRE™, SCOUT™, S-GOLD™, SensoNor™, SEROCCO™, SICOFI™, SIEGET™,
SINDRION™, SLIC™, SMARTi™, SmartLEWIS™, SMINT™, SOCRATES™, TEMPFET™, thinQ!™,
TrueNTRY™, TriCore™, TRENCHSTOP™, VINAX™, VINETIC™, VIONTIC™, WildPass™, X-GOLD™, XMM™,
X-PMU™, XPOSYS™, XWAY™.
Other Trademarks
AMBA™, ARM™, MULTI-ICE™, PRIMECELL™, REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is
licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum.
COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of
Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium.
HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION.
MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of
Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc.,
USA. muRata™ of MURATA MANUFACTURING CO. OmniVision™ of OmniVision Technologies, Inc.
Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of
Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™
of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™
of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™,
PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™,
WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.
Last Trademarks Update 2009-10-19
TDA7210V ASK/FSK Single Conversion Receiver
Revision History: 2010-06-18, Revision 1.1
Previous Revision: 1.0
Page Subjects (major changes since last revision)
29 Explanation regarding the Absolute Maximum Ratings
TDA7210V
Table of Contents
Data Sheet 4 Revision 1.1, 2010-06-18
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.9 Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.1 FSK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1.3 AC/DC Characteristics at TAMB = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.4 AC/DC Characteristics at TAMB = -40 to 85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Customer Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 Customer Test Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table of Contents
TDA7210V
Product Description
Data Sheet 5 Revision 1.1, 2010-06-18
1 Product Description
1.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency
bands 810 to 870 MHz and 400 to 440 MHz. The IC offers a high level of integration and needs only a few external
components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a
PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data
comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
1.2 Features
Main features:
• Selectable frequency ranges 810-870 MHz and 400-440 MHz
• Low supply current (at 434 MHz Is = 5.7 mA typ. FSK mode, 5.0 mA typ. ASK mode)
• Power down mode with very low supply current (50 nA typ.)
• FSK and ASK demodulation capability
• RF input sensitivity ASK/FSK typ. –115 dBm/–112 dBm @ 1 kbit/s RF=434 MHz
• RF input sensitivity ASK/FSK typ. –111 dBm/–111 dBm @ 1 kbit/s RF=868 MHz
• Fully integrated VCO and PLL Synthesiser
• Limiter with RSSI generation, operating at 10.7 MHz
• Selectable reference frequency
• 2nd order low pass data filter with external capacitors
• Data slicer with self-adjusting threshold
• Supply voltage range 5 V ±10%
1.3 Application
The TDA7210V is suitable for any kind of remote control system especially for low data rate wireless applications
where low current consumption is important and where the line-of-sight limitation is driving the infra-red to RF
replacement.
Main applications:
• Home automation
- Lighting Control
- Curtain, Roller Blind Control
- Air Condition Control
• Set-top-boxes
• Garage Door Openers
• Alarm Systems
• Wireless Toys
• Remote Keyless Entry Systems
TDA7210V
Product Description
Data Sheet 6 Revision 1.1, 2010-06-18
1.4 Ordering Information
1.5 Package Outlines
Figure 1 Package
Figure 2 VQFN-32 Package Outlines
Table 1 Ordering Info
Type Ordering Code Package1)
1) Samples available on tape and reel.
TDA7210V SP000698080 VQFN-32
TDA7210V
Functional Description
Data Sheet 7 Revision 1.1, 2010-06-18
2 Functional Description
2.1 Pin Configuration
Figure 3 Pin Configuration TDA7210V
LNI
TAGC
AGND1
LNO
VCC1
MI
MIX
AGND2
FSEL
IFO
TDA7210V
27
28
29
30
16
15
14
13
12
26 25 24 23 22 21
123456
PDWN
CRST2
N.C.
CRST1
LIM
CSEL
MSEL
VDD
DGND
PDO
DATA
3VOUT
THRES
FFB
GNDRF3
OPP
SLN
SLP
VCC2
GNDRF1 GNDRF2
789
20 19 18
31
32 11
LIMX
17
10
TDA7210V
Functional Description
Data Sheet 8 Revision 1.1, 2010-06-18
2.2 Pin Definition and Function
In the subsequent table the internal circuits connected to the pins of the device are shown. ESD-protection circuits
are omitted to ease reading.
Table 2 Pin Definition and Function
Pin No. Symbol Equivalent I/O-Schematic Function
1 LNI LNA Input
2 TAGC AGC Time Constant Control
3 AGND1 Analogue Ground Return
4 LNO LNA Output
57uA
4k
1k
1
500uA
1k
4.2uA
1.5uA
1.7V
4.3V
2
4
1k
5V
TDA7210V
Functional Description
Data Sheet 9 Revision 1.1, 2010-06-18
5 VCC1 5 V Supply
6 MI Mixer Input
7 MIX Complementary Mixer Input
8 AGND2 Analogue Ground Return
9 FSEL 868/434 MHz Operating
Frequency Selector
10 IFO 10.7 MHz IF Mixer Output
11 GNDRF2 Internal GND Plane connected
to RF-GND
12 DGND Digital Ground Return
13 VDD 5 V Supply Digital
Table 2 Pin Definition and Function (cont’d)
Pin No. Symbol Equivalent I/O-Schematic Function
6
1.7V
7
400uA
2k 2k
750
2k
9
1.2V
2.2V
4.5k
60
10
300uA
TDA7210V
Functional Description
Data Sheet 10 Revision 1.1, 2010-06-18
14 MSEL ASK/FSK Modulation Format
Selector
15 CSEL 6.xx or 13.xx MHz Quartz
Selector
16 LIM Limiter Input
17 LIMX Complementary Limiter Input
18 SLP Data Slicer Positive Input
Table 2 Pin Definition and Function (cont’d)
Pin No. Symbol Equivalent I/O-Schematic Function
1.2V
3.6k
14
1.2V
80k
15
330
15k
15k
17
16
75uA
18
80µA
15uA
3k
100
TDA7210V
Functional Description
Data Sheet 11 Revision 1.1, 2010-06-18
19 SLN Data Slicer Negative Input
20 OPP OpAmp Noninverting Input
21 GNDRF3 Internal GND Plane connected
to RF-GND
22 FFB Data Filter Feedback Pin
23 THRES AGC Threshold Input
24 3VOUT 3 V Reference Output
Table 2 Pin Definition and Function (cont’d)
Pin No. Symbol Equivalent I/O-Schematic Function
10k
5uA
19
20
200
5uA
100k
5uA
22
10k
5uA
23
3.1V
24
20kΩ
TDA7210V
Functional Description
Data Sheet 12 Revision 1.1, 2010-06-18
25 DATA Data Output
26 PDO Peak Detector Output
27 PDWN Power Down Input
28 CRST2 External Crystal Connector 2
29 N.C. Not connected
Table 2 Pin Definition and Function (cont’d)
Pin No. Symbol Equivalent I/O-Schematic Function
25
500
40k
26
200
27
220k
220k
4.15V
50uA
28
TDA7210V
Functional Description
Data Sheet 13 Revision 1.1, 2010-06-18
2.3 Functional Block Diagram
Figure 4 Main Block Diagram TDA7210V
2.4 Functional Blocks
30 CRST1 External Crystal Connector 1
31 VCC2 5 V Supply Analogue
32 GNDRF1 Internal GND Plane connected
to RF-GND
Table 2 Pin Definition and Function (cont’d)
Pin No. Symbol Equivalent I/O-Schematic Function
4.15V
50uA
30
: 1 / 2 VCO : 128 / 64 Φ
DET CRYSTAL
OSC
Crystal
PDWN
FSEL
Loop
Filter
Bandgap
Reference
LNA
RF
TAGC
VDD
VCC1
VCC2
GNDRF2
GNDRF3
AGC
Reference
THRES
3VOUT
FSK
PLL Demod
OTA
LNI
DGND
-
+
MIXLNO MI OPPFFB SLP
VCC
LIM LIMX
IF
Filter
IFO
MSEL
LIMITER
4671016 17 22 20 18
26
23
24
1
2
13
12
5,31 11,21
14
930 28 27
-
+
ASK
FSK
OP
+
-
UREF
DETECTOR
PEAK
TDA 7210V
CSEL
15
SLN
DATA
PDO
SLICER
+
-
25
19
GNDRF1 32
(LNA, RF)
AGND1
AGND2
3,8
(RF)
TDA7210V
Functional Description
Data Sheet 14 Revision 1.1, 2010-06-18
2.4.1 Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 20 to 27 dB (depending on the matching). The gain
figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO
(Pin 4) and the Mixer Inputs MI and MIX (Pins 6 and 7). The noise figure of the LNA is approximately 3 dB, the
current consumption is 500 μA. The gain can be reduced by approximately 18 dB. The switching point of this AGC
action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is
compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI
level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be
generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable
3 V output generated from the internal bandgap voltage and the THRES pin as described in Chapter 3.1. The time
constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 2) and should be
chosen along with the appropriate threshold voltage according to the intended operating case and interference
scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is
described in Chapter 3.1.
2.4.2 Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 400-440 MHz/810-870 MHz to
the intermediate frequency (IF) at 10.7 MHz with a voltage gain of approximately 24 dB (depending on the
matching) by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced
only single-ended, the unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low
pass filter with a corner frequency of 20 MHz in order to suppress RF signals to appear at the IF output (IFO pin).
The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330
to facilitate interfacing the pin directly to a standard 10.7 MHz ceramic filter without additional matching circuitry.
2.4.3 PLL Synthesizer
The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with
charge pump and a loop filter and is fully implemented on-chip. The VCO is including on-chip spiral inductors and
varactor diodes. It’s nominal centre frequency is 840 MHz, the operating range guaranteed over the temperature
range specified is 820 to 860 MHz. Depending on whether high- or low-side injection of the local oscillator is used
the receive frequency ranges are 810 to 840 MHz and 840 to 870 MHz or 400 to 420 MHz and 420 to 440 MHz
(see also Chapter 3.4). No additional external components are necessary.
The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. In case of
operation in the 400 to 440 MHz range, the signal is divided by two before it is fed to the mixer. This is controlled
by the selection pin FSEL (Pin 9) as described in the following table. The overall division ratio of the divider chain
can be selected to be either 128 or 64, depending on the frequency of the reference oscillator quartz (see below
and Chapter 3.4). The loop filter is also realised fully on-chip.
2.4.4 Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 6 and 13 MHz range as the
overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 15) pin according to the
following table.
Table 3 FSEL Pin Operating States
FSEL RF Frequency
Open 400-440 MHz
Shorted to ground 810-870 MHz
TDA7210V
Functional Description
Data Sheet 15 Revision 1.1, 2010-06-18
The calculation of the value of the necessary quartz load capacitance is shown in Chapter 3.3, the quartz
frequency calculation is explained in Chapter 3.4.
2.4.5 Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a
bandpass-characteristic centred around 10.7 MHz. It has a typical input impedance of 330 to allow for easy
interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator
(RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen
in Figure 6. This signal is used to demodulate ASK-modulated receive signals in the subsequent baseband
circuitry. The RSSI output is applied to the modulation format switch, to the Peak Detector input and to the AGC
circuitry.
In order to demodulate ASK signals the MSEL pin has to be left open as described in the next chapter.
2.4.6 FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter
output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO.
The demodulator gain is typically 200 μV/kHz. The passive loop filter output that is comprised fully on chip is fed
to both the VCO and the modulation format switch described in more detail below. This signal is representing the
demodulated signal with high frequencies applied to the demodulator demodulated to logic ones and low
frequencies demodulated to logic zeroes. Please note that due to this behaviour a sign inversion of the data occurs
in case of high-side injection of the local oscillator at receive frequencies below 840 or 420 MHz, respectively.
The modulation format switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL
pin (Pin 14) as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits.
The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset produced by the demodulator
in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle
of operation of the switch are described in Chapter 3.6.
The demodulator circuit is switched off in case of reception of ASK signals.
2.4.7 Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100 kHz used as a voltage follower and two 100 k on-
chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection
of the capacitor values is described in Chapter 3.6.
Table 4 CSEL Pin Operating States
CSEL Crystal Frequency
Open 6.xx MHz
Shorted to ground 13.xx MHz
Table 5 MSEL Pin Operating States
MSEL Modulation Format
Open ASK
Shorted to ground FSK
TDA7210V
Functional Description
Data Sheet 16 Revision 1.1, 2010-06-18
2.4.8 Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of
up to 100 kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local
oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels)
for sbsequent circuits. The self-adjusting threshold on pin 19 its generated by RC-term or peak detector depending
on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in
Chapter 3.5.
2.4.9 Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An
external RC network is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output
is connected to the PDO pin (Pin 26). This output can be used as an indicator for the received signal strength to
use in wake-up circuits and as a reference for the data slicer in ASK mode. Note that the RSSI level is also output
in case of FSK mode.
2.4.10 Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode
is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following
table. The supply current drawn in this case is typically 50 nA.
Table 6 PDWN Pin Operating States
PDWN Operating State
Open or tied to ground Powerdown Mode
Tied to VCC Receiver On
TDA7210V
Applications
Data Sheet 17 Revision 1.1, 2010-06-18
3 Applications
3.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
Figure 5 LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to
compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold
voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately
0.8 and 2.8 V to provide a switching point within the receive signal dynamic range.
This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a
voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3 V output generated from
the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres,
the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 2). Otherwise, the OTA
generates a negative current. These currents do not have the same values in order to achieve a fast-attack and
slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain
control voltage.
2
LNA
RSSI (0.8 - 2.8V)
VCC
Gain control
voltage
OTA
+3.1 V
Iload
RSSI > Uthreshold: Iload=4.2µA
RSSI < Uthreshold: Iload= -1.5µA
UC
C
Uc:< 2.6V : Gain high
Uc:> 2.6V : Gain low
Ucmax= VCC - 0.7V
Ucmin = 1.67V
R1 R2
Pins: 24 23
Uthreshold
20kΩ
TDA7210V
Applications
Data Sheet 18 Revision 1.1, 2010-06-18
Figure 6 RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the
optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8 V is apparently
a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50 µA, but that the
THRES pin input current is only in the region of 40 nA. As the current drawn out of the 3VOUT pin is directly related
to the receiver power consumption, the power divider resistors should have high impedance values. The sum of
R1 and R2 has to be 600 k in order to yield 3 V at the 3VOUT pin. R1 can thus be chosen as 240 k, R2 as
360 k to yield an overall 3VOUT output current of 5 µA1) and a threshold voltage of 1.8 V.
Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES
pin to a fixed voltage. In order to achieve always high gain mode operation, a voltage of at least 2.9 V or
higher shall be applied to the THRES pin, such as a short to the 3VOUT pin. In order to achieve low gain
mode operation a voltage lower than 0.7 V (depending on the matching and IF-filter) shall be applied to the
THRES, such as a short to ground.
As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due
to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As
the charging and discharging currents are not equal two different time constants will result. The time constant
corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to
measurements performed at Infineon the capacitor value should be higher than 47 nF.
1) Note the 20 k resistor in series with the 3.1 V internal voltage source
LNA always
in high gain mode
0
0.5
1
1.5
2
2.5
3
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30
Input Level at LNA Input [dBm]
UTHRES Voltage Range
RSSI Level Range LNA always
in low gain mode
RSSI Level
TDA7210V
Applications
Data Sheet 19 Revision 1.1, 2010-06-18
3.2 Data Filter Design
Utilising the on-board voltage follower and the two 100 k on-chip resistors a 2nd order Sallen-Key low pass data
filter can be constructed by adding 2 external capacitors between pins 18 (SLP) and 22 (FFB) and to pin 20 (OPP)
as depicted in the following figure and described in the following formulas1).
Figure 7 Data Filter Design
(1)
(2)
with
(3)
the quality factor of the poles, where in case of a Bessel filter a = 1.3617, b = 0.618
and thus Q = 0.577
and in case of a Butterworth filter a = 1.414, b = 1
and thus Q = 0.71
Example
Butterworth filter with f3dB = 5 kHz and R = 100 k:
C14 = 450 pF, C12 = 225 pF
1) Taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999.
Pins: 22 20 18
RR
100k 100k
C14 C12
dB
fQR
b
C
3
4
12
π
=
dB
fR
bQ
C
3
2
2
14
π
=
a
b
Q=
TDA7210V
Applications
Data Sheet 20 Revision 1.1, 2010-06-18
3.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is
determined by the reactive part of the negative resistance of the oscillator circuit as shown in Chapter 4.1.3 and
by the quartz specifications given by the quartz manufacturer.
Figure 8 Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
(4)
with CL the load capacitance (refer to the quartz crystal specification).
Examples
6.7 MHz: CL = 12 pF, XL=695 , CS = 8.9 pF
13.4 MHz: CL = 12 pF, XL=1010 , CS = 5.9 pF
These values may be obtained in high accuracy by putting two capacitors in series to the quartz, such as 22 pF
and 15 pF in the 6.7 MHz case and 22 pF and 8.2 pF in the 13.4 MHz case.
But please note that the calculated value of CS includes the parasitic capacitors also.
CS
Crystal Input
impedance
Z30-28 TDA7210V
Pin 30
Pin 28
L
L
S
Xf
C
C
π
2
1
1
+
=
TDA7210V
Applications
Data Sheet 21 Revision 1.1, 2010-06-18
3.4 Quartz Frequency Calculation
As described in Chapter 2.4.3 the operating range of the on-chip VCO is 820 to 860 MHz with a nominal center
frequency of 840 MHz. This signal is divided by 2 before applied to the mixer in case of operation at 434 MHz. This
local oscillator signal can be used to downconvert the RF signals both with high- or low-side injection at the mixer.
The resulting receive frequency ranges then extend between 810 and 870 MHz or between 400 and 440 MHz.
Low-side injection of the local oscillator has to be used for receive frequencies between 840 and 870 MHz as well
as high-side injection for receive frequencies below 840 MHz. Corresponding to that in the 400 MHz region low-
side injection is applicable for receive frequencies above 420 MHz, high-side injection below this frequency.
Therefore for operation both in the 868 and the 434 MHz ISM bands low-side injection of the local oscillator has
to be used. Then the local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the
RF frequency (434 or 868 MHz). Please note that for low-side injection no sign-inversion occurs in case of
reception and demodulation of FSK-modulated signals.
The overall division ratios in the PLL are 64 or 128 in case of operation at 868 MHz or 32 and 64 in case of
operation at 434 MHz, depending on the crystal frequency used as shown below. The quartz frequency in case of
low-side injection may be calculated by using the following formula:
(5)
Example (low-side injection mode):
(6)
(7)
(8)
(9)
ƒRF Receive frequency
ƒLO Local oscillator (PLL) frequency (ƒRF ± 10.7)
ƒQU Quartz oscillator frequency
r Ratio of local oscillator (PLL) frequency and quartz, frequency as shown in the subsequent table.
Table 7 Dependence of PLL Overall Division Ratio on FSEL and CSEL
FSEL CSEL Ratio r = (fLO/fQU)
Open Open 64
Open GND 32
GND Open 128
GND GND 64
r
f
fRF
QU
7.10±
=
(
)
MHzMHzMHzf 40156.1364/7.104.868
QU =−=
()
MHzMHzMHzf 7008.6128/7.104.868
QU
=−=
()
MHzMHzMHzf 23437.1332/7.102.434
QU
=−=
()
MHzMHzMHzf 6.617264/7.102.434
QU
=−=
TDA7210V
Applications
Data Sheet 22 Revision 1.1, 2010-06-18
3.5 Data Slicer Threshold Generation
The threshold of the data slicer, especially for a coding scheme without DC-content, can be generated using an
external R-C integrator as shown in Figure 9. The time constant TA of the R-C integrator has to be significantly
larger than the longest period of no signal change TL within the data sequence. For the calculation of the time
constant TA please see Application Note „TDA521x_ANV1.1“, chapter „4.11 Data Slicer“. In order to keep
distortion low, the minimum value for R1 is 20 k.
Figure 9 Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use the peak detector in connection with
two resistors and one capacitor as shown in the following figure. The component values are depending on the
coding scheme and the protocol used.
Figure 10 Data Slicer Threshold Generation Utilising the Peak Detector
Pins: 1918
R1
C13
25
data out
Uthreshold
data slicer
data
filter
Pins: 19
18 25
data out
Uthreshold
data slicer
data
filter
26
peak detector
C15
R3
R2
TDA7210V
Applications
Data Sheet 23 Revision 1.1, 2010-06-18
3.6 ASK/FSK Switch Functional Description
The TDA7210V is containing an ASK/FSK switch which can be controlled via Pin 14 (MSEL). This switch is
actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain
of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to
compensate for the DC-offset generated especially in case of the FSK PLL demodulator there is a feedback
connection between the threshold voltage of the bit slicer comparator (Pin 19) to the negative input of the FSK
switch amplifier. This is shown in the following figure.
Figure 11 ASK/FSK Mode Datapath
3.6.1 FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above (highpass) and the data filter
(lowpass). The lower cutoff frequency f2 is determined by the external RC-combination. The upper cutoff
frequency f3 is determined by the data filter bandwidth.
The demodulation gain of the FSK PLL demodulator is 200 µV/kHz. This gain is increased by the gain v of the FSK
switch, which is 11. Therefore the resulting dynamic gain of this circuit is 2.2 mV/kHz within the bandpass. The
gain for the DC content of FSK signal remains at 200 µV/kHz. The cutoff frequencies of the bandpass have to be
chosen such that the spectrum of the data signal is influenced in an acceptable amount.
In case that the user data is containing long sequences of logical zeroes the effect of the drift-off of the bit slicer
threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (Pin
19) is used. The comparator has no hysteresis built in.
This offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20 nA) running
over the external resistor R1. This voltage raises the voltage appearing at pin 19 (e.g. 1 mV with R1 = 100 k). In
order to obtain benefit of this asymmetrical offset for the demodulation of long zeros the lower of the two FSK
frequencies should be chosen in the transmitter as the zero-symbol frequency.
RF1 int
100k
RF2 int
100k
v = 1
18
30k
RF3 int
300k
DATA Out
AC DC
typ. 2 V
1.5 V......2.5 V
0.2 mV/kHz
FSK PLL Demodulator
RSSI (ASK signal)
C14
R1
ASK/FSK Switch
ASK
FSK
+
-
+
-
22
25
C13
19
ASK mode : v=1
FSK mode : v=11
20
14 MSEL
FFB OPP SLP SLN
Comp
-
+
Data Filter
C12
RF4 int
TDA7210V
Applications
Data Sheet 24 Revision 1.1, 2010-06-18
In the following figure the shape of the above mentioned bandpass is shown.
Figure 12 Frequency Characterstic in Case of FSK Mode
The cutoff frequencies are calculated with the following formulas:
(10)
(11)
(12)
f3 is the 3dB cutoff frequency of the data filter - see Section 3.2.
Example:
R1 = 100 k, C13 = 47 nF
This leads to f1 = 44 Hz and f2 = 485 Hz
v
0dB
3dB
v-3dB
f
20dB/dec -40dB/dec
f1 f2 f3
gain (pin 18)
DC
0.18mV/kHz 2mV/kHz
13
3301
3301
2
1
1
C
k
R
kR
f
⋅
Ω+
Ω⋅
=
π
112 11 ffvf
⋅=⋅=
dB
ff 33
=
TDA7210V
Applications
Data Sheet 25 Revision 1.1, 2010-06-18
3.6.2 ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter
alone, thus it is lowpass shaped.The cutoff frequency is determined by the external capacitors C12 and C14 and
the internal 100k resistors as described in Chapter 3.2.
Figure 13 Frequency Charcteristic in Case of ASK Mode
3.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network as described in Chapter 3.5 it is
necessary to use large values for the capacitor C13 attached to the SLN pin (pin 19) in order to achieve long time
constants. This results also from the fact that the choice of the value for R1 connected between the SLP and SLN
pins (pins 18 and 19) is limited by the 330 k resistor appearing in parallel to R1 as can be seen in Figure 11.
Apart from this a resistor value of 100 k leads to a voltage offset of 1mV at the comparator input as described in
Chapter 3.6.1. The resulting startup time constant t1 can be calculated with:
(13)
In case R1 is chosen to be 100 k and C13 is chosen as 47 nF this leads to
(14)
When the device is turned on this time constant dominates the time necessary for the device to be able to
demodulate data properly. In the powerdown mode the capacitor is only discharged by leakage currents.
In order to reduce the turn-on time in the presence of large values of C13 a precharge circuit was included in the
TDA7210V as shown in the following figure.
0dB
-3dB
f
-40dB/dec
f3dB
()
13330||1
1CkR ×Ω=
τ
()
msnFknFkk 6.3477747330||100
1
=×Ω=×ΩΩ=
τ
TDA7210V
Applications
Data Sheet 26 Revision 1.1, 2010-06-18
Figure 14 Principle of the Precharge Circuit
This circuit charges the capacitor C13 with an inrush current Iload of typically 220 µA for a duration of T2 until the
voltage Uc appearing on the capacitor is equal to the voltage Us at the input of the data filter. This voltage is limited
to 2.5 V. As soon as these voltages are equal or the duration T2 is exceeded the precharge circuit is disabled.
t2 is the time constant of the charging process of C18 which can be calculated as:
(15)
As the sum of R4 and R5 is sufficiently large and thus can be neglected. T2 can then be calculated according to
the following formula:
(16)
The voltage transient during the charging of C18 is shown in the following figure:
Iload
+3.1V
20k
+
-
OTA
+2.4V
R4 R5
24 23
Uthreshold
C13
0 / 240uA +
-
19 18
R1
Data Filter ASK/FSK Switch
C18
U2
Us
Uc
Uc<Us
Uc>Us
U2<2.4V : I=240uA
U2>2.4V : I=0
R4+R5=600k
1820
2Ck ×Ω=
τ
6.1
3
4.2
1
1
ln 22 ×≈
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
−
=
ττ
V
V
Tl
TDA7210V
Applications
Data Sheet 27 Revision 1.1, 2010-06-18
Figure 15 Voltage Appearing on C18 During Precharging Process
The voltage appearing on the capacitor C13 connected to pin 20 is shown in the following figure. It can be seen
that due to the fact that it is charged by a constant current source it exhibits is a linear increase in voltage which
is limited to USmax = 2.5 V which is also the approximate operating point of the data filter input. The time constant
appearing in this case can be denoted as T3, which can be calculated with
(17)
Figure 16 Voltage Transient on Capacitor C13 Attached to Pin 19
U2
2
3V
2.4V
T2
T3 USmax C13⋅
220μA
------------------------------2,5V
220μA
----------------- C13⋅==
Us
T3
Uc
TDA7210V
Applications
Data Sheet 28 Revision 1.1, 2010-06-18
As an example the choice of C18 = 22 nF and C13 = 47 nF yields
t2 = 0.44 ms
T2 = 0.71 ms
T3 = 0.53 ms
This means that in this case the inrush current could flow for a duration of 0.64 ms but stops already after 0.49 ms
when the USmax limit has been reached. T3 should always be chosen to be shorter than T2.
It has to be noted finally that during the turn-on duration T2 the overall device power consumption is increased by
the 220 µA needed to charge C13.
The precharge circuit may be disabled if C18 is not equipped. This yields a T2 close to zero. Note that the sum of
R4 and R5 has to be 600 k in order to produce 3 V at the THRES pin as this voltage is internally used also as
the reference for the FSK demodulator.
TDA7210V
Electrical Characteristics
Data Sheet 29 Revision 1.1, 2010-06-18
4 Electrical Characteristics
4.1 Electrical Data
4.1.1 Absolute Maximum Ratings
Attention: TDA7210V is intended for use in general electronic equipment (AV equipment,
telecommunication equipment, home appliances, amusement equipment, computer
equipment, personal equipment, office equipment, measurement equipment) under a normal
operation and use condition.
Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
4.1.2 Operating Range
Within the operational range the IC operates as explained in the circuit description. The AC/DC characteristic limits
are not guaranteed. Currents flowing into the device are denoted as positive currents and v.v.
Supply voltage: VCC = 4.5 V .. 5.5 V
Table 8 Absolute Maximum Ratings, Ambient temperature TAMB=-40°C ... + 85°C
Parameter Symbol Values Unit Note / Test Condition Test Number
Min. Typ. Max.
Supply Voltage VCC -0.3 – 5.5 V 1.1
Junction Temperature Tj-40 – +125 °C 1.2
Storage Temperature TS-40 – +125 °C 1.3
Thermal Resistance Rth JA – – tbd. K/W 1.4
ESD HBM integrity
(all pins)
VESD – – ±2 kV AEC Q100-002
EIA/JESD22-A114
1.5
ESD SDM integrity
(all pins)
VESD – – ±500 V AINSI/ESD5.3.2-2008 1.6
ESD SDM integrity
(corner pins)
VESD ––±750V 1.7
Table 9 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
Supply Current ISF 868 4.1 – 7.7 mA fRF = 868 MHz, FSK Mode 2.1
ISF 434 3.9 – 7.5 mA fRF = 434 MHz, FSK Mode 2.2
ISA 868 3.4 – 7 mA fRF = 868 MHz, ASK Mode 2.3
ISA 434 3.2 – 6.8 mA fRF = 434 MHz, ASK Mode 2.4
TDA7210V
Electrical Characteristics
Data Sheet 30 Revision 1.1, 2010-06-18
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
Receiver Input Level
ASK,fRF=434 MHz
RFin -116 – -13 dBm @ source imp. 50 , BER
2E-3, average power level,
Manchester enc. datarate
1 kBit, 280 kHz IF Bandwidth
2.5
Receiver Input Level FSK,
frequ. dev. ± 50 kHz
fRF=434 MHz
RFin -113 – -13 dBm ■2.6
Receiver Input Level ASK,
fRF=868 MHz
RFin -112 -13 @ source impedance 50 ,
BER 2E-3, average power
level, Manchester encoded
datarate 1 kBit, 280 kHz IF
Bandwidth
■2.7
Receiver Input Level FSK,
frequ. dev. ± 50kHz
fRF=868 MHz
RFin -112 -13 ■2.8
LNI Input Frequency fRF 400/
810
–440/
870
MHz 2.9
M/X Input Frequency fMI 400/
810
–440/
870
MHz 2.10
3 dB IF Frequency Range
ASK
fIF -3dB 5–23MHz ■2.11
3 dB IF Frequency Range
FSK
fIF -3dB 10.4 – 11 MHz ■2.12
Power Mode Standby Standby 0 – 0.8 V 2.13
Power Mode On ON 2.8 – VCC V2.14
Gain Control Voltage,
LNA high gain state
VTHRES 2.8 – VCC-1 V 2.15
Gain Control Voltage,
LNA low gain state
VTHRES 0 – 0.7 V 2.16
Table 9 Operating Range, Ambient temperature TAMB= -40°C ... + 85°C (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 31 Revision 1.1, 2010-06-18
4.1.3 AC/DC Characteristics at TAMB = 25°C
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient
temperature range. Typical characteristics are the median of the production. Currents flowing into the device are
denoted as positive currents and vice versa. The device performance parameters marked with are not subject
to production test. They were verified by design/characterization.
Table 10 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
Supply - Supply Current
Supply Current
Standby Mode
IS PDWN – 50 100 nA Pin 27 (PDWN) open or
tied to 0 V
3.1
Supply Current
Device operating in
868 MHz range, FSK mode
ISF 868 5.1 5.9 6.7 mA Pin 9 (FSEL) tied to GND,
Pin 14 (MSEL) tied to
GND
3.2
Supply Current
Device operating in
434 MHz range, FSK mode
ISF 434 4.9 5.7 6.5 mA Pin 9 (FSEL) open, Pin 14
(MSEL) tied to GND
3.3
Supply Current
Device operating in
868 MHz range, ASK mode
ISA 868 4.4 5.2 6 mA Pin 9 (FSEL) tied to GND,
Pin 14 (MSEL) open
3.4
Supply Current
Device operating in
434 MHz range, ASK mode
ISA 434 4.2 5 5.8 mA Pin 9 (FSEL) open, Pin 14
(MSEL) open
3.5
LNA - Signal Input LNI (PIN 1), VTHRES > 2.8 V, high gain mode
Average Power Level
atBER = 2E-3 (Sensitivity)
ASK fRF=434 MHz
RFin – -112 – dBm Manchester encoded
datarate 4 kBit, 280 kHz
IF Bandwidth
■3.6
Average Power Level
atBER = 2E-3 (Sensitivity)
FSK fRF=434 MHz
RFin – -108 – dBm Manchester enc. datarate
4 kBit, 280 kHz IF
Bandw.,± 50 kHz pk. dev.
■3.7
Average Power Level
atBER = 2E-3 (Sensitivity)
ASK fRF=868 MHz
RFin – -108 – dBm Manchester encoded
datarate 4 kBit, 280 kHz
IF Bandwidth
■3.8
Average Power Level
atBER = 2E-3 (Sensitivity)
FSK fRF=868 MHz
RFin – -107 – dBm Manchester enc. datarate
4 kBit, 280 kHz IF
Bandw.,± 50 kHz pk. dev
■3.9
Average Power Level
atBER = 2E-3 (Sensitivity)
ASK fRF=434 MHz
RFin – -115 – dBm Manchester encoded
datarate 1 kBit, 280 kHz
IF Bandwidth
■3.10
Average Power Level
atBER = 2E-3 (Sensitivity)
FSK fRF=434 MHz
RFin – -112 – dBm Manchester enc. datarate
1 kBit, 280 kHz IF
Bandw.,± 50 kHz pk. dev.
■3.11
Average Power Level
atBER = 2E-3 (Sensitivity)
ASK fRF=868 MHz
RFin – -111 – dBm Manchester encoded
datarate 1 kBit, 280 kHz
IF Bandwidth
■3.12
TDA7210V
Electrical Characteristics
Data Sheet 32 Revision 1.1, 2010-06-18
Average Power Level
atBER = 2E-3 (Sensitivity)
FSK fRF=868 MHz
RFin – -111 – dBm Manchester enc. datarate
1 kBit, 280 kHz IF
Bandw.,± 50 kHz pk. dev.
■3.13
Input impedance,
fRF=434 MHz
S11 LNA 0.890 /
-36.3
deg
■3.14
Input impedance,
fRF=868 MHz
S11 LNA 0.784 /
-66.2
deg
■3.15
Input level @ 1 dB C.P. fRF =
434 MHz
P1dBLNA – -16 – dBm Matched input ■3.16
Input level @ 1 dB C.P.
fRF = 868 MHz
P1dBLNA – -7 – dBm Matched input ■3.17
Input 3rd order intercept
point fRF=434 MHz
IIP3LNA – -21 – dBm Matched input ■3.18
Input 3rd order intercept
point fRF=868 MHz
IIP3LNA – -14 – dBm Matched input ■3.19
LO signal feedthrough at
antenna port
LOLNI –-83-73dBm ■3.20
LNA - Signal Output LNO (PIN 4), VTHRES > 2.8 V, high gain mode
Gain fRF=434 MHz S21 LNA 1.497 /
137.0
deg
■3.21
Gain fRF=868 MHz S21 LNA 1.298 /
103.7
deg
■3.22
Output impedance,
fRF=434 MHz
S22 LNA 0.899 /
-16.4
deg
■3.23
Output impedance,
fRF=868 MHz
S22 LNA 0.885 /
-25.7
deg
■3.24
LNA- Signal Input LNI, VTHRES = GND, low gain mode
Input impedance,
fRF=434 MHz
S11 LNA 0.896 /
-37.1
deg
■3.25
Input impedance,
fRF=868 MHz
S11 LNA 0.794 /
-69.1
deg
■3.26
Input level @ 1 dB C. P.
fRF=434 MHz
P1dBLNA – -7 – dBm Matched input ■3.27
Input level @ 1 dB C. P.
fRF = 868 MHz
P1dBLNA – -3 – dBm Matched input ■3.28
Table 10 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 33 Revision 1.1, 2010-06-18
Input 3rd order intercept
point fRF=434 MHz
IIP3LNA – -19 – dBm Matched input ■3.29
Input 3rd order intercept
point fRF=868 MHz
IIP3LNA – -13 – dBm Matched input ■3.30
LNA - Signal Output LNO, VTHRES = GND, low gain mode
Gain fRF=434 MHz S21 LNA 0.180 /
138.1
deg
■3.31
Gain fRF=868 MHz S21 LNA 0.162 /
109.6
deg
■3.32
Output impedance,
fRF=434 MHz
S22 LNA 0.904 /
-16.0
deg
■3.33
Output impedance,
fRF=868 MHz
S22 LNA 0.888 /
-26.4
deg
■3.34
LNA - Antenna to IFO, VTHRES > 2.8 V, high gain mode
Voltage Gain Antenna to
IFO fRF=434 MHz
GAnt-IFO – 51 – dB 3.35
Voltage Gain Antenna to
IFO fRF=868 MHz
GAnt-IFO – 47 – dB 3.36
LNA - Antenna to IFO, VTHRES = GND, low gain mode
Voltage Gain Antenna to
IFO fRF=434 MHz
GAnt-IFO – 36 – dB 3.37
Voltage Gain Antenna to
IFO fRF=868 MHz
GAnt-IFO – 28 – dB 3.38
3VOUT - Signal 3VOUT (PIN 24)
Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open 3.39
Current out I3VOUT -3 -5 -10 µA See Chapter 3.3.40
AGC - Signal THRES (PIN 23)
Input Voltage range VTHRES 0–V
CC-1 V See Chapter 3.3.41
LNA low gain mode VTHRES 0 – – V 3.42
LNA high gain mode VTHRES 2.9 3.0 VCC-1 V Voltage must not be
higher than VCC-1 V
3.43
Current in ITHRES_in –5–nAµA ■3.44
AGC - Signal TAGC (PIN 2)
Current out
LNA low gain state
ITAGC_out -3.6 -4.2 -5 A RSSI > VTHRES 3.45
Current in
LNA high gain state
ITAGC_in 11.52.2A RSSI<VTHRES 3.46
Table 10 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 34 Revision 1.1, 2010-06-18
MIXER - Signal Input MI/MIX (PINS 6/7)
Input impedance,
fRF=434 MHz
S11 MIX 0.936 /
-15.2
deg
■3.47
Input impedance,
fRF=868 MHz
S11 MIX 0.917 /
-27.6
deg
■3.48
Input 3rd order intercept
point fRF=434 MHz
IIP3MIX –-42–dBm ■3.49
Input 3rd order intercept
point fRF=868 MHz
IIP3MIX –-42–dBm ■3.50
MIXER - Signal Output IFO (PIN 10)
Output impedance ZIFO – 330 – ■3.51
Conversion Voltage Gain
fRF=434 MHz
GMIX – 24 – dB 3.52
Conversion Voltage Gain
fRF=868 MHz
GMIX – 31 – dB 3.53
LIMITER - Signal Input LIM/X (PINS 16/17)
Input Impedance ZLIM 264 330 396 ■3.54
RSSI dynamic range DRRSSI 60 – 80 dB ■3.55
RSSI linearity LINRSSI– ±1 – dB ■3.56
Operating frequency
(3 dB points)
fLIM 5 10.7 23 MHz ■3.57
LIMITER - DATA FILTER
Useable bandwidth BWBB
FILT
––100kHz ■3.58
RSSI Level at Data Filter
Output SLP,
RFIN=-103 dBm
RSSIlow – 1.39 – V LNA in high gain mode
RF=434 MHz
3.59
RSSI Level at Data Filter
Output SLP, RFIN=-30 dBm
RSSIhigh – 2.79 – V LNA in high gain mode
RF=434 MHz
3.60
SLICER - Signal Output DATA (PIN 25)
Maximum Datarate DRmax – – 100 kB/s NRZ, 20 pF capacitive
loading
■3.61
LOW output voltage VSLIC_L 0 – 0.1 V 3.62
HIGH output voltage VSLIC_H VCC-1.3 VCC-1 VCC-0.7 V Output current = 200 A3.63
SLICER - Signal SLN (PIN 19)
Precharge Current Out IPCH_SLN -100 -220 -300 ASee Chapter 3.3.64
PEAK DETECTOR - Signal Output PDO (PIN 26)
Table 10 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 35 Revision 1.1, 2010-06-18
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
Load current Iload -500 – – A Static load current must
not exceed -500 A
3.65
Leakage current Ileakage 0 200 1000 nA 3.66
CRYSTAL OSCILLATOR - Signals CRST1, CRST2, (PINS 30/28)
Operating frequency fCRSTL 6 – 14 MHz Fundamental mode,
series resonance
3.67
Input Impedance @ ~6MHz Z1-28 – -825
+j695
–■3.68
Input Impedance @
~13MHz
Z1-28 – -600
+j1010
–■3.69
Serial Capacity @ ~6MHz CS 6=C1 – 8.9 – pF 3.70
Serial Capacity @ ~13MHz CS13=C1 – 5.9 – pF 3.71
ASK/FSK SIGNAL SWITCH - Signal MSEL (PIN 14)
ASK Mode VMSEL 1.4 – 41) V Or open 3.72
FSK Mode VMSEL 0 – 0.2 V 3.73
FSK DEMODULATOR
Demodulation Gain GFMDEM – 200 – V/
kHz
3.74
Useable IF Bandwidth BWIFPLL 10.2 10.7 11.2 MHz 3.75
POWER DOWN MODE - Signal PDWN (PIN 27)
Power Mode On ON 2.8 – VCC V3.76
Power Mode Standby Standby 0 – 0.8 V 3.77
Input bias current PDWN IPDWN –19–A Power On Mode 3.78
Start-up Time until valid
signal is detected at IF
TSU – <1 – ms Depends on the used
crystal
3.79
VCO MULTIPLEXER - Signal FSEL (PIN 9)
fRF range 434 MHz VFSEL 1.4 – 41) V Or open 3.80
fRF range 868 MHz VFSEL 0 – 0.2 V 3.81
Output bias current FSEL IFSEL -160 -200 -240 A FSEL tied to GND 3.82
PLL DIVIDER - Signal CSEL (PIN 15)
fCRSTL range 6.xxMHz VCSEL 1.4 – 41) V or open 3.83
fCRSTL range 13.xxMHz VCSEL 0 – 0.2 V 3.84
Input bias current CSEL ICSEL -3 -5 -7 A CSEL tied to GND 3.85
1) Maximum voltage in Power-On state is 4 V, but in PDWN-state the maximum voltage is 2.8 V.
Table 10 AC/DC Characteristics with TAMB = 25 °C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Num
ber
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 36 Revision 1.1, 2010-06-18
4.1.4 AC/DC Characteristics at TAMB = -40 to 85°C
Currents flowing into the device are denoted as positive currents and vice versa.
Table 11 AC/DC Characteristics with TAMB= -40°C ... + 85°C, VCC = 4.5 ... 5.5 V
Parameter Symbol Values Unit Note / Test Condition Test Number
Min. Typ. Max.
Supply - Supply Current
Supply Current
Standby Mode
IS PDWN – 50 400 nA Pin 27 (PDWN) open or tied
to 0 V
4.1
Supply Current
Device operating in
868 MHz range, FSK
mode
ISF 868 4.1 5.9 7.7 mA Pin 9 (FSEL) tied to GND,
Pin 14 (MSEL) tied to GND
4.2
Supply Current
Device operating in
434 MHz range, FSK
mode
ISF 434 3.9 5.7 7.5 mA Pin 9 (FSEL) open, Pin 14
(MSEL) tied to GND
4.3
Supply Current
Device operating in
868 MHz range, ASK
mode
ISA 868 3.4 5.2 7 mA Pin 9 (FSEL) tied to GND,
Pin 14 (MSEL) open
4.4
Supply Current
Device operating in
434 MHz range, ASK
mode
ISA 434 3.2 5 6.8 mA Pin 9 (FSEL) open, Pin 14
(MSEL) open
4.5
3VOUT - Signal 3VOUT (PIN 24)
Output voltage V3VOUT 2.9 3.1 3.3 V 3VOUT Pin open 4.6
Current out I3VOUT -3 -5 -10 µA See Chapter 3.4.7
AGC - Signal THRES (PIN 23)
Input Voltage range VTHRES 0–V
CC-1 V See Chapter 3.4.8
LNA low gain mode VTHRES 0 – 0.3 V 4.9
LNA high gain mode VTHRES 2.9 3 3.3 V Voltage must not be higher
than VCC-1V
4.10
Current in ITHRES_in –5–nA ■4.11
AGC - Signal TAGC (PIN 2)
Current out
LNA low gain state
ITAGC_out -1 -4.2 -8 µA RSSI > VTHRES 4.12
Current in
LNA high gain state
ITAGC_in 0.5 1.5 5 µA RSSI<VTHRES 4.13
MIXER
Conversion Voltage
Gain fRF=434 MHz
GMIX – 24 – dB 4.14
Conversion Voltage
Gain fRF=868 MHz
GMIX – 32 – dB 4.15
TDA7210V
Electrical Characteristics
Data Sheet 37 Revision 1.1, 2010-06-18
LIMITER - Signal Input LIM/X (PINS 16/17)
RSSI dynamic range DRRSSI 60 – 80 dB 4.16
LIMITER - DATA FILTER
RSSI Level at Data
Filter Output SLP,
RFIN=-103 dBm
RSSIlow – 1.39 – dB LNA in high gain mode
RF=434 MHz
4.17
RSSI Level at Data
Filter Output SLP,
RFIN=-30 dBm
RSSIhigh – 2.79 – dB LNA in high gain mode
RF=434 MHz
4.18
SLICER - Signal Output DATA (PIN 25)
Maximum Datarate DRmax – – 100 kB/s NRZ, 20 pF capacitive
loading
■4.19
LOW output voltage VSLIC_L 0 – 0.1 V 4.20
HIGH output voltage VSLIC_H VCC-1.5 VCC-1 VCC-0.5 V Output current = 200 µA 4.21
SLICER - Signal SLN (PIN 19)
Precharge Current
Out
IPCH_SLN -100 -220 -300 µA See Chapter 3.4.22
PEAK DETECTOR - Signal Output PDO (PIN 26)
Load current Iload -400 – – µA Static load current must not
exceed -500 µA
4.23
Leakage current Ileakage 0 700 2000 nA 4.24
CRYSTAL OSCILLATOR - Signals CRST1, CRST2, (PINS 30/28)
Operating frequency fCRSTL 6 – 14 MHz Fundamental mode, series
resonance
4.25
ASK/FSK SIGNAL SWITCH - Signal MSEL (PIN 14)
ASK Mode VMSEL 1.4 – 41) V Or open 4.26
FSK Mode VMSEL 0 – 0.2 V 4.27
FSK DEMODULATOR
Demodulation Gain GFMDEM –200–µV/
kHz
4.28
Useable IF Bandwidth BWIFPLL 10.2 10.7 11.2 MHz 4.29
POWER DOWN MODE - Signal PDWN (PIN 27)
Power Mode On ON 2.8 – VCC V4.30
Power Mode Standby Standby 0 – 0.8 V 4.31
Start-up Time until
valid signal is
detected at IF
TSU – <1 – ms Depends on the used
crystal
4.32
VCO MULTIPLEXER - Signal FSEL (PIN 9)
fRF range 434 MHz VFSEL 1.4 – 41) V Or open 4.33
fRF range 868 MHz VFSEL 0 – 0.2 V 4.34
Table 11 AC/DC Characteristics with TAMB= -40°C ... + 85°C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Number
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 38 Revision 1.1, 2010-06-18
Attention: Test ■ means that the parameter is not subject to production test.
It was verified by design/characterization.
4.2 Customer Test Circuit
The device performance parameters marked with in Table 9, Table 10, and Table 11 are not subject to
production test. They were verified by design/characterization. The received signal is accessible on a 2-pole pin
connector and can be used for simple remote-control applications. More information on the board is available on
request.
Output bias current
FSEL
IFSEL -110 -200 -340 µA FSEL tied to GND 4.35
PLL DIVIDER - Signal CSEL (PIN 15)
fCRSTL range 6.xxMHz VCSEL 1.4 – 41) V Or open 4.36
fCRSTL range
13.xxMHz
VCSEL 0 – 0.2 V 4.37
Input bias current
CSEL
ICSEL -3 -5 -7 µA CSEL tied to GND 4.38
1) Maximum voltage in Power-On state is 4 V, but in PDWN-state the maximum voltage is 2.8 V.
Table 11 AC/DC Characteristics with TAMB= -40°C ... + 85°C, VCC = 4.5 ... 5.5 V (cont’d)
Parameter Symbol Values Unit Note / Test Condition Test Number
Min. Typ. Max.
TDA7210V
Electrical Characteristics
Data Sheet 39 Revision 1.1, 2010-06-18
Figure 17 Schematic of the Customer Test Board TDA7210V
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TDA7210V
Electrical Characteristics
Data Sheet 40 Revision 1.1, 2010-06-18
4.3 Customer Test Board Layout
Figure 18 Top Layer of Customer Test Board TDA7210V
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TDA7210V
Electrical Characteristics
Data Sheet 41 Revision 1.1, 2010-06-18
Figure 19 Bottom Layer of Customer Test Board TDA7210V
TDA7210V
Electrical Characteristics
Data Sheet 42 Revision 1.1, 2010-06-18
4.4 Bill of Materials
The following components are necessary for evaluation of the TDA7210V.
Table 12 Bill of Materials
Ref Value Specification
R1 100 k0402, ± 5%
R2 100 k0402, ± 5%
R3 820 k0402, ± 5%
R4 240 k0402, ± 5%
R5 360 k0402, ± 5%
R6 10 k0402, ± 5%
R7 434 MHz: -
868 MHz: 0
-
0402, ± 5%
R8 - -
R9 0 0402, ± 5%
L1 434 MHz: 30 nH
868 MHz: 8.2 nH
Coilcraft SIMID 0402HP, ± 2%
Coilcraft SIMID 0402HP, ± 2%
L2 434 MHz: 56 nH
868 MHz: 15 nH
Coilcraft SIMID 0402HP, ± 2%
Coilcraft SIMID 0402HP, ± 2%
C1 434 MHz: 1.8 pF
868 MHz: 1.2 pF
0402, COG, ± 0.1 pF
0402, COG, ± 0.1 pF
C2 434 MHz: -
868 MHz: -
-
0402, COG, ± 0.1pF
C3 434 MHz: 18 pF
868 MHz: 10 pF
0402, COG, ± 0.1pF
0402, COG, ± 0.1pF
C4 100 pF 0402, COG, ± 5%
C5 47 nF 0402, COG, ± 5%
C6 434 MHz: -
868 MHz: -
-
-
C7 100 pF 0402, X7R, ± 5%
C8 434 MHz: 100 pF
868 MHz: 270 pF
0402, COG, ± 1%
0402, COG, ± 1%
C9 100 pF 0402, COG, ± 5%
C10 10 nF 0402, X7R, ± 10%
C11 10 nF 0402, X7R, ± 10%
C12 220 pF 0402, COG, ± 5%
C13 47 nF 0402, X7R, ± 10%
C14 470 pF 0402, COG, ± 5%
C15 47 nF 0402, X7R, ± 5%
C16 8.2 pF 0402, COG, ± 0.1 pF
C17 22 pF 0402, COG, ± 1%
C18 22 nF 0402, X7R, ± 5%
TDA7210V
Electrical Characteristics
Data Sheet 43 Revision 1.1, 2010-06-18
C19 10 nF 0402, X7R, ± 5%
C20 47 nF 0402, X7R, ± 5%
C21 2.2 µF 0805, X7R, ± 10%
C22 47 nF 0402, X7R, ± 5%
Q1 (fRF – 10.7 MHz)/32 or
(fRF – 10.7 MHz)/64
Tokoy Denpa TSS-6035B
434 MHz: 13.2343750 MHz, CL=12 pF, Spec.No. 120-16504
868 MHz: 13.4015625 MHz, CL=12 pF, Spec.No. 120-16505
Q2 IF-Filter 10,7MHz Murata SFECF10M7FA00S0-R0
X1, X3 2-pole pin connector 2-pole pin connector, 2,54mm
X2 SMA-connector RS: SMA Jack End Launch 1,07mm
JP1 3-pole pin connector 3-pole pin connector, 2,54mm
MSEL solder bridge closed solder bridge
CSEL solder bridge closed solder bridge
IC1 TDA7210V Infineon
Table 12 Bill of Materials (cont’d)
Ref Value Specification
