BCM® in a VIA™ Package
Bus Converter
BCM® in a VIA™ Package Rev 1.6
Page 1 of 43 08/2020
Isolated Fixed-Ratio DC-DC Converter
BCM4414xG0F4440yzz
S
NRTL
CUS
CUS
®
Note: Product images may not highlight current product markings.
Features & Benefits
• Up to 40A continuous low-voltage-side current
• Fixed transformation ratio (K) of 1/16
• Up to 776W/in3 power density
• 97.5% peak efficiency
• Integrated filtering
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 4414 package
• High MTBF
• Thermally enhanced VIA package
• PMBus® management interface
Typical Applications
• High-Voltage DC Power Distribution
• 3-Phase AC-DC Converters
• Information and Communication
Technology (ICT) Equipment
• High-End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High-Density Energy Systems
• Transportation
• Green Buildings and Microgrids
Product Description
The BCM4414xG0F4440yzz in a VIA package is a high-efficiency
Bus Converter, operating from a 400 to 700VDC high-voltage bus
to deliver an isolated 25 to 43.8VDC unregulated, low voltage.
This unique ultra-low-profile module incorporates DC-DC
conversion, integrated filtering and PMBus commands and controls
in a chassis or PCB mount form factor.
The BCM offers low noise, fast transient response and
industry-leading efficiency and power density. A low-voltage-side
referenced PMBus-compatible telemetry and control interface
provides access to the BCM’s configuration, fault monitoring and
other telemetry functions.
Leveraging the thermal and density benefits of Vicor VIA packaging
technology, the BCM module offers flexible thermal management
options with very low top and bottom side thermal impedances.
When combined with downstream Vicor DC-DC conversion
components and regulators, the BCM allows the Power Design
Engineer to employ a simple, low-profile design, which will
differentiate the end system without compromising on cost or
performance metrics.
Product Ratings
VHI = 544V (400 – 700V) ILO = up to 40A
VLO = 34V (25 – 43.8V)
(no load)K = 1/16
Size:
4.35 x 1.40 x 0.37in
[110.55 x 35.54 x 9.40mm]
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
Typical Applications
+HI +LO
EXT_BIAS
SCL
SDA
ISOLATION BOUNDARY
SGND
ADDR
–HI –LO
L
O
A
D
3-Phase AIM BCMin a VIA package
+
–
L1
L2
L3
+HI +LO
EXT_BIAS
SCL
SDA
SGND
SCL
SDA
SGND
ADDR
–HI –LO
L
O
A
D
BCM in a VIA package
BCM in a VIA package
+HI
DC
+LO
EXT_BIAS
SCL
SDA
SGND
ADDR
–HI –LOR2
5V
R1
5V
CLOCK
DATA
GROUND
Host PMBus®
+
–
ISOLATION BOUNDARY
ISOLATION BOUNDARY
3-phase AC to point-of-load (3-phase AIM + BCM4414xG0F4440yzz)
Paralleling BCM in a VIA package – connection to common Host PMBus®
BCM® in a VIA™ Package Rev 1.6
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External Current Sense
SGND
SGND
Voltage Reference with Soft Start
Voltage Sense and Error Amplifier
(Differential)
VTM Start up Pulse
SGND
IN OUT
GND
V +
VOUT
–IN+IN
V –
PRM
ENABLE
TRIM
SHARE/
CONTROL NODE
AL
IFB
VC
VT
VAUX
REF/
REF_EN
+IN
–IN
+OUT
–OUT
PRM_SGND
SGND
TM
VC
PC
+IN
–IN –OUT
+OUT
ISOLATION BOUNDARY
VTM
HV LV
REF 3312
SGND
Voltage Sense
SGND
LOAD
PRM_SGND
CI_PRM_ELEC
RI_PRM_DAMP
LI_PRM_FLT
RO_PRM_DAMP
LO_PRM_FLT CO_PRM_CER
CO_VTM_CER
VREF
enable/disable
switch
–HI
+LO
–LO
FUSE
ISOLATION BOUNDARY
HV LV
+HI
CHI
SOURCE_RTN
VHI
EXT_BIAS
SDA
Host PMBus®
SGND
PMBus
SGND
+
–
VEXT
SCL
SGND
SGND
ADDR
}
3
SGND
0 Ω
BCM in a VIA Package
PRM
ENABLE
TRIM
SHARE/
CONTROL NODE
AL
IFB
VC
VT
VAUX
REF/
REF_EN
+IN
–IN
+OUT
–OUT
TM
VC
PC
+IN
–IN –OUT
+OUT
Adaptive Loop Temperature Feedback
VTM Start Up Pulse
PRM_SGND
SGND
ISOLATION BOUNDARY
LOAD_RTN
VTM
HV LV
BCM in a VIA Package
–HI
+LO
–LO
FUSE
ISOLATION BOUNDARY
HV LV
+HI
RI_PRM_CER
RTRIM_PRM
RAL_PRM
PRM_SGND
CHI
SOURCE_RTN
VHI
RI_PRM_DAMP
LI_PRM_FLT
RO_PRM_DAMP
LO_PRM_FLT
CO_PRM_CER
LOAD
VOUT
CO_VTM_CER
enable/disable
switch
EXT_BIAS
SDA
Host PMBus®
SGND
PMBus
SGND
+
–
VEXT
SCL
SGND
SGND
ADDR
}
3
PRM_SGND
SGND
Typical Applications (Cont.)
BCM4414xG0F4440yzz + PRM + VTM, Remote-Sense Configuration – connection to common Host PMBus
BCM4414xG0F4440yzz + PRM™ + VTM™, Adaptive-Loop Configuration – connection to common Host PMBus®
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
13
+HI +LO
TOP VIEW
BCM4414 in a VIA Package - Chassis (Lug) Mount
–LO
–HI
5 EXT BIAS
6 SCL
7 SDA
8 SGND
9 ADDR
PMBus
PMBus
2 4
–HI –LO
TOP VIEW
BCM4414 in a VIA Package - Board (PCB) Mount
+LO
+HI
9 ADDR
8 SGND
7 SDA
6 SCL
5 EXT BIAS
24
13
Pin Configuration
Pin Descriptions
Pin Number Signal Name Type Function
1 +HI HIGH SIDE POWER High-voltage-side positive power terminal
2 –HI HIGH SIDE POWER
RETURN High-voltage-side negative power terminal
3 +LO LOW SIDE
POWER Low-voltage-side positive power terminal
4 –LO LOW SIDE
POWER RETURN Low-voltage-side negative power terminal
5 EXT BIAS INPUT 5V supply input
6 SCL INPUT I2C™ Clock, PMBus® Compatible
7 SDA INPUT/OUTPUT I2C Data, PMBus Compatible
8 SGND LOW SIDE
SIGNAL RETURN Signal Ground
9 ADDR INPUT Address assignment – Resistor based
Note: The dot on the VIA housing indicates the location of the signal pin 9.
Notes: All signal pins (5, 6, 7, 8, 9) are referenced to the low-voltage side and isolated from the high-voltage side.
Keep SGND signal separated from the low-voltage side power return terminal (–LO) in electrical design.
BCM® in a VIA™ Package Rev 1.6
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Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter Comments Min Max Unit
+HI to –HI –1 800 V
HI_DC or LO_DC Slew Rate 1 V/µs
+LO to –LO –1 60 V
EXT BIAS to SGND –0.3 10 V
0.15 A
SCL to SGND –0.3 5.5 V
SDA to SGND –0.3 5.5 V
ADDR to SGND –0.3 3.6 V
Isolation Voltage /
Dielectric Withstand
High-voltage side to case 3100 VDC
High-voltage side to low-voltage side 4300 VDC
Low-voltage side to case 1200 VDC
Part Ordering Information
Part Number Package Type Product Grade Option Field
BCM4414BG0F4440C06
B = Board VIA
C = –20 to 100°C [a] 06 = Short Pin/PMBus®
BCM4414BG0F4440C10 10 = Long Pin/PMBus
BCM4414BG0F4440T06 T = –40 to 100°C [a] 06 = Short Pin/PMBus
BCM4414BG0F4440T10 10 = Long Pin/PMBus
BCM4414BG0F4440M06 M = –55 to 100°C [a] 06 = Short Pin/PMBus
BCM4414BG0F4440M10 10 = Long Pin/PMBus
BCM4414VG0F4440C02
V = Chassis VIA
C = –20 to 100°C [a]
02 = Chassis/PMBus
BCM4414VG0F4440T02 T = –40 to 100°C [a]
BCM4414VG0F4440M02 M = –55 to 100°C [a]
[a] High-temperature current derating may apply; see Figure 1, specified thermal operating area.
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Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powertrain Specification – Forward Direction Operation (High-Voltage Side to Low-Voltage Side)
HI-Side Voltage Range,
(Continuous) VHI_DC 400 700 V
HI-Side Voltage Range,
(Transient) VHI_TRANS 400 700 V
HI-Side Voltage Initialization
Threshold VµC_ACTIVE HI-side voltage where internal controller is initialized,
(powertrain inactive) 130 350 V
HI-Side Quiescent Current IHI_Q
Disabled, VHI_DC = 544V 6.3 mA
TCASE ≤ 100ºC 10.2
No-Load Power Dissipation PHI_NL
VHI_DC = 544V, TCASE = 25ºC 12 20
W
VHI_DC = 544V 30
VHI_DC = 400 – 700V, TCASE = 25ºC 22
VHI_DC = 400 – 700V 32
HI-Side Inrush Current Peak IHI_INR_PK
VHI_DC = 700V, CLO_EXT = 470μF,
RLOAD_LO = 20% of full-load current 4A
TCASE ≤ 100ºC 8
DC HI-Side Current IHI_IN_DC At ILO_OUT_DC = 40A, TCASE ≤ 70ºC 2.6 A
Transformation Ratio K High voltage to low voltage
K = VLO_DC / VHI_DC,at no load 1/16 V/V
LO-Side Current (Continuous) ILO_OUT_DC TCASE ≤ 70ºC 40 A
LO-Side Current (Pulsed) ILO_OUT_PULSE
2ms pulse, 25% duty cycle,
ILO_OUT_AVG ≤ 50% rated ILO_OUT_DC
44 A
Efficiency (Ambient) ηAMB
VHI_DC = 544V, ILO_OUT_DC = 40A 95 96.9
%VHI_DC = 400 – 700V, ILO_OUT_DC = 40A 94
VHI_DC = 544V, ILO_OUT_DC = 20A 96 97.5
Efficiency (Hot) ηHOT VHI_DC = 544V, ILO_OUT_DC = 40A, TCASE = 70°C 95 96.1 %
Efficiency (Over Load Range) η20% 8A < ILO_OUT_DC < 40A 92 %
LO-Side Output Resistance
RLO_COLD VHI_DC = 544V, ILO_OUT_DC = 40A, TCASE = –40°C 5.5 10.8 20
mΩRLO_AMB VHI_DC = 544V, ILO_OUT_DC = 40A 8 14.4 22
RLO_HOT VHI_DC = 544V, ILO_OUT_DC = 40A, TCASE = 70°C 9 21.9 30
Switching Frequency FSW LO-side voltage ripple frequency = 2x FSW 0.7 0.75 0.8 MHz
LO-Side Voltage Ripple VLO_OUT_PP
CLO_EXT = 0μF, ILO_OUT_DC = 40A,
VHI_DC = 544V, 20MHz BW 300 mV
TCASE ≤ 100ºC 800
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powertrain Specification – Forward Direction Operation (High-Voltage Side to Low-Voltage Side) Cont.
Effective HI-Side Capacitance
(Internal) CHI_INT Effective value at 544VHI_DC 0.18 µF
Effective LO-Side Capacitance
(Internal) CLO_INT Effective value at 34VLO_DC 50.6 µF
Rated LO-Side Capacitance (External) CLO_OUT_EXT Excessive capacitance may drive module into short
circuit protection 470 µF
Rated LO-Side Capacitance (External),
Parallel Array Operation CLO_OUT_AEXT CLO_OUT_AEXT Max = N • 0.5 • CLO_OUT_EXT MAX, where
N = the number of units in parallel 235 µF
Powertrain Hardware Protection Specification – Forward Direction Operation (High-Voltage Side to Low-Voltage Side)
• These built-in powertrain protections are fixed in hardware and cannot be configured through PMBus®.
• When duplicated in supervisory limits, hardware protections serve a secondary role and become active when supervisory limits are
disabled through PMBus.
Auto Restart Time tAUTO_RESTART
Start up into a persistent fault condition. Non-latching
fault detection given VHI_DC > VHI_UVLO+
900 1000 1100 ms
HI-Side Overvoltage
Lockout Threshold VHI_OVLO+ 730 750 780 V
HI-Side Overvoltage
Recovery Threshold VHI_OVLO– 700 730 740 V
HI-Side Overvoltage
Lockout Hysteresis VHI_OVLO_HYST 20 V
HI-Side Overvoltage
Lockout Response Time tHI_OVLO 10 µs
HI-Side Soft Start Time tHI_SOFT_START From powertrain active. Fast current limit protection
disabled during soft start 12ms
LO-Side Overcurrent Trip Threshold ILO_OUT_OCP 42 50 70 A
LO-Side Overcurrent
Response Time Constant tLO_OUT_OCP Effective internal RC filter 3.6 ms
LO-Side Short Circuit
Protection Trip Threshold ILO_OUT_SCP 55 A
LO-Side Short Circuit
Protection Response Time tLO_OUT_SCP Short circuit protection (fast current limit) is
disabled at start up [b] 1 µs
Overtemperature
Shutdown Threshold tOTP+ Internal 125 °C
[b] At start up, short circuit protection is disabled. Soft-start current limit provides protection against pre-existing output shorts. Soft-start mode ends when the
output voltage reaches at least 90% of the final output voltage, and short-circuit protection is enabled when tHI_SOFT_START expires. Shorts that occur after
soft start ends but before tHI_SOFT_START expires may cause damage to the product and will require external protection.
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Powertrain Supervisory Limits Specification – Forward Direction Operation (High-Voltage Side to Low-Voltage Side)
• These supervisory limits are set in the internal controller and can be reconfigured or disabled through PMBus®.
• When disabled, the powertrain protections presented in the previous table will intervene during fault events.
HI-Side Overvoltage
Lockout Threshold VHI_OVLO+ 730 750 780 V
HI-Side Overvoltage
Recovery Threshold VHI_OVLO– 700 730 740 V
HI-Side Overvoltage
Lockout Hysteresis VHI_OVLO_HYST 20 V
HI-Side Overvoltage
Lockout Response Time tHI_OVLO 100 µs
HI-Side Undervoltage
Lockout Threshold VHI_UVLO– 350 360 370 V
HI-Side Undervoltage
Recovery Threshold VHI_UVLO+ 370 380 399 V
HI-Side Undervoltage
Lockout Hysteresis VHI_UVLO_HYST 20 V
HI-Side Undervoltage
Lockout Response Time tHI_UVLO 100 µs
HI-Side Undervoltage Start Up Delay tHI_UVLO+_DELAY
From VHI_DC = VHI_UVLO+ to powertrain active
(i.e., one-time start up delay from application of
VHI_DC to VLO_DC)
50 ms
LO-Side Overcurrent
Trip Threshold ILO_OUT_OCP 42 50 70 A
LO-Side Overcurrent
Response Time Constant tLO_OUT_OCP Effective internal RC filter 2 ms
Overtemperature
Shutdown Threshold tOTP+ Internal 125 °C
Overtemperature
Recovery Threshold tOTP– Internal 105 110 115 °C
Undertemperature
Shutdown Threshold (Internal) tUTP
C-Grade –25
°CT-Grade –45
M-Grade –55
Undertemperature Restart Time tUTP_RESTART Start up into a persistent fault condition. Non-latching
fault detection given VHI_DC > VHI_UVLO+ 3 s
BCM® in a VIA™ Package Rev 1.6
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Operating Area
0
5
10
15
20
25
30
35
40
45
50
40 60 50 80 90 70 100 110 120
LO-Side Output Current (A)
Case Temperature (°C)
400 – 700V
LO-Side Capacitance
(% Rated CLO_EXT_MAX)
LO-Side Current (% I
LO_DC
)
0
10
20
30
40
50
60
70
80
90
100
110
0 20 40 60 80 100
Figure 3 — Specified HI-side start up into load current and external capacitance
LO-Side Current (A)
HI-Side Voltage (V)
ILO_OUT_DC ILO_OUT_PULSE
0
5
10
15
20
25
30
35
40
45
50
400 430 460 490 520 550 580 610 640 670 700
LO-Side Power (W)
HI-Side Voltage (V)
PLO_OUT_DC PLO_OUT_PULSE
0
250
500
750
1000
1250
1500
1750
2000
2250
2500
400 430 460 490 520 550 580 610 640 670 700
Figure 1 — Specified thermal operating area
Figure 2 — Specified electrical operating area using rated RLO_HOT
1. The BCM in a VIA package is cooled through the non-pin-side case.
2. The thermal rating is based on typical measured device efficiency.
3. The case temperature in the graph is the measured temperature of the non-pin-side housing, such that the internal operating temperature
does not exceed 125°C.
BCM® in a VIA™ Package Rev 1.6
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PMBus® Reported Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Monitored Telemetry
• The current telemetry is only available in forward operation. The input and output current reported value is not supported in reverse operation.
Attribute PMBus Read Command Accuracy
(Rated Range)
Functional
Reporting Range Update Rate Reported Units
HI-Side Voltage (88h) READ_VIN ±5% (LL – HL) 130 to 780V 100µs VACTUAL = VREPORTED x 10–1
HI-Side Current (89h) READ_IIN ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) –0.85 to 4.4A 100µs IACTUAL = IREPORTED x 10–3
LO-Side Voltage [c] (8Bh) READ_VOUT ±5% (LL – HL) 8.125 to 48.75V 100µs VACTUAL = VREPORTED x 10–1
LO-Side Current (8Ch) READ_IOUT ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) –13.6 to 70A 100µs IACTUAL = IREPORTED x 10–2
LO-Side Resistance (D4h) READ_ROUT ±5% (50 – 100% of FL) at NL
±10% (50 – 100% of FL)(LL – HL) 5 to 40mΩ 100ms RACTUAL = RREPORTED x 10–5
Temperature [d] (8Dh) READ_TEMPERATURE_1 ±7°C (Full Range) –55 to 130ºC 100ms TACTUAL = TREPORTED
Variable Parameters
• Factory setting of all Thresholds and Warning limits listed below are 100% of specified protection values.
• Variables can be written only when module is disabled with VHI < VHI_UVLO– and external bias (VDDB) applied.
• Module must remain in a disabled mode for 3ms after any changes to the variables below to allow sufficient time to commit changes to EEPROM.
Attribute PMBus Command Conditions / Notes Accuracy
(Rated Range)
Functional
Reporting
Range
Default
Value
HI-Side Overvoltage
Protection Limit (55h) VIN_OV_FAULT_LIMIT VHI_OVLO– is automatically 3%
lower than this set point ±5% (LL – HL) 130 – 750V 100%
HI-Side Overvoltage
Warning Limit (57h) VIN_OV_WARN_LIMIT ±5% (LL – HL) 130 – 750V 100%
HI-Side Undervoltage
Protection Limit (D7h) DISABLE_FAULTS Can only be disabled to a preset
default value ±5% (LL – HL) 130 – 400V 100%
HI-Side Overcurrent
Protection Limit (5Bh) IIN_OC_FAULT_LIMIT ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) 0 – 4.4A 100%
HI-Side Overcurrent
Warning Limit (5Dh) IIN_OC_WARN_LIMIT ±20% (10 – 20% of FL)
±5% (20 – 133% of FL) 0 – 4.4A 100%
Overtemperature
Protection Limit (4Fh) OT_FAULT_LIMIT Internal temperature ±7°C (Full Range) 0 – 125°C 100%
Overtemperature
Warning Limit (51h) OT_WARN_LIMIT Internal temperature ±7°C (Full Range) 0 – 125°C 100%
Turn On Delay (60h) TON_DELAY Additional time delay to the
undervoltage start up delay ±50µs 0 – 100ms 0ms
[c] Default READ LO Side Voltage returned when unit is disabled = –300V.
[d] Default READ Temperature returned when unit is disabled = –273°C.
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Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted. Please note: For chassis mount model, Vicor part
number 42550 will be needed for applications requiring the use of the signal pins. Signal cable 42550 is rated up to five insertions and extractions.
To avoid unnecessary stress on the connector, the cable should be appropriately strain relieved.
EXT. BIAS (VDDB) Pin
• VDDB powers the internal controller.
• VDDB needs to be applied to enable and disable the BCM through PMBus® control (using OPERATION COMMAND), and to adjust warning and
protection thresholds.
• VDDB voltage not required for telemetry; however, if VDDB is not applied, telemetry information will be lost when VIN is removed.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
INPUT
Regular
Operation
VDDB Voltage VVDDB 4.5 5 9 V
VDDB Current Consumption IVDDB 50 mA
Start Up
Inrush Current Peak IVDDB_INR VVDDB slew rate = 1V/µs 3.5 A
Turn-On Time tVDDB_ON From VVDDB_MIN to PMBus active 1.5 ms
Address (ADDR) Pin
• This pin programs the address using a resistor between ADDR pin and signal ground.
• The address is sampled during start up and is stored until power is reset. This pin programs only a Fixed and Persistent address.
• This pin has an internal 10kΩ pullup resistor to 3.3V.
• 16 addresses are available. The range of each address is 206.25mV (total range for all 16 addresses is 0 – 3.3V).
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
MULTI‐LEVEL
INPUT
Regular
Operation
ADDR Input Voltage VSADDR See address section 0 3.3 V
ADDR Leakage Current ISADDR Leakage current 1 µA
Start Up ADDR Registration Time tSADDR From VVDDB_MIN 1 ms
SGND Pin
• All PMBus interface signals (SCL, SDA, ADDR) are referenced to SGND pin.
• SGND pin also serves as return pin (ground pin) for VDDB.
• Keep SGND signal separated from the low-voltage side power return terminal (–LO) in electrical design.
BCM® in a VIA™ Package Rev 1.6
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SCL
SDA
SSP
P
VIH
VIL
VIH
VIL
tBUF
tHD,STA
tLOW tR
tHD,DAT
tHIGH
tF
tSU,DAT tSU,STA tSU,STO
Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High-power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is not supported.
• PMBus® command compatible.
Signal Type State Attribute Symbol Conditions / Notes Min Typ Max Unit
DIGITAL
INPUT/OUTPUT
Regular
Operation
Electrical Parameters
Input Voltage Threshold VIH 2.1 V
VIL 0.8 V
Output Voltage Threshold VOH 3 V
VOL 0.4 V
Leakage Current ILEAK_PIN Unpowered device 10 µA
Signal Sink Current ILOAD VOL = 0.4V 4 mA
Signal Capacitive Load CITotal capacitive load of
one device pin 10 pF
Signal Noise Immunity VNOISE_PP 10 – 100MHz 300 mV
Timing Parameters
Operating Frequency FSMB Idle state = 0Hz 10 400 kHz
Free Time Between
Stop and Start Condition tBUF 1.3 µs
Hold Time After Start or
Repeated Start Condition tHD:STA First clock is generated
after this hold time 0.6 µs
Repeat Start Condition
Set-Up Time tSU:STA 0.6 µs
Stop Condition Set-Up Time tSU:STO 0.6 µs
Data Hold Time tHD:DAT 300 ns
Data Set-Up Time tSU:DAT 100 ns
Clock Low Timeout tTIMEOUT 25 35 ms
Clock Low Period tLOW 1.3 µs
Clock High Period tHIGH 0.6 50 µs
Cumulative Clock Low
Extend Time tLOW:SEXT 25 ms
Clock or Data Fall Time tF20 300 ns
Clock or Data Rise Time tR20 300 ns
Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted. Please note: For chassis mount model, Vicor part
number 42550 will be needed for applications requiring the use of the signal pins. Signal cable 42550 is rated up to five insertions and extractions.
To avoid unnecessary stress on the connector, the cable should be appropriately strain relieved.
BCM® in a VIA™ Package Rev 1.6
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Timing Diagram (Forward Direction)
+VHI
INPUT
+VLO
OPERATION COMMAND OFF
OPERATION COMMAND ON
SHORT CIRCUIT EVENT
OUTPUT
STARTUP OVERVOLTAGE OPERATION
COMMAND
CONTROL
OVERCURRENT
SHUTDOWN
VHI_OVLO-
VHI_OVLO+
VHI_UVLO+
VµC_ACTIVE
VNOM
VHI_UVLO-
tLO_OUT_SCP
tAUTO_RESTART
> tHI_UVLO+_DELAY
tHI_UVLO+_DELAY
HI SIDE TURN OFF
LO SIDE TURN ON
HI SIDE TURN ON
HI SIDE OVERVOLTAGE
HI SIDE RESTART
CONTROLER INITIALIZE
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
Application Characteristics
Temperature controlled via pin-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (high-voltage side to low-voltage side). See associated figures for general trend data.
HI to LO,
Power Dissipation (W)
HI-Side Input Voltage (V)
–40°C25°C 70°C
TCASE:
0
3
6
9
12
15
18
21
24
27
30
400 430 460 490 520 550 580 610 640 670 700
Case Temperature (ºC)
400V 544V 700V
HI to LO,
Full-Load Efficiency (%)
VHI_DC:
94.0
94.5
95.0
95.5
96.0
96.5
97.0
97.5
98.0
–40 –20 0 20 40 60 80 100
HI to LO, Efficiency (%)
LO-Side Output Current (A)
400V 544V 700V
VHI_DC:
79
81
83
85
87
89
91
93
95
97
99
0 4 8 12 16 20 24 28 32 36 40
Figure 4 — No-load power dissipation vs. VHI_DC Figure 5 — Full-load efficiency vs. temperature
Figure 6 — Efficiency at TCASE = –40°C
LO-Side Output Current (A)
400V 544V 700V
0
8
16
24
32
40
48
56
64
72
80
VHI_DC:
HI to LO,
Power Dissipation (W)
0 4 8 12 16 20 24 28 32 36 40
HI to LO, Efficiency (%)
LO-Side Output Current (A)
400V 544V 700V
VHI_DC:
79
81
83
85
87
89
91
93
95
97
99
0 4 8 12 16 20 24 28 32 36 40
Figure 7 — Power dissipation at TCASE = –40°C
LO-Side Output Current (A)
400V 544V 700V
0
8
16
24
32
40
48
56
64
72
80
VHI_DC:
HI to LO,
Power Dissipation (W)
0 4 8 12 16 20 24 28 32 36 40
Figure 8 — Efficiency at TCASE = 25°C Figure 9 — Power dissipation at TCASE = 25°C
BCM® in a VIA™ Package Rev 1.6
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Application Characteristics (Cont.)
Temperature controlled via pin-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (high-voltage side to low-voltage side). See associated figures for general trend data.
HI to LO, Efficiency (%)
LO-Side Output Current (A)
400V 544V 700V
VHI_DC:
79
81
83
85
87
89
91
93
95
97
99
0 4 8 12 16 20 24 28 32 36 40
Figure 10 — Efficiency at TCASE = 70°C
LO-Side Output Current (A)
400V 544V 700V
0
8
16
24
32
40
48
56
64
72
80
VHI_DC:
HI to LO,
Power Dissipation (W)
0 4 8 12 16 20 24 28 32 36 40
Case Temperature (ºC)
40AILO_DC:
0
5
10
15
20
25
–40 –20 0 20 40 60 80 100
HI to LO,
Output Resistance (mΩ)
Figure 11 — Power dissipation at TCASE = 70°C
LO-Side Output
Voltage Ripple (mVpk-pk)
LO-Side Output Current (A)
544V
VHI_DC:
0
40
80
120
160
200
240
280
320
360
400
0 4 8 12 16 20 24 28 32 36 40
Figure 12 — RLO vs. temperature; nominal VHI_DC
ILO_DC = 40A
Figure 13 — VLO_OUT_PP vs. ILO_DC ; no external CLO_OUT_EX T.
Board-mounted module, scope setting:
20MHz analog BW
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
Figure 15 — 0 – 40A transient response: no external CHI_IN_EXT,
no external CLO_OUT_EX T
Figure 14 — Full-load LO-side voltage ripple, no external CHI_IN_EXT;
no external CLO_OUT_EX T. Board-mounted module,
scope setting: 20MHz analog BW
Figure 16 — 40 – 0A transient response: no external CHI_IN_EXT,
no external CLO_OUT_EX T
Figure 17 — Start up from application of VHI_DC = 544V, 20% ILO_DC,
100% CLO_OUT_ EXT
Figure 18 — Start up from application of OPERATION COMMAND
with pre-applied VHI_DC = 700V, 20% ILO_DC,
100% CLO_OUT_ EXT
Application Characteristics (Cont.)
Temperature controlled via pin-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (high-voltage side to low-voltage side). See associated figures for general trend data.
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Mechanical
Length L Lug (Chassis) Mount 110.30 [4.34] 110.55 [4.35] 110.80 [4.36] mm [in]
Length L PCB (Board) Mount 112.51 [4.43] 112.76 [4.44] 113.01 [4.45] mm [in]
Width W 35.29 [1.39] 35.54 [1.40] 35.79 [1.41] mm [in]
Height H 9.019 [0.355] 9.40 [0.37] 9.781 [0.385] mm [in]
Volume Vol Without heatsink 36.93 [2.25] cm3 [in3]
Weight W 145 [5.115] g [oz]
Pin Material C145 copper
Underplate Low-stress ductile Nickel 50 100 µin
Pin Finish (Gold) Palladium 0.8 6 µin
Soft Gold 0.12 2
Pin Finish (Tin) Whisker-resistant matte Tin 200 400 µin
Thermal
Operating Internal Temperature TINT
BCM4414xG0F4440yzz (T-Grade) –40 125
°C
BCM4414xG0F4440yzz (C-Grade) –20 125
BCM4414xG0F4440yzz (M-Grade) –55 125
Operating Case Temperature TCASE
BCM4414xG0F4440yzz (T-Grade),
derating applied, see safe thermal
operating area
–40 100
°C
BCM4414xG0F4440yzz (C-Grade),
derating applied, see safe thermal
operating area
–20 100
BCM4414xG0F4440yzz (M-Grade),
derating applied, see safe thermal
operating area
–55 100
Thermal Resistance Pin Side θINT_PIN_SIDE
Estimated thermal resistance to
maximum temperature internal
component from isothermal pin/
terminal-side housing
1.5 °C/W
Thermal Resistance Housing θHOU
Estimated thermal resistance of thermal
coupling between the pin-side and
non-pin-side case surfaces
0.28 °C/W
Thermal Resistance Non-Pin Side θINT_NON_PIN_SIDE
Estimated thermal resistance to
maximum temperature internal
component from isothermal non-pin/
non-terminal housing
1.6 °C/W
Thermal Capacity 54 Ws/°C
Assembly
Storage Temperature TST
BCM4414xG0F4440yzz (T-Grade) –40 125
°CBCM4414xG0F4440yzz (C-Grade) –40 125
BCM4414xG0F4440yzz (M-Grade) –65 125
ESD Withstand
ESDHBM
Human Body Model,
“ESDA / JEDEC JDS-001-2012” Class I-C
(1kV to < 2kV)
1000
ESDCDM
Charge Device Model,
“JESD 22-C101-E” Class II (200V to
< 500V)
200
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
General Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TCASE ≤ 100°C (T-Grade). All other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Safety
Isolation Capacitance CHI_LO Unpowered unit 620 780 940 pF
Isolation Resistance RHI_LO At 500VDC 10 MΩ
MTBF
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
1.5 MHrs
Telcordia Issue 2 - Method I Case III;
25°C Ground Benign, Controlled 1.8 MHrs
Agency Approvals / Standards
cTÜVus EN 60950-1
cURus UL 60950-1
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
BCM® in a VIA™ Package Rev 1.6
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BCM in a VIA Package
The BCM uses a high-frequency resonant tank to move energy
from the high-voltage side to the low-voltage side and vice
versa. The resonant LC tank, operated at high frequency, is
amplitude modulated as a function of the HI-side voltage and
the LO-side current. A small amount of capacitance embedded
in the high-voltage-side and low-voltage-side stages of the
module is sufficient for full functionality and is key to achieving
high power density.
The BCM4414xG0F4440yzz can be simplified into the model
shown in Figure 19.
At no load:
K represents the “turns ratio” of the BCM.
Rearranging Equation 1:
In the presence of a load, VLO is represented by:
and ILO is represented by:
RLO represents the impedance of the BCM and is a function of the
RDS_ON of the HI-side and LO-side MOSFETs, PC board resistance
of HI-side and LO-side boards and the winding resistance of the
power transformer. IHI_Q represents the HI-side quiescent current of
the BCM controller, gate drive circuitry and core losses.
The effective DC voltage transformer action provides additional
interesting attributes. Assuming that RLO = 0Ω and IHI_Q = 0A,
Equation 3 now becomes Equation 1 and is essentially load
independent, resistor R is now placed in series with VHI.
The relationship between VHI and VLO becomes:
Substituting the simplified version of Equation 4
(IHI_Q is assumed = 0A) into Equation 5 yields:
This is similar in form to Equation 3, where RLO is used to represent
the characteristic impedance of the BCM. However, in this case a
real resistor, R, on the high-voltage side of the BCM is effectively
scaled by K2 with respect to the low-voltage side.
Assuming that R = 1Ω, the effective R as seen from the low-voltage
side is 3.9mΩ, with K = 1/16.
R
SAC
K = 1/32
VinVout
+
–
VHI
VLO
R
BCM
K = 1/16
Figure 20 — K = 1/16 BCM with series HI-side resistor
+
–
+
–
VLO
VHI
V•I
K
+
–
+
–
IHI_Q
RLO
IHI
K • ILO
ILO
K • VHI
Figure 19 — BCM DC model (Forward Direction)
VLO = VHI • K (1)
K =
V
LO
V
HI
(2)
(4)
IHI – IHI_Q
K
ILO =
VLO = VHI • K – ILO • RLO (3)
(5)VLO =
(
VHI – IHI • R
)
• K
(6)VLO = VHI • K – ILO • R • K2
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
A similar exercise can be performed with the addition of a
capacitor or shunt impedance at the high-voltage side of the
BCM. A switch in series with VHI is added to the circuit. This is
depicted in Figure 21.
A change in VHI with the switch closed would result in a change in
capacitor current according to the following equation:
Assume that with the capacitor charged to VHI, the switch is
opened and the capacitor is discharged through the idealized
BCM. In this case,
substituting Equation 1 and 8 into Equation 7 reveals:
The equation in terms of the LO-side has yielded a K2 scaling factor
for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger
capacitance on the low-voltage side when expressed in terms
of the high-voltage side. With K = 1/16 as shown in Figure 21,
C = 1µF would appear as C = 256µF when viewed from the
low-voltage side.
Low impedance is a key requirement for powering a high-current,
low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a BCM
between the regulation stage and the point-of-load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, these benefits are
not achieved if the series impedance of the BCM is too high. The
impedance of the BCM must be low, i.e., well beyond the crossover
frequency of the system.
A solution for keeping the impedance of the BCM low involves
switching at a high frequency. This enables the use of small
magnetic components because magnetizing currents remain low.
Small magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
The two main terms of power loss in the BCM module are:
n No-load power dissipation (PHI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
n Resistive loss (PRLO): refers to the power loss across
the BCM module modeled as pure resistive impedance.
Therefore,
The above relations can be combined to calculate the overall
module efficiency:
C
S
SAC
K = 1/32
VinVout
+
–
VHI
VLO
C
BCM
K = 1/16
Figure 21 — BCM with HI-side capacitor
S
(7)
dVHI
dt
IC (t) = C
dVLO
dt
C
K
2
ILO(t) = • (9)
IC = ILO • K (8)
PDISSIPATED = PHI_NL + PRLO (10)
P
LO_OUT
= P
HI_IN
– P
DISSIPATED
= P
HI_IN
– P
HI_NL
– P
RLO
(11)
=
()
P
LO_OUT
PHI_IN
P
HI_IN
– P
HI_NL
– P
RLO
PHI_IN
=η = (12)
VHI • IHI – PHI_NL – (ILO)2 • RLO
VHI • IHI
PHI_NL + (ILO)2 • RLO
VHI • IHI
= 1 –
BCM® in a VIA™ Package Rev 1.6
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Thermal Considerations
The VIA package provides effective conduction cooling from
either of the two module surfaces. Heat may be removed from
the pin-side surface, the non-pin-side surface or both. The extent
to which these two surfaces are cooled is a key component for
determining the maximum power that can be processed by a BCM,
as can be seen from the specified thermal operating area in
Figure 1. Since the BCM has a maximum internal temperature
rating, it is necessary to estimate this temperature based on a
system-level thermal solution. For this purpose, it is helpful to
simplify the thermal solution into a roughly equivalent circuit
where power dissipation is modeled as a current source, isothermal
surface temperatures are represented as voltage sources and the
thermal resistances are represented as resistors. Figure 22 shows
the “thermal circuit” for the BCM in a VIA package.
In this case, the internal power dissipation is PDISS, θINT_PIN_SIDE and
θINT_NON_PIN_SIDE are the thermal resistance characteristics of the
BCM and the pin-side and non-pin-side surface temperatures are
represented as TC_PIN_SIDE and TC_NON_PIN_SIDE. It is interesting to
note that the package itself provides a high degree of thermal
coupling between the pin-side and non-pin-side case surfaces
(represented in the model by the resistor θHOU). This feature enables
two main options regarding thermal designs:
n Single-side cooling: the model of Figure 22 can be simplified by
calculating the parallel resistor network and using one simple
thermal resistance number and the internal power dissipation
curves; an example for non-pin-side cooling only is shown in
Figure 23.
In this case, θINT can be derived as follows:
n Double-side cooling: while this option might bring limited
advantage to the module internal components (given the
surface-to-surface coupling provided), it might be appealing
in cases where the external thermal system requires allocating
power to two different elements, such as heat sinks with
independent airflows or a combination of chassis/air cooling.
Current Sharing
The performance of the BCM is based on efficient transfer
of energy through a transformer without the need of closed
loop control. For this reason, the transfer characteristic can be
approximated by an ideal transformer with a positive temperature
coefficient series resistance.
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
When multiple BCM modules of a given part number are
connected in an array, they will inherently share the load current
according to the equivalent impedance divider that the system
implements from the power source to the point-of-load. Ensuring
equal current sharing among modules requires that BCM array
impedances be matched.
Some general recommendations to achieve matched array
impedances include:
n Dedicate common copper planes/wires within the PCB/Chassis
to deliver and return the current to the modules.
n Provide as symmetric a PCB/Wiring layout as possible
among modules
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
PDISS
+
–
–
s
s
+
θINT_PIN_SIDE
θINT_NON_
PIN_SIDE
θHOU
TC_PIN_SIDE
TC_NON_
PIN_SIDE
Figure 22 — Double-sided cooling thermal model
PDISS
+
–
θINT
s
s
TC_NON_
PIN_SIDE
Figure 23 — Single-sided cooling thermal model
θINT =
(
θ
INT_PIN_SIDE
+ θ
HOU
)
• θ
INT_NON_PIN_SIDE
θINT_PIN_SIDE + θHOU + θINT_NON_PIN_SIDE
(13)
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
Fuse Selection
In order to provide flexibility in configuring power systems, BCM in
a VIA package modules are not internally fused. Input line fusing
of BCM products is recommended at the system level to provide
thermal protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
n Current rating
(usually greater than maximum current of BCM module)
n Maximum voltage rating
(usually greater than the maximum possible input voltage)
n Ambient temperature
n Nominal melting I2t
n Recommend fuse: see safety agency approvals (HI side)
Reverse Operation
BCM modules are capable of reverse power operation. Once the
unit is started, energy will be transferred from the low-voltage
side back to the high-voltage side whenever the low side voltage
exceeds VHI • K. The module will continue operation in this fashion
as long as no faults occur.
The BCM4414xG0F4440yzz has not been qualified for continuous
operation in a reverse power condition. However, fault protections
that help to protect the module in forward operation will also
protect the module in reverse operation.
Transient operation in reverse is expected in cases where there is
significant energy storage on the low-voltage side and transient
voltages appear on the high-voltage side.
Dielectric Withstand
The chassis of the BCM in a VIA package is required to be
connected to Protective Earth when installed in the end
application and must satisfy the requirements of IEC 60950-1 for
Class I products.
Summary
The case is required to be connected to protective earth in the
final installation.
The construction of the BCM in a VIA package can be summarized
by describing it as a “Class II” component installed in a
“Class I” subassembly.
SELV
R
I
ChiP Isolation
High voltage side Low voltage side
Figure 25 — BCM in a ChiP™ package before final assembly in the
VIA package
BCM®1
R0_1
ZHI_EQ1 ZLO_EQ1
ZLO_EQ2
VLO
ZLO_EQn
ZHI_EQ2
ZHI_EQn
R0_2
R0_n
BCM®2
BCM®n
Load
DC
VHI
+
Figure 24 — BCM module array
SELV
ChiP
BI
RI
VIA HI Side Circuit
PE
+HI
-HI
+LO
-LO
FI
High voltage side Low voltage side
VIA LO Side Circuit
HV VIA Isolation Drawing
Figure 26 — BCM in a VIA package after final assembly
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
Filtering
The BCM in a VIA package has built-in single stage EMI filtering
located on the high-voltage side. The integrated EMI filtering
consists of a common mode choke and differential mode
capacitors. However, it does not include Y2 capacitors for
common mode filtering. Y2 common mode capacitors can be
added externally on the high-voltage side between +HI and PE
(Case), and –HI and PE (Case) to meet certain EMI requirements.
A typical test set-up block diagram for conducted emissions is
shown in Figure 27.
The integrated filtering reduces the voltage ripple on the
high-voltage side. External LO-side filtering can be added as
needed, with ceramic capacitance used as a LO-side bypass for
this purpose. BCM HI-side and LO-side voltage ranges shall not
be exceeded. An internal overvoltage function prevents operation
outside of the normal operating HI-side range. However, the BCM
is exposed to the applied voltage even when disabled, and must
withstand it. External transient protection circuitry may be required
to protect the BCM from overvoltage transients imposed by a
system that would exceed maximum ratings.
The source response is generally the limiting factor in the
overall system response, given the wide bandwidth of the BCM.
Anomalies in the response of the source will appear at the LO side
of the module multiplied by its K factor.
Total load capacitance at the LO side of the BCM shall not exceed
the specified maximum to ensure correct operation in start up.
Due to the wide bandwidth and small LO-side impedance of the
BCM, low frequency bypass capacitance and significant energy
storage may be more densely and efficiently provided by adding
capacitance at the HI-side of the BCM.
At frequencies less than 500kHz, the BCM appears as an
impedance of RLO between the source and load. Within this
frequency range, capacitance connected at the HI side appears as
an effective scaled capacitance on the LO side per the relationship
defined in Equation 14.
This enables a reduction in the size and number of capacitors used
in a typical system.
DC
Power
Supply
Screen
Room /
Filters
LISN
LISN
Single
VIA BCM
(DUT)
Load
EMI
Receiver
+HI
–HI
+LO
–LO
Figure 27 — Typical test set up block diagram for
Conducted Emissions
CLO =
C
HI
K
2(14)
BCM® in a VIA™ Package Rev 1.6
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System Diagram for PMBus® Interface
The controller of the BCM in a VIA package is referenced to the low-voltage-side signal ground (SGND).
The BCM in a VIA package provides the Host PMBus system with accurate telemetry monitoring and reporting, threshold and
warning limits adjustment, in addition to corresponding status flags. The standalone BCM is periodically polled for status by the host
PMBus. Direct communication to the BCM is enabled by a page command. For example, the page (0x00) prior to a telemetry inquiry
points to the controller data and page (0x01) prior to a telemetry inquiry points to the BCM parameters.
The BCM enables the PMBus compatible host interface with an operating bus speed of up to 400kHz. The BCM follows the PMBus
command structure and specification.
EXT_BIAS
SDA
SGND
SCL
ADDR
BCM in a VIA
Package
Host
SDA
SGND
SCL
5V
PMBus®
BCM® in a VIA™ Package Rev 1.6
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BCM4414xG0F4440yzz
PMBus® Interface
Refer to “PMBus Power System Management Protocol Specification
Revision 1.2, Part I and II” for complete PMBus specifications details
at http://pmbus.org.
Device Address
The PMBus address (ADDR Pin) should be set to one of the
predetermined 16 possible addresses shown in the table below
using a resistor between the ADDR pin and SGND pin.
The BCM accepts only a fixed and persistent address and does not
support SMBus address resolution protocol. At initial power-up, the
BCM controller will sample the address pin voltage and will keep
this address until device power is removed.
Reported DATA Formats
The BCM controller employs a direct data format where all
reported measurements are in Volts, Amperes, Degrees Celsius,
or Seconds. The host uses the following PMBus specification
to interpret received values metric prefixes. Note that the
COEFFICIENTS command is not supported:
Where:
X, is a “real world” value in units (A, V, °C, s)
Y, is a two’s complement integer received from the BCM controller
m, b and R are two’s complement integers defined as follows:
No special formatting is required when lowering the supervisory
limits and warnings.
ID Child
Address HEX Recommended
Resistor RADDR (Ω)
1 1010 000b 50h 487
2 1010 001b 51h 1050
3 1010 010b 52h 1870
4 1010 011b 53h 2800
5 1010 100b 54h 3920
6 1010 101b 55h 5230
7 1010 110b 56h 6810
8 1010 111b 57h 8870
9 1011 000b 58h 11300
10 1011 001b 59h 14700
11 1011 010b 5Ah 19100
12 1011 011b 5Bh 25500
13 1011 100b 5Ch 35700
14 1011 101b 5Dh 53600
15 1011 110b 5Eh 97600
16 1011 111b 5Fh 316000
Command Code m R b
TON_DELAY 60h 1 3 0
READ_VIN 88h 1 1 0
READ_IIN 89h 1 3 0
READ_VOUT [e] 8Bh 1 1 0
READ_IOUT 8Ch 1 2 0
READ_TEMPERATURE_1 [f] 8Dh 1 0 0
READ_POUT 96h 1 0 0
MFR_VIN_MIN A0h 1 0 0
MFR_VIN_MAX A1h 1 0 0
MFR_VOUT_MIN A4h 1 0 0
MFR_VOUT_MAX A5h 1 0 0
MFR_IOUT_MAX A6h 1 0 0
MFR_POUT_MAX A7h 1 0 0
READ_K_FACTOR D1h 65536 0 0
READ_BCM_ROUT D4h 1 5 0
1
X = • (Y • 10-R - b)
m
(
)
[e] Default READ LO-side voltage returned when BCM unit is disabled = –300V.
[f] Default READ Temperature returned when BCM unit is disabled = –273°C.
BCM® in a VIA™ Package Rev 1.6
Page 26 of 43 08/2020
BCM4414xG0F4440yzz
Supported Command List
Command Code Function Default Data Content Data Bytes
PAGE 00h Access BCM stored information 00h 1
OPERATION 01h Turn BCM on or off 80h 1
CLEAR_FAULTS 03h Clear all faults N/A None
CAPABILITY 19h PMBus® key capabilities set by factory 20h 1
OT_FAULT_LIMIT 4Fh [g] Overtemperature protection 64h 2
OT_WARN_LIMIT 51h [g] Overtemperature warning 64h 2
VIN_OV_FAULT_LIMIT 55h [g] High-voltage-side overvoltage protection 64h 2
VIN_OV_WARN_LIMIT 57h [g] High-voltage-side overvoltage warning 64h 2
IIN_OC_FAULT_LIMIT 5Bh [g] High-voltage-side overcurrent protection 64h 2
IIN_OC_WARN_LIMIT 5Dh [g] High-voltage-side overcurrent warning 64h 2
TON_DELAY 60h [g] Start up delay in addition to fixed delay 00h 2
STATUS_BYTE 78h Summary of faults 00h 1
STATUS_WORD 79h Summary of fault conditions 00h 2
STATUS_IOUT 7Bh Overcurrent fault status 00h 1
STATUS_INPUT 7Ch Overvoltage and undervoltage fault status 00h 1
STATUS_TEMPERATURE 7Dh Overtemperature and undertemperature
fault status 00h 1
STATUS_CML 7Eh PMBus communication fault 00h 1
STATUS_MFR_SPECIFIC 80h Other BCM status indicator 00h 1
READ_VIN 88h Reads HI-side voltage FFFFh 2
READ_IIN 89h Reads HI-side current FFFFh 2
READ_VOUT 8Bh Reads LO-side voltage FFFFh 2
READ_IOUT 8Ch Reads LO-side current FFFFh 2
READ_TEMPERATURE_1 8Dh Reads internal temperature FFFFh 2
READ_POUT 96h Reads LO-side power FFFFh 2
PMBUS_REVISION 98h PMBus compatible revision 22h 1
MFR_ID 99h BCM controller ID “VI” 2
MFR_MODEL 9Ah Internal controller or BCM model Part Number 18
MFR_REVISION 9Bh Internal controller or BCM revision FW and HW revision 18
MFR_LOCATION 9Ch Internal controller or BCM factory location “AP” 2
MFR_DATE 9Dh Internal controller or BCM manufacturing date “YYWW” 4
MFR_SERIAL 9Eh Internal controller or BCM serial number Serial Number 16
MFR_VIN_MIN A0h Minimum rated high side voltage Varies per BCM 2
MFR_VIN_MAX A1h Maximum rated high side voltage Varies per BCM 2
MFR_VOUT_MIN A4h Minimum rated low side voltage Varies per BCM 2
MFR_VOUT_MAX A5h Maximum rated low side voltage Varies per BCM 2
MFR_IOUT_MAX A6h Maximum rated low side current Varies per BCM 2
MFR_POUT_MAX A7h Maximum rated low side power Varies per BCM 2
READ_K_FACTOR D1h Reads K factor Varies per BCM 2
READ_BCM_ROUT D4h Reads low-voltage side output resistance Varies per BCM 2
SET_ALL_THRESHOLDS D5h [g] Set supervisory warning and protection thresholds 646464646464h 6
DISABLE_FAULT D7h [g] Disable overvoltage, overcurrent or
undervoltage supervisory faults 00h 2
[g] The BCM must be in a disabled state with VHI < VHI_UVLO– and VDDB applied during a write message.
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Command Structure Overview
Write Byte protocol:
The Host always initiates PMBus® communication with a START bit. All messages are terminated by the Host with a STOP bit. In a write
message, the parent sends the child device address followed by a write bit. Once the child acknowledges, the parent proceeds with the
command code and then similarly the data byte.
S Start Condition
Sr Repeated start Condition
Rd Read
Wr Write
X Indicated that field is required to have the value of x
A Acknowledge (bit may be 0 for an ACK or 1 for a NACK)
P Stop Condition
From Parent to Child
From Child to Parent
… Continued next line
Read Byte protocol:
A Read message begins by first sending a Write Command, followed by a REPEATED START Bit and a child Address. After receiving the
READ bit, the BCM controller begins transmission of the Data responding to the Command. Once the Host receives the requested Data, it
terminates the message with a NACK preceding a stop condition signifying the end of a read transfer.
Figure 1 — PAGE COMMAND (00h), WRITE BYTE PROTOCOL
Child AddressSWrACommand Code A
171181
x = 0x = 0x = 0
Data Byte PA
811
x = 0
Child AddressSWrACommand Code A
17 11 81
x = 0x = 0x = 0
Child AddressSr Rd AData Byte A
17 11 81
x = 1x =
0x
= 1
P
1
Figure 2 — ON_OFF_CONFIG COMMAND (02h), READ BYTE PROTOCOL
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Write Word protocol:
When transmitting a word, the lowest order byte leads the highest order byte. Furthermore, when transmitting a Byte, the least significant
bit (LSB) is sent last. Refer to System Management Bus (SMBus) specification version 2.0 for more details.
Note: Extended command and Packet Error Checking Protocols are not supported.
Read Word protocol:
Write Block protocol:
Child AddressSWrACommand Code
171181
x = 0x = 0x = 0
Data Byte Low
8
P
1
AData Byte High A
181
x = 0x = 0
A
Child AddressSWrACommand Code
171181
x = 0x = 0x = 0
Child AddressSr Rd AData Byte Low A
171181
x = 1x = 0x = 0
AP
1
Data Byte High A
81
x = 1
Figure 4 — MFR_VIN_MIN COMMAND (88h)_READ WORD PROTOCOL
Child AddressSWrACommand Code
17 11 81
x = 0x = 0x = 0
AData Byte 1A
181
...
x = 0x = 0
Byte Count = N
8
A
AData Byte NA
181
...
x = 0x = 0
Data Byte 2
8...
...
P
1
Figure 5 — SET_ALL_THRESHOLDS COMMAND (D5h)_WRITE BLOCK PROTOCOL
Figure 3 — TON_DELAY COMMAND (D6h)_WRITE WORD PROTOCOL
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Read Block protocol:
Write Group Command protocol:
Note that only one command per device is allowed in a group command.
Figure 6 — SET_ALL_THRESHOLDS COMMAND (D5h)_READ BLOCK PROTOCOL
Child AddressSWrACommand Code
17 11 81
x = 0x = 0x = 0First Device First Command
A
1
x = 0
Data Byte Low
8
Data Byte High A
81
x = 0One or more Data Bytes
A...
Child AddressSr Wr A Command Code
17 11 8 1
x = 0x = 0x = 0
Second Device Second Command
A
1
x = 0
Data Byte Low
8
Data Byte High A
8 1
x = 0One or more Data Bytes
A...
Child AddressSr Wr A Command Code
171181
x = 0x = 0x = 0
Nth Device Nth Command
A
1
x = 0
Data Byte Low
8
Data Byte High A
81
x = 0One or more Data Bytes
AP
Figure 7 — DISABLE_FAULT COMMAND (D7h)_WRITE
Child AddressSWrACommand Code
171181
x = 0x = 0x = 0
Child AddressSr Rd AData Byte = NA
171181
x = 1x = 0x = 0
...A
AData Byte 2A
181
...
x = 0x = 0
Data Byte 1
8...
...
AP
11
x = 1
Data Byte N
8
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Supported Commands Transaction Type
A direct communication to the BCM controller and a simulated
communication to non-PMBus® devices is enabled by a page
command. Supported command access privileges with a
pre-selected PAGE are defined in the following table. Deviation
from this table generates a communication error in
STATUS_CML register.
Page Command (00h)
The page command data byte of 00h prior to a command call will
address the BCM controller specific data and a page data byte
of 01h would broadcast to the BCM. The value of the Data Byte
corresponds to the pin name trailing number with the exception
of 00h and FFh.
OPERATION Command (01h)
The OPERATION command can be used to turn on and off
the connected BCM.
If synchronous start up is required in the system, it is recommended
to use the command from host PMBus in order to achieve
simultaneous array start up.
This command accepts only two data values: 00h and 80h. If any
other value is sent the command will be rejected and a CML Data
error will result.
Data Byte Description
00h BCM controller
01h BCM
Command Code
PAGE Data Byte
Access Type
00h 01h
PAGE 00h R/W R/W
OPERATION 01h R R/W
CLEAR_FAULTS 03h W W
CAPABILITY 19h R
OT_FAULT_LIMIT 4Fh R/W
OT_WARN_LIMIT 51h R/W
VIN_OV_FAULT_LIMIT 55h R/W
VIN_OV_WARN_LIMIT 57h R/W
IIN_OC_FAULT_LIMIT 5Bh R/W
IIN_OC_WARN_LIMIT 5Dh R/W
TON_DELAY 60h R/W
STATUS_BYTE 78h R/W R
STATUS_WORD 79h R R
STATUS_IOUT 7Bh R R/W
STATUS_INPUT 7Ch R R/W
STATUS_TEMPERATURE 7Dh R R/W
STATUS_CML 7Eh R/W
STATUS_MFR_SPECIFIC 80h R R/W
READ_VIN 88h R
READ_IIN 89h R R
READ_VOUT 8Bh R
READ_IOUT 8Ch R R
READ_TEMPERATURE_1 8Dh R R
READ_POUT 96h R R
PMBUS_REVISION 98h R
MFR_ID 99h R
MFR_MODEL 9Ah R R
MFR_REVISION 9Bh R R
MFR_LOCATION 9Ch R R
MFR_DATE 9Dh R R
MFR_SERIAL 9Eh R R
MFR_VIN_MIN A0h R R
MFR_VIN_MAX A1h R R
MFR_VOUT_MIN A4h R R
MFR_VOUT_MAX A5h R R
MFR_IOUT_MAX A6h R R
MFR_POUT_MAX A7h R R
READ_K_FACTOR D1h R
READ_BCM_ROUT D4h R
SET_ALL_THRESHOLDS D5h R/W
DISABLE_FAULT D7h R/W
7 6 5 4 3 2 1 0
Unit is On when asserted (default)
Reserved
1 0 0 0 0 0 0 0 b
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CLEAR_FAULTS Command (03h)
This command clears all status bits that have been previously set.
Persistent or active faults are re-asserted again once cleared. All
faults are latched once asserted in the BCM controller. Registered
faults will not be cleared when shutting down the BCM
powertrain by recycling the BCM high side voltage or sending
the OPERATION command.
CAPABILITY Command (19h)
The BCM controller returns a default value of 20h. This value
indicates that the PMBus® frequency supported is up to 400kHz
and that both Packet Error Checking (PEC) and SMBALERT# are
not supported.
OT_FAULT_LIMIT Command (4Fh),
OT_WARN_ LIMIT Command (51h),
VIN_OV_FAULT_ LIMIT Command (55h),
VIN_OV_WARN_ LIMIT Command (57h),
IIN_OC_FAULT_ LIMIT Command (5Bh),
IIN_OC_WARN_ LIMIT Command (5Dh)
The values of these registers are set in non-volatile memory and
can only be written when the BCM is disabled.
The values of the above mentioned faults and warnings are set by
default to 100% of the respective BCM model supervisory limits.
However, these limits can be set to a lower value. For example: In
order for a limit percentage to be set to 80%, one would send a
write command with a (50h) Data Word.
Any values outside the range of (00h – 64h) sent by a host will be
rejected, will not override the currently stored value and will set the
Unsupported Data bit in STATUS_CML.
The SET_ALL_THRESHOLDS COMMAND (D5h) combines in one
block overtemperature fault and warning limits, VHI overvoltage
fault and warning limits as well as ILO overcurrent fault and warning
limits. A delay prior to a read command of up to 200ms following a
write of new value is required.
The VIN_UV_WARN_LIMIT (58h) and VIN_UV_FAULT_LIMIT
(59h) are set by the factory and cannot be changed by the host.
However, a host can disable the undervoltage setting using the
DISABLE_FAULT COMMAND (D7h).
All FAULT_RESPONSE commands are unsupported. The BCM
powertrain supervisory limits and powertrain protection will behave
as described in the Electrical Specifications. In general, once a fault
is detected, the BCM powertrain will shut down and attempt to
auto-restart after a predetermined delay.
TON_DELAY Command (60h)
The value of this register word is set in non-volatile memory and
can only be written when the BCM is disabled.
The maximum possible delay is 100ms. Default value is set
to (00h). The reported value can be interpreted using the
following equation.
Staggering start up in an array is possible with the TON_DELAY
Command. This delay will be in addition to any start up delay
inherent in the BCM module. For example: start up delay from
application of VHI is typically 20ms. When TON_DELAY is greater
than zero, the set delay will be added to it.
7 6 5 4 3 2 1 0
Packet Error Checking is not supported
Maximum supported bus speed is 400kHz
The Device does not have SMBALERT# pin and does
not support the SMBus Alert Response protocol
Reserved
0 0 1 0 0 0 0 0 b
TON_DELAYACTUAL = tREPORTED • 10 -3(s)
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All fault or warning flags, if set, will remain asserted until
cleared by the host or once the BCM and VDDB power is
removed. This includes undervoltage fault, overvoltage fault,
overvoltage warning, overcurrent warning, overtemperature
fault, overtemperature warning, undertemperature fault, reverse
operation, communication faults and analog controller
shutdown fault.
Asserted status bits in all status registers, with the exception of
STATUS_WORD and STATUS_BYTE, can be individually cleared.
This is done by sending a data byte with one in the bit position
corresponding to the intended warning or fault to be cleared. Refer
to the PMBus® Power System Management Protocol Specification –
Part II – Revision 1.2 for details.
The POWER_GOOD# bit reflects the state of the device and does
not reflect the state of the POWER_GOOD# signal limits. The
POWER_GOOD_ON COMMAND (5Eh) and POWER_GOOD_OFF
COMMAND (5Fh) are not supported. The POWER_GOOD# bit is
set, when the BCM is not in the active state, to indicate that the
powertrain is inactive and not switching. The POWER_GOOD#
bit is cleared, when the BCM is in the active state, 5ms after the
powertrain is activated allowing for soft start to elapse.
POWER_GOOD# and OFF bits cannot be cleared as they always
reflect the current state of the device.
The Busy bit can be cleared using CLEAR_ALL Command (03h) or
by writing either data value (40h, 80h) to PAGE (00h) using the
STATUS_BYTE (78h).
Fault reporting, such as SMBALERT# signal output, and host
notification by temporarily acquiring bus parent status is
not supported.
If the BCM controller is powered through VDDB, it will retain the
last telemetry data and this information will be available to the user
via a PMBus Status request. This is in agreement with the PMBus
standard, which requires that status bits remain set until specifically
cleared. Note that in the case where the BCM VHI is lost, the status
will always indicate an undervoltage fault, in addition to any other
fault that occurred.
NONE OF THE ABOVE bit will be asserted if either the
STATUS_MFR_SPECIFIC (80h) or the High Byte of the
STATUS WORD is set.
STATUS_IOUT (7Bh)
Unsupported bits are indicated above. A one indicates a fault.
UNIT IS BUSY
UNIT IS OFF
Not Supported: VOUT_OV_FAULT
IOUT_OC_FAULT
TEMPERATURE FAULT OR WARNING
PMBus COMMUNCATION EVENT
NONE OF THE ABOVE
VIN_UV_FAULT
Not Supported: UNKNOWN FAULT OR WARNING
Not Supported: OTHER
Not Supported: FAN FAULT OR WARNING
POWER_GOOD Negated*
INPUT FAULT OR WARNING
IOUT/POUT FAULT OR WARNING
Not Supported: VOUT FAULT OR WARNING
STATUS_MFR_SPECIFIC
0111100011011110
Low ByteHigh Byte
STATUS_BYTE
STATUS_WORD
b
7 6 5 4 3 2 1 0
76543210
* equal to POWER_GOOD#
IOUT_OC_FAULT
Not Supported: IOUT_OC_LV_FAULT
IOUT_OC_WARNING
Not Supported: IOUT_UC_FAULT
Not Supported: In Power Limiting Mode
Not Supported: POUT_OP_FAULT
Not Supported: POUT_OP_WARNING
Not Supported: Current Share Fault
7 6 5 4 3 2 1 0
1 0 0 1 0 0 0 0 b
STATUS_BYTE (78h) and STATUS_WORD (79h)
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STATUS_INPUT (7Ch)
Unsupported bits are indicated above. A one indicates a fault.
STATUS_TEMPERATURE (7Dh)
Unsupported bits are indicated above. A one indicates a fault.
STATUS_CML (7Eh)
Unsupported bits are indicated above. A one indicates a fault.
The STATUS_CML data byte will be asserted when an unsupported
PMBus® command or data or other communication fault occurs.
STATUS_MFR_SPECIFIC (80h)
The reverse operation bit, if asserted, indicates that the BCM is
processing current in reverse. Reverse current reported value is
not supported.
The BCM has hardware protections and supervisory limits. The
hardware protections provide an additional layer of protection
and have the fastest response time. The Hardware Protections
Shutdown Fault, when asserted, indicates that at least one of the
powertrain protection faults is triggered. This fault will also be
asserted if a disabled fault event occurs after asserting any bit using
the DISABLE_FAULTS COMMAND.
The BCM communicates with its internal secondary microcontroller
via UART communication. If the BCM UART CML is asserted, it may
indicate a hardware or connection issue between the BCM and the
secondary microcontroller.
When the PAGE COMMAND (00h) data byte is equal to (00h), the
BCM Reverse operation, Analog Controller Shutdown Fault, and
BCM UART CML bit will return the result of the active BCM. The
BCM UART CML will also be asserted if the active BCM
stops responding. The BCM must communicate at least once
to the internal controller in order to trigger this FAULT. The
BCM UART CML can be cleared using the PAGE (00h) CLEAR_
FAULTS (03h) Command.
OT_FAULT
OT_WARNING
Not Supported: UT_WARNING
UT_FAULT
Reserved
Reserved
Reserved
Reserved
7 6 5 4 3 2 1 0
11010000b
Invalid Or Unsupported Command Received
Invalid Or Unsupported Data Received
Not Supported: Packet Error Check Failed
Not Supported: Memory Fault Detected
Reserved
Other Communication Faults
Not Supported: Other Memory Or Logic
Fault
Not Supported: Processor Fault Detected
7 6 5 4 3 2 1 0
1 1 0 0 0 0 1 0 b
Reserved
Reserved
Reserved
Reserved
BCM UART CML
Hardware Protections Shutdown Fault
BCM Reverse Operation
Reserved
7 6 5 4 3 2 1 0
0 0 0 0 0 1 1 1 b
PAGE Data Byte = (01h)
VIN_OV_FAULT
VIN_OV_WARNING
Not Supported: VIN_UV_WARNING
VIN_UV_FAULT
Not Supported: IIN_OC_FAULT
Not Supported: IIN_OC_WARNING
Not Supported: PIN_OP_WARNING
Not Supported: Unit Off For Insufficient
Input Voltage
7 6 5 4 3 2 1 0
1 1 0 1 0 0 0 0 b
Reserved
Reserved
Reserved
BCM at PAGE (01h) is present
BCM UART CML
Hardware Protections Shutdown Fault
BCM Reverse Operation
Reserved
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 b
PAGE Data Byte = (00h)
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READ_VIN Command (88h)
If PAGE data byte is equal to (01h), command will return the BCM’s
HI-side voltage in the following format:
READ_IIN Command (89h)
If PAGE data byte is equal to (01h), command will return the BCM’s
HI-side current in the following format:
If PAGE data byte is equal (00h), command will also return the
BCM’s HI-side current.
READ_VOUT Command (8Bh)
If PAGE data byte is equal to (01h), command will return the BCM’s
LO-side voltage in the following format:
READ_IOUT Command (8Ch)
If PAGE data byte is equal to (01h), command will return the BCM’s
LO-side current in the following format:
If PAGE data byte is equal (00h), command will also return the
BCM’s LO-side current.
READ_TEMPERATURE_1 Command (8Dh)
If PAGE data byte is equal to (01h), command will return the BCM’s
temperature in the following format:
If PAGE data byte is equal (00h), command will also return the
BCM’s temperature
READ_POUT Command (96h)
If PAGE data byte is equal to (01h), command will return the BCM’s
LO-side power in the following format:
If PAGE data byte is equal to (00h), command will also return the
BCM’s LO-side power.
MFR_VIN_MIN Command (A0h),
MFR_VIN_MAX Command (A1h),
MFR_VOUT_MIN Command (A4h),
MFR_VOUT_MAX Command (A5h),
MFR_IOUT_MAX Command (A6h),
MFR_POUT_MAX Command (A7h)
These values are set by the factory and indicate the device
HI-side/LO-side voltage and LO-side current range and LO-side
power capacity.
If the PAGE data byte is equal to (00h – 01h),commands report
the rated BCM HI-side voltage minimum and maximum in Volts,
LO-side voltage minimum and maximum in Volts, LO-side current
maximum in Amperes and LO-side power maximum in Watts.
VHI_ACTUAL = VHI_REPORTED • 10 -1(V)
IHI_ACTUAL = IHI_REPORTED • 10 -3(A)
VLO_ACTUAL = VLO_REPORTED • 10 -1(V)
ILO_ACTUAL = ILO_REPORTED • 10 -2(A)
TACTUAL = ±TREPORTED (°C)
PLO_ACTUAL = PLO_REPORTED (W)
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READ_K_FACTOR Command (D1h)
If PAGE data byte is equal to (01h), command will return the BCM’s
K factor in the following format:
The K factor is defined in the BCM to represent the ratio of the
transformer winding and hence is equal to VLO / VHI.
READ_BCM_ROUT Command (D4h)
If PAGE data byte is equal to (01h), command will return the BCM’s
LO-side resistance in the following format:
SET_ALL_THRESHOLDS Command (D5h)
The values of this register block are set in non-volatile memory and
can only be written when the BCM is disabled.
This command provides a convenient way to configure all of the
limits, or any combination of limits described previously using
one command.
VHI overvoltage, overcurrent and overtemperature values are all set
to 100% of the specified supervisory limits by default and can only
be set to a lower percentage.
To leave a particular threshold unchanged, set the corresponding
threshold data byte to a value greater than (64h).
DISABLE_FAULT Command (D7h)
Unsupported bits are indicated above. A one indicates that the
supervisory fault associated with the asserted bit is disabled.
The values of this register block are set in non-volatile memory and
can only be written when the BCM is disabled.
This command allows the host to disable the supervisory faults
and respective statuses. It does not disable the powertrain analog
protections or warnings with respect to the set limits in the
SET_ALL_THRESHOLDS Command.
The HI-side undervoltage can only be disabled to a pre-set low
limit as specified in the Monitored Telemetry Functional
Reporting Range.
K_FACTORACTUAL = K_FACTORREPORTED • 2 -16(V/V)
BCM_RLO_ACTUAL = BCM_RLO_REPORTED • 10 -5(Ω)
IOUT_OC_WARN_ LIMIT
IOUT_OC_FAULT_ LIMIT
VIN_OV_FAULT_ LIMIT
OT_WARN_LIMIT
OT_FAULT_LIMIT
VIN_OV_WARN_ LIMIT
5 4 3 2 1 0
64 64 64 64 64 64 h
SET_ALL_THRESHOLDS_BLOCK (6 Bytes)
Reserved
Reserved
IOUT_OC_FAULT
Reserved
Reserved
Reserved
Reserved
VIN_OV_FAULT
Reserved
Reserved
Reserved
Reserved
Reserved
VIN_UV_FAULT
Reserved
Reserved
0100000000101000
LSBMSB
DISABLE_FAULT
76543210
7 6 5 4 3 2 1 0
b
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The BCM Controller Implementation vs.
PMBus® Specification Rev 1.2
The BCM controller is an I2C™ compliant, SMBus compatible device
and PMBus command compliant device. This section denotes some
deviation, perceived as differences from the PMBus Part I and Part II
specification Rev 1.2.
1. The PMBus interface meets all Part I and II PMBus specification
requirements with the following differences to the
transport requirement.
2. The BCM accepts 38 PMBus command codes.
Implemented commands execute functions as described in the
PMBus specification.
nDeviations from the PMBus specification:
a. Section 15, fault related commands
• The limits and Warnings unit is implemented as a
percentage (%) a range from decimal (0 – 100) of the
factory set limits.
3. The unsupported PMBus command code
response as described in the Fault Management and Reporting:
nDeviations from the PMBus specification:
a. PMBus section 10.2.5.3, exceptions
• The busy bit of the STATUS_BYTE as implemented can
be cleared (80h). In order to maintain compatibility with
the specification, (40h) can also be used.
nManufacturer Implementation of the PMBus Spec:
a. PMBus section 10.5, setting the response to a detected
fault condition
• All powertrain responses are pre-set and cannot
be changed.
b. PMBus section 10.6, reporting faults and warnings
to the Host
• SMBALERT# signal and Direct PMBus Device to Host
Communication are not supported. However, the PMBus
interface will set the corresponding fault status bits and
will wait for the host to poll.
c. PMBus section 10.7, clearing a shutdown due to a fault
• There is no RESET pin or EN pin in the BCM. Cycling
power to the BCM will not clear a BCM Shutdown. The
BCM will clear itself once the fault condition is removed.
d. PMBus Section 10.8.1, corrupted data transmission faults:
• Packet error checking is not supported.
Unmet DC parameter Implementation vs SMBus spec
Symbol Parameter
PMBus
Interface
SMBus
Rev 2.0 Units
Min Max Min Max
VIL [a] Input Low Voltage – 0.99 – 0.8 V
VIH [a] Input High Voltage 2.31 – 2.1 VVDD_IN V
ILEAK_PIN [c] Input Leakage per Pin 10 22 – ±5 µA
Section Description
Response to Host STATUS_BYTE STATUS_CML
Notes
NAK FFh CML Other Fault Unsupported
Data
10.8.1 Corrupted data No response; PEC not supported
10.8.2 Sending too few bits X X
10.8.3 Reading too few bits X X
10.8.4 Host sends or reads too
few bytes X X
10.8.5 Host sends too many
bytes X X X
10.8.6 Reading too many bytes X X X
10.8.7 Device busy X X
Device will ACK own address
BUSY bit in STATUS_BYTE even if
STATUS_WORD is set
Data Transmission Faults Implementation
This section describes data transmission faults as implemented in the BCM controller.
[a] VVDD_IN = 3.3V
[c] VBUS = 5V
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Section Description
Response
to Host STATUS_BYTE STATUS_CML
Notes
NAK CML Other
Fault
Unsupported
Command
Unsupported
Data
10.9.1 Improperly set read bit
in the address byte X X X
10.9.2 Unsupported
command code X X X
10.9.3 Invalid or
unsupported data X X
10.9.4 Data out of range X X
10.9.5 Reserved bits No response; not a fault
Data Content Faults Implementation
This section describes data content fault as implemented in the BCM controller.
BCM® in a VIA™ Package Rev 1.6
Page 38 of 43 08/2020
BCM4414xG0F4440yzz
BCM in VIA Package Chassis (Lug) Mount Package Mechanical Drawing
)RUFKDVVLVPRXQWPRGHOV9LFRUSDUWQXPEHU
ZLOOEHQHHGHGIRUDSSOLFDWLRQVUHTXLULQJWKHXVHRIVLJQDOSLQV
127(6
8QOHVVRWKHUZLVHVSHFLILHGGLPHQVLRQVDUH,QFK>PP@
6HH3LQ&RQILJXUDWLRQDQG3LQ'HVFULSWLRQVHFWLRQVIRUSLQGHVLJQDWLRQV
1.171
29.750
.11
2.90
DIM 'A'
DIM 'B'
.15
3.86
THRU
TYP
INPUT
INSERT
(41816)
TO BE
REMOVED
PRIOR
TO USE
OUTPUT
INSERT
(41817)
TO BE
REMOVED
PRIOR
TO USE

5('

86(7<&2/8*25
(48,9)25,1387&211(&7,21
$//352'8&76
USE TYCO LUG #696049-1 OR EQUIVALENT
FOR PRODUCTS WITH - OUT RETURN TO CASE,
USE TYCO LUG #2-36161-6 OR EQUIVALENT
FOR ALL OTHER PRODUCTS.
1
2
3
4
DIM 'C'
23.98
609.14
.37±.015
9.40±.381
.010 [.254]
1.40
35.54
PRODUCT DIM ‘A’ DIM ‘B’ DIM ‘C’
3414 DCM 1.61 [40.93] .788 [20.005] 3.38 [85.93]
3714 DCM 1.61 [40.93] 1.150 [29.200] 3.75 [95.13]
3814 NBM –OUT RETURN TO CASE 1.02 [25.96] 1.277 [32.430] 3.76 [95.59]
3814 BCM –OUT RETURN TO CASE 1.02 [25.96] 1.277 [32.430] 3.76 [95.59]
4414 BCM 1.61 [40.93] 1.757 [44.625] 4.35 [110.55]
4414 BCM –OUT RETURN TO CASE 1.61 [40.93] 1.277 [32.430] 4.35 [110.55]
4414 UHV BCM 1.61 [40.93] 1.718 [43.625] 4.35 [110.55]
4414 PFM 1.61 [40.93] 1.757 [44.625] 4.35 [110.55]
4414 PFM 3kV 1.61 [40.93] 1.658 [42.110] 4.35 [110.55]
4914 PFM 2.17 [55.12] 1.757 [44.625] 4.91 [124.75]
BCM® in a VIA™ Package Rev 1.6
Page 39 of 43 08/2020
BCM4414xG0F4440yzz
BCM in VIA Package PCB (Board) Mount Package Mechanical Drawing
127(6
8QOHVVRWKHUZLVHVSHFLILHGGLPHQVLRQVDUH,QFK>PP@
6HH3LQ&RQILJXUDWLRQDQG3LQ'HVFULSWLRQVHFWLRQVIRUSLQGHVLJQDWLRQV
BOTTOM SIDE
1
2
3
4
10 12
11 13
TOP VIEW
(COMPONENT SIDE)
5
6
7
8
9
PRODUCT DIM 'A' DIM 'B' DIM 'C' DIM 'D' DIM 'E' DIM 'F' DIM 'G'
3414 DCM 1.61 [40.93] .788 [20.005] 3.38 [85.93] 2.988 [75.897] 3.47 [88.14] 1.439 [36.554] 3.251 [82.586]
3714 DCM 1.61 [40.93] 1.150 [29.200] 3.75 [95.13] 3.350 [85.092] 3.83 [97.34] 1.439 [36.554] 3.613 [91.781]
4414 BCM 1.61 [40.93] 1.757 [44.625] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.439 [36.554] 4.221 [107.206]
4414 UHV BCM 1.65 [41.93] 1.718 [43.625] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.479 [37.554] 4.221 [107.206]
4414 PFM 1.61 [40.93] 1.757 [44.625] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.439 [36.554] 4.221 [107.206]
4414 PFM 3kV 1.61 [40.93] 1.658 [42.110] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.439 [36.554] 4.221 [107.206]
4914 PFM 2.17 [55.12] 1.757 [44.625] 4.91 [124.75] 4.517 [114.741] 5.00 [126.96] 1.999 [50.777] 4.780 [121.430]
BCM® in a VIA™ Package Rev 1.6
Page 40 of 43 08/2020
BCM4414xG0F4440yzz
BCM in VIA Package PCB (Board) Mount Package Recommended Hole Pattern
127(6
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6HH3LQ&RQILJXUDWLRQDQG3LQ'HVFULSWLRQVHFWLRQVIRUSLQGHVLJQDWLRQV
2
1
11
10
13
12
4
3
SEE DETAIL 'A'
RECOMMENED HOLE PATTERN
DETAIL A
9
8
7
6
5
PRODUCT DIM 'A' DIM 'B' DIM 'C' DIM 'D' DIM 'E' DIM 'F' DIM 'G'
3414 DCM 1.61 [40.93] .788 [20.005] 3.38 [85.93] 2.988 [75.897] 3.47 [88.14] 1.439 [36.554] 3.251 [82.586]
3714 DCM 1.61 [40.93] 1.150 [29.200] 3.75 [95.13] 3.350 [85.092] 3.83 [97.34] 1.439 [36.554] 3.613 [91.781]
4414 BCM 1.61 [40.93] 1.757 [44.625] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.439 [36.554] 4.221 [107.206]
4414 UHV BCM 1.65 [41.93] 1.718 [43.625] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.479 [37.554] 4.221 [107.206]
4414 PFM 1.61 [40.93] 1.757 [44.625] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.439 [36.554] 4.221 [107.206]
4414 PFM 3kV 1.61 [40.93] 1.658 [42.110] 4.35 [110.55] 3.957 [100.517] 4.44 [112.76] 1.439 [36.554] 4.221 [107.206]
4914 PFM 2.17 [55.12] 1.757 [44.625] 4.91 [124.75] 4.517 [114.741] 5.00 [126.96] 1.999 [50.777] 4.780 [121.430]
BCM® in a VIA™ Package Rev 1.6
Page 41 of 43 08/2020
BCM4414xG0F4440yzz
4414 UHV VIA BCM TIM PAD Mechanical Drawing
1.54
39.12
1.26
32.00
2.13
54.15
1.72
43.64
.20
5.00
(4) PL.
1.17
29.72
.60
15.24
(2) PL.
4.76
120.79
.14
3.56
.04
1.14
FULL R
TYP
.020±.005
.500±.127
NOMINAL TIM
THICKNESS
NOTES:
1- RoHS COMPLIANT PER CST-0001 LATEST REVISION.
2- MATERIAL: BERGQUIST GAP PAD 5000 S35.
3- NOMINAL THICKNESS .020 [.500] EXCLUSIVE OF LINER
4- PART IS KISS CUT AND SUPPLIED WITH A REMOVABLE PROTECTIVE LINER ON BOTH SIDES.
5- LINEAR TOLERANCE: ±.02 [.51]
In chassis-mount applications or in board-mount applications with heat sink, an insulation layer of Gap Pad TIM (for example, Henkel
Bergquist Gap Pad 5000S35 thickness 20 thousands, or similar) is necessary to meet the creepage requirements from the high-voltage
terminals to the case. Vicor part number 45766 is the TIM Pad recommended for use with Vicor UHV BCM4414 VIA.
BCM® in a VIA™ Package Rev 1.6
Page 42 of 43 08/2020
BCM4414xG0F4440yzz
Revision Date Description Page Number(s)
1.0 07/05/17 Initial release n/a
1.1 10/06/17 Updated agency approvals
Updated TIM pad mechamical drawing
1, 18
41
1.2 01/16/18 Updated monitored telemetry technical information
Updated mechanical drawings
10
38 – 40
1.3 08/17/18 Updated mechanical drawings
Updated TIM pad note
38 – 40
41
1.4 11/25/18 Updated to include M-Grade option 1, 8, 9, 17
1.5 05/22/19
Updated features & benefits
Updated electrical specifications
Updated figure 12 description
Updated 80h command description
1
6, 7
15
33
1.6 08/06/20 Updated terminology 25, 27, 28, 29, 32
Revision History
BCM® in a VIA™ Package Rev 1.6
Page 43 of 43 08/2020
BCM4414xG0F4440yzz
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