FDU2572 - Fairchild Semiconductor

Septembe r 2002

FDD2572 / FDU2572 Rev. B

FDD2572 / FDU2572

N-Channel PowerTrench® MOSFET

150V, 29A, 54mΩ

Features

•r

DS(ON) = 45mΩ (Typ.), VGS = 1 0V, ID = 9A

•Q

g(tot) = 26nC (Typ.), VGS = 10V

• Low Miller Charge

•Low Q

RR Body Diode

• UIS Capability (Single Pulse and Repetitive Pulse)

• Qualified to AEC Q101

Formerly developmental type 82860

Applications

• DC/DC converters and Off-Line UPS

• Distributed Power Architectu res and VRMs

• Primary Switch for 24V and 48V Systems

• High Voltage Synch ronous Recti fier

• Direct Injection / Diesel Injection Systems

• 42V Automotive Load Co ntrol

• Electr oni c Valve Train Systems

MOSFET Maximum Ratings TC = 25°C unl ess otherwise noted

Thermal C hara cterist ics

Thi s produ ct has bee n desi gned to mee t the ex treme te st condi ti ons an d environme nt de mande d by the au tomot ive indust ry. For a

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

certification.

Symbol Parameter Ratings Units

VDSS Drain to Source Voltage 150 V

VGS Gate to Sourc e Voltage ±20 V

Drain C urr e nt 29 A

Continuous (TC = 25oC, VGS = 10V)

Continuous (TC = 100oC, VGS = 1 0V) 20 A

Continuous (Tamb = 25oC, VGS = 10V, RθJA = 5 2oC/W) 4

Pulsed Figure 4 A

EAS Single Pulse Avalanche Energy (Note 1) 36 mJ

PDPower dissip atio n 135 W

Derate above 25oC0.9W/

TJ, TSTG Operating and Stor age Temperature -55 to 175 oC

RθJC Thermal Resistance Junct ion to Case TO-251, TO-252 1.11 oC/W

RθJA Thermal Resistance Junction to Ambient TO-251, TO-252 100 oC/W

RθJA Thermal R esistance Ju ncti on t o Ambien t TO-252, 1in2 co pper pad area 52 oC/W

GATE

(FLANGE)

DRAIN

SOURCE

TO-252AA

FDD SERIES

TO-251AA

FDU SERIES

(FLANGE)

DRAIN GATE

DRAIN

SOURCE

FDD2572 / FDU2572

Package Marking and Ordering Information

Electrical Characteristics TC = 25°C unless otherwise noted

Off Characteristics

On Characteristics

Dynamic Characteristic s

Resistive Switching Characteristics (VGS = 10V)

Drain-Source Diode Character istics

Notes:

1: Starting TJ = 25°C, L = 0.2mH, IAS = 19A.

Device Marking Device Package Reel Size Tape Width Quantity

FDD2572 FDD2572 TO-252AA 330mm 16mm 2500 units

FDU25 72 FDU257 2 TO- 251A A Tube N/A 75 units

Symbo l Parame ter Test Cond itio ns Min Typ Max Unit s

BVDSS Drain to Source Breakd own Voltage ID = 250µA, VGS = 0V 150 - - V

IDSS Zero Gate Voltage Drain Current VDS = 120V - - 1 µA

VGS = 0V TC = 150o--250

IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA2-4V

rDS(ON) Drain to Source On Resist ance ID=9A, VGS=10V - 0.045 0.054 ΩID = 4A, VGS = 6V, - 0.050 0.075

ID=9A, VGS=10V, TC=175oC - 0.126 0.146

CISS Input Capacitance VDS = 25V, VGS = 0V,

f = 1MHz

-1770- pF

COSS Output Capacitance - 183 - pF

CRSS Reverse Transfer Capacitance - 40 - pF

Qg(TOT) Tota l G ate Ch arg e at 10 V VGS = 0V to 10V

VDD = 75V

ID = 9A

Ig = 1.0m A

-2634nC

Qg(TH) Threshold Gate Charge VGS = 0V to 2V - 3.3 4.3 nC

Qgs Gate to Source Gate Charge - 8 - nC

Qgs2 Gate Char ge Threshold to Plateau - 5 - nC

Qgd Gate to Drain “Miller” Charge - 6 - nC

tON Turn-On Time

VDD = 75V, ID = 9A

VGS = 10V, RGS = 11.0Ω

--36ns

td(ON) Turn-On Delay Time - 11 - ns

trRise Time - 14 - ns

td(OFF) Turn-Off Delay Time - 31 - ns

tfFall Time - 14 - ns

tOFF Turn-Off Time - - 66 ns

VSD Source to Dra in Diode Vol tage ISD = 9A - - 1. 25 V

ISD = 4A - - 1.0 V

trr Rev erse Recov ery Time ISD = 9A , dISD/d t =100A/µs- -74ns

QRR Reverse Recovered Charge ISD = 9 A, dISD/dt =100A/µs - - 169 nC

FDD2572 / FDU2572

Typical Characteristics TC = 25°C unless otherwi s e note d

Figure 1. Normalized Power Diss ipation vs

Ambient Temperature Figure 2. Maximu m Continuous Drain Curr ent vs

Case Temperature

Figure 3. Normalized M aximum Tr ansient Thermal Impedance

Figure 4. Peak Current Capability

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00255075100 175

0.2

0.4

0.6

0.8

1.0

1.2

125 150 0

25 50 75 100 125 150 175

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

VGS = 10V

0.01

0.1

1.0

10-4 10-3 10-2 10-1 100101

2.0

10-5

t, RECTANG ULAR PULSE DURATI ON (s)

ZθJC, NORMALIZED

THERMAL IMPEDANCE

NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

0.5

0.2

0.1

0.05

0.01

0.02

DUTY CYCLE - DESCENDING ORDER

SINGLE PULSE

100

10-5 10-4 10-3 10-2 10-1 100101

500

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

VGS = 10V

TC = 25oC

I = I25 175 - TC

150

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

FDD2572 / FDU2572

Figure 5. Forward Bi as Safe Oper ati ng Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 6. Unclam ped Inductive Switchi ng

Capability

Figure 7. Transfer Charact eristic s Figure 8. Satur ation Character istics

Figur e 9 . Dr ain t o So urce On Resis tance v s Dr ain

Current Figure 10. Normalized Drai n to Source On

Resist ance vs Junction Temperature

Typical Characteristics TC = 2 5°C unless otherwis e noted

0.1

100

1000

1 10 100 200

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAG E (V)

TJ = MAX RATED

TC = 25oC

SINGLE PULSE

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

10µs

10ms

1ms

100µs

0.1

100

0.001 0.01 0.1 1

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVAL ANCHE (ms)

STARTING TJ = 25oC

STARTING TJ = 150oC

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

ID, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

TJ = 175oC

TJ = 25oC

TJ = -55oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V

012345

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 6V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 5V

TC = 25oC

VGS = 7V

VGS = 10V

0102030

ID, DRAIN CURRENT (A)

VGS = 6V

VGS = 10V

DRAIN TO SOURCE ON RESISTANCE (m Ω)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

0.5

1.0

1.5

2.0

2.5

3.0

-80 -40 0 40 80 120 160 200

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

VGS = 10V, ID =9A

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

FDD2572 / FDU2572

Figur e 11. Normalized Gate Thre shold Voltage vs

Junction Temperature Figure 12. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

Figure 13. Capacitance vs Drain to Source

Voltage Figure 1 4. Gate Charge Waveforms for Constant

Gate Cur rents

Typical Characteristics TC = 2 5°C unless otherwis e noted

0.4

0.6

0.8

1.0

1.2

1.4

-80 -40 0 40 80 120 160 200

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

THRESHOLD VOLTAGE

0.9

1.0

1.1

1.2

-80 -40 0 40 80 120 160 200

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ID = 250µA

BREAKDOWN VOLTAGE

100

1000

0.1 1 10 150

1000

C, CAPACITANCE (pF)

VGS = 0V, f = 1MHz

CISS = CGS + CGD

COSS ≅ CDS + CGD

CRSS = CGD

VDS, DRAIN TO SOURCE VOLTAGE (V)

0 5 10 15 20 25 30

VGS, GATE TO SOURCE VOLTAGE (V)

Qg, GATE CHARGE (nC)

VDD = 75V

ID = 9A

ID = 4A

WAVEFORMS IN

DESCENDING ORDER:

FDD2572 / FDU2572

Test Circuits and Waveforms

Figure 15. Unclamped Energy Test Circuit Fi gure 16. Unclamped Energy Waveforms

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

Figure 19. Switching Time Test Ci rcuit Figure 20. Switching Time Waveforms

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 2V

Qg(TOT)

VGS = 10V

VDS

VGS

Ig(REF)

Qgs Qgd

Qgs2

VGS

RGS

DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%50%

10% PULSE WI DT H

VGS

FDD2572 / FDU2572

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the

thermal resistance of the heat dissipating path determines

the maxi mum al lowab le devi ce powe r di ssipat ion, PDM, in an

application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJM is never exceeded.

Equation 1 mathematically represents the relationship and

s erves as the basis for establishing the r ating of the part.

In using surface mount devices such as the TO-252

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

power dissipation ratings. Precise determination of PDM is

c omplex and influenced by many factors:

1. Mounting pa d area onto which the d evice is attached an d

wh ethe r the re is copp er o n on e sid e or bot h si des o f the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board or ienta tion.

6. For non steady state applications, the pulse width, the

duty cycle and the transient ther mal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 21

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

posit i on ed FR-4 bo ard with 1 oz c opp er aft er 100 0 se c on ds

of stea dy st ate powe r w ith n o air flow . Th is gr aph prov ides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using

Equation 2 or 3. Equation 2 is used for copper area defined

in inches square and equation 3 is for area in centimeter

square. The area, in square inches or square centimeters is

the top copper area including the gate and source pads.

(EQ. 1)

PDM

TJM TA

–()

RθJA

-----------------------------=

Area in Inches Squared

(EQ. 2)

RθJA 33.32 23.84

0.268 Area+()

-------------------------------------+

(EQ. 3)

RθJA 33.32 154

1.73 Area+()

----------------------------------+

Area in Centimeters Squared

100

125

0.01 0.1 1 10

Figure 21. Thermal Resistance vs Mounting

Pad Area

RθJA = 33.32+ 23.84/(0.268+Area) EQ.2

RθJA (oC/W)

AREA, TOP COPPER AREA in2 (cm2)

RθJA = 33.32+ 154/(1.73+Area) EQ.3

(0.645) (6.45) (64.5)(0.0645)

FDD2572 / FDU2572

PSPICE El ectrical M ode l

.SUBCKT FDD2572 2 1 3 ; rev April 2002

C A 12 8 5. 5e-10

Cb 1 5 14 7. 4e-10

Cin 6 8 1.7e-9

D bo dy 7 5 Dbod yMOD

Dbreak 5 11 Dbreak MOD

Dplc ap 10 5 Dpl capMO D

Ebreak 11 7 17 18 160

Ed s 14 8 5 8 1

Eg s 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtem p 20 6 18 22 1

It 8 17 1

Lgate 1 9 1.21e -9

Ldrai n 2 5 1.0e-9

Lsource 3 7 4.45e-9

RLgate 1 9 12. 1

R Ld rain 2 5 10

RLsource 3 7 44. 5

Mm e d 16 6 8 8 Mm edMOD

Mstro 16 6 8 8 Mst roM OD

Mwe ak 16 21 8 8 MweakMOD

Rbreak 17 18 Rbreak M O D 1

Rdrain 50 16 RdrainMOD 35e-3

Rgate 9 20 1. 6

RSLC1 5 51 R SLCMOD 1. 0e-6

RSLC2 5 50 1.0e3

Rsource 8 7 RsourceMOD 3.0e-3

Rvthres 22 8 R vt hresM OD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESL C 51 50 VAL UE = {(V (5,51)/ A BS( V (5,51)))*(P WR(V (5,51)/ (1e-6* 52), 3))}

.MODEL DbodyMOD D (IS=6.0E-11 N=1.14 RS=3.9e-3 TRS1=3.5e-3 TRS2=3.0e-6

+ CJO=1. 1e-9 M =0.63 TT= 6. 2e-8 X T I=4.5 )

.MO DE L DbreakM OD D (RS= 10 T RS 1=5.0e- 3 T RS2=-5. 0e-6)

.MODEL DplcapMOD D (CJO=3.5e-10 IS=1.0e-30 N=10 M=0.65)

.MO DE L M m edM OD NMOS (VT O=3.55 KP=3 IS=1e-40 N=1 0 T OX=1 L=1u W=1u RG=1.6 )

.MO DE L M st roMOD NM OS (VTO=4. 0 KP= 25 I S=1e-30 N=10 TOX = 1 L=1u W=1u)

.MO DE L M weakMO D NM OS (VT O=2.95 K P=0. 05 IS= 1e-30 N=10 T OX = 1 L=1u W=1u RG=16 RS=0. 1)

.MO DE L RbreakMOD RES (T C1=1.15e-3 TC2=-9.5 e-7)

.MO DE L Rdrai nM O D RE S (TC1=9. 0 e-3 TC2=2. 5e-5)

.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=2.5e-6)

.MO DE L Rsourc eM OD RES (TC1=4.0 e-3 TC 2=1.0 e-6)

.MO DE L Rvt hresM OD RE S (T C1=-4.1e-3 TC2=-1.0 e-5)

.MO DE L Rvt empMOD RE S (TC1=-4.0e -3 T C2=1.0e -6)

.M ODEL S1AMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 5. 0 VOFF =-3 .5 )

.M ODEL S1BMOD VSWITC H (RON= 1e- 5 ROFF = 0.1 VON= - 3. 5 VOFF =-5 .0 )

.M ODEL S2AMOD VSWITC H (RON= 1e- 5 ROFF =0. 1 VON=- 0. 5 VOF F=0.3)

.M ODEL S2BMOD VSWITC H (RON= 1e- 5 ROFF =0. 1 VON=0 .3 VOFF= -0.5)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IE EE P ower Elect roni cs Speci al i st Conf erence Recor ds, 1991, writte n by Wil liam J. Hepp and C. Frank

Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

FDD2572 / FDU2572

SABER Electrical Model

REV Apri l 200 2

ttemplate FDD257 2 n2,n1, n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=6.0e-11,nl=1.14,rs=3.9e-3,trs1=3.5e-3,trs2=3.0e-6,cjo=1.1e-9,m=0.63,tt=6.2e-8,xti=4.5)

dp.. m odel dbreakmod = (rs=10,trs 1=5.0e- 3,tr s2=-5.0e-6)

dp..model dplcapmod = (cjo=3.5e-10,isl=10.0e-30,nl=10,m=0.65)

m..model mmedmod = (type=_n,vto=3.55,kp=3,is=1e-40, tox=1)

m..model mstrongmod = (type=_n,vto=4.0,kp=25,is=1e-30, tox=1)

m..model mweakmod = (type=_n,vto=2.95,kp=0.05,is=1e-30, tox=1,rs=0.1)

sw_v cs p.. mo del s1amod = (ron=1e-5, roff= 0. 1,vo n=-5. 0,voff = -3.5 )

sw_v cs p.. mo del s1bmod = (ron=1e-5, roff= 0. 1,vo n=-3. 5,voff = -5.0 )

sw_v cs p.. mo del s2amod = (ron=1e-5, rof f=0. 1,vo n=-0. 5, vof f=0. 3)

sw_v cs p.. mo del s2bmod = (ron=1e-5, rof f=0. 1,vo n=0.3 ,v off= -0. 5)

c . ca n1 2 n8 = 5.5e -10

c.cb n15 n14 = 7.4e- 10

c.c in n6 n8 = 1.7e-9

dp.dbody n7 n5 = mod el =dbodymod

dp.dbreak n5 n11 = m odel =dbreak m od

dp.dplcap n10 n5 = model =dpl ca pm od

spe. ebreak n11 n7 n17 n18 = 160

spe. eds n14 n8 n5 n8 = 1

spe. egs n13 n8 n6 n8 = 1

spe. esg n6 n10 n6 n8 = 1

spe.evthres n6 n21 n19 n8 = 1

spe. evte mp n20 n6 n18 n22 = 1

i.it n8 n17 = 1

l.lg ate n1 n9 = 1.21e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 4.45e-9

res. rl gate n1 n9 = 12.1

res. rl drai n n2 n5 = 10

res. rl source n3 n7 = 44. 5

m.mmed n16 n6 n8 n8 = model =m m edm od, l=1u, w=1 u

m.ms t rong n16 n6 n8 n8 = m odel= m strongmo d, l=1u, w=1u

m.mw eak n16 n21 n8 n8 = mo del =m weakmod, l=1u, w=1u

res. rbreak n17 n18 = 1, tc1=1. 15e-3, tc2 =-9.5e-7

res. rdrai n n50 n16 = 35e-3, tc 1=9.0 e-3,tc2=2.5 e-5

r e s .rgat e n9 n2 0 = 1.6

res. rslc1 n5 n51 = 1. 0e-6, tc1 = 3. 0e-3,tc2=2. 5e-6

res. rslc2 n5 n50 = 1. 0e3

res. rsource n8 n7 = 3.0e-3, tc1 = 4. 0e-3,tc2=1.0 e-6

res. rvth res n22 n8 = 1, tc1=- 4.1e-3,tc 2=-1.0e-5

res.rvtemp n18 n19 = 1, tc1=-4.0e-3,tc2=1.0e-6

sw_v cs p.s1 a n6 n12 n13 n8 = model =s1amod

sw_v cs p.s1 b n13 n12 n13 n8 = m odel= s1 bm od

sw_v cs p.s2 a n6 n15 n14 n13 = m odel= s2 am od

sw_v cs p.s2 b n13 n15 n14 n13 = model =s2bm od

v.vbat n22 n19 = dc =1

equations {

i (n51->n50) +=iscl

iscl : v (n51, n50) = ((v(n5, n51)/ (1e-9+abs(v (n5,n 51))))*((abs(v (n5,n 51)*1e6/52))** 3))}

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK

DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

FDD2572 / FDU2572

SPICE Thermal Model

REV 2 6 April 2002

FDD2572

CTHERM1 TH 6 3.8e-3

CTH ERM2 6 5 4.0e-3

CTH ERM3 5 4 4.2e-3

CTH ERM4 4 3 4.3e-3

CTH ERM5 3 2 8.5e-3

CTH ERM6 2 T L 3.0e-2

RTHERM1 TH 6 5.5e-4

RTH ERM2 6 5 5.0e-3

RTH ERM3 5 4 4.5e-2

RTH ERM4 4 3 10.5e-2

RTH ERM5 3 2 3.7e-1

RTH ERM6 2 T L 3.8e-1

SABER Thermal Mod el

SABE R t herm al m odel F DD2572

template thermal_model th tl

the r m al_ c th , tl

{

cth er m.ctherm1 th 6 =3.8e -3

ctherm.ctherm2 6 5 =4.0e-3

ctherm.ctherm3 5 4 =4.2e-3

ctherm.ctherm4 4 3 =4.3e-3

ctherm.ctherm5 3 2 =8.5e-3

ctherm.ctherm6 2 tl =3.0e-2

rtherm.rtherm1 th 6 =5.5 e-4

r therm.rtherm2 6 5 =5.0e-3

r therm.rtherm3 5 4 =4.5e-2

r therm.rtherm4 4 3 =10.5 e-2

r therm.rtherm5 3 2 =3.7e-1

r therm.rtherm6 2 tl =3.8e -1

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

Rev. I1

TRADEMARKS

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intended to be an exhaustive list of all such trademarks.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life su pport devices or systems are devi ces or systems

wh ich, (a) ar e int ende d fo r s urgic al i mpla nt into the body ,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Defini ti on of Terms

ACEx™

ActiveArray™

Bottomless™

CoolFET™

CROSSVOLT™

DOME™

EcoSPARK™

E2CMOS™

EnSigna™

FACT™

FACT Quiet Series™

FAST®

FASTr™

FRFET™

GlobalOptoisolator™

GTO™

HiSeC™

I2C™

ImpliedDisconnect™

ISOPLANAR™

LittleFET™

MicroFET™

MicroPak™

MICROWIRE™

MSX™

MSXPro™

OCX™

OCXPro™

OPTOLOGIC®

OPTOPLANAR™

PACMAN™

POP™

Power247™

PowerTrench®

QFET™

QS™

QT Optoelectroni cs™

Quie t Series™

RapidConfigure™

RapidConnect™

SILENT SWITCHER®

SMART START™

SPM™

Stealth™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SyncFET™

TinyLogic™

TruTranslation™

UHC™

UltraFET®

VCX™

A cross the board. Around the world.™

T he Power Franchise™

P rogrammable Acti ve Droop™

Datasheet Identification Product Status Definition

Advance Informat ion Formativ e or In

Design This datasheet contains the design specifications f or

product development. Specifications may change in

any manner without notice.

Preliminary First Production This data s heet contain s preliminary data, and

supplementary data will be p ublished at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improv e

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconductor re serves the right to ma ke chan ges at

any time without notice in order to improve design.

Obsolete Not In P roduction This datas heet contain s specifications on a product

that has been discontinued b y Fa irchild s emicond uctor.

The datasheet is printed for reference information only.