L1OH* wo HI-8382 ARINC 429 DIFFERENTIAL LINE DRIVER General Description The HI-8382 bus interface device is a silicon gate CMOS device designed as a line driver in accordance with the ARINC 429 bus specifications. Inputs are provided for clocking and synchronization. These sig- nals are ANDd with the DATA inputs to enhance system performance and allow the HI-8382 to be used in a variety of ap- plications. Both logic and synchronization inputs feature built-in 2,000V minimum ESD input protection as well as TTL end CMOS compatibility. The differential outputs of the HI-8382 are independently program- mable to the ARINC 429 output rise and fall time specifications, for both high speed and low speed applications, through the use of two external capacitors. The output voltage swing is also adjus- table by the application of an external voltage to the Vprp input. On-chip overvoltage and short-circuit protection is provided for the differentia! outputs. The HI-8382 is intended for use with either of two companion CMOS devices, the HI-8282 ARINC 429 Serial Transmitter/Dual Receiver, or the HI-8482 ARINC 429 Dual Line Receiver. These devices provide the necessary data formatting between the system processor bus and the ARINC 429 protocol. All three products are readily available for both industrial and military applications. Please contact the Holt Sales Department for additional informa- tion, including HI-8282 and HI-8482 data sheets, Features e Low Power CMOS TTL and CMOS Compatible Inputs e Programmable Output Voltage Swing Adjustable ARINC Rise and Fall Times e Operates at Data Rates Up to 100 Kbits e Short Circuit and Overvoltage Protection Full Military Temperature Range and DESC Chin Topograph Oy pography evoke ewe A r cu Glee i wa. ah. = he fio ted _______ my 4 boone ee : OH , nae & = Lig oe a a MW, Se * OS ee mene se RIM St OE Rem ae MEN Function ARINC 429 DIFFERENTIAL LINE DRIVER Pin Configurations DATA (A) &&9 8 & 12 18 14 15 16 17 16 ge727 Rg 28 PIN CHIP CARRIERS (LCC & PLCC) (TOP VIEW) HOLT INTEGRATED CIRCUITSHI-8382 Functional Description The SYNC and CLOCK inputs establish data synchronization utilizing two AND gates, one for each data input. This built in feature allows the HI-8382 to be used in applications not requiring the HI-8282 companion circuit. Each logic input, including the power enable (STROBE) input, are TTL/CMOS compatible. Figure 1 illustrates a typical ARINC 429 bus application. Three power supplies are necessary to operate the HI-8382: + 15V, i5V and +S5V. The + SV supply powers the intemal bus current regulator and also provides a reference voltage that determines the output voltage swing. The differential output voltage swing will equal 2Vrer. If a value of Vrup other than +5V is needed, a separate + SV power supply is required for pin V1. With the DATA (A) input at a logic high and Data (B) input at a logic low, Aout will switch to the + Vper rail and Bout will switch to the - Vrer rail (a logic high state). Reversing the data input states will cause Aour to switch to the Vrsr rail and Bout to switch to the + Vrer rail (a logic low state). With both data input signals at a logic low state, the outputs will both switch to OV (null state). The driver output impedance is nominally 75 Ohms. The rise and fall times of the outputs can be calibrated through the selection of two extemal capacitor values that are connected to the Ca and Cp OATA (A) OJ DATA () o__ +5 > iW FIGURE 1. ARINC 429 BUS APPLICATION input pins. For high-speed operation (LOOKBPS), the values are typically Ca = Cg = 75 pF, while Ca = Cp = 500 pF is typical for Truth Table -speed operati 2.5 to 14KBPS). low tion (1 to 14KBPS) SYNC | CLOCK | DATA(A) | DATAQ) | Aour | Bour | COMMENTS The functional block diagram (Figure 2) shows the internal Zener x L x x ov Ov NULL diodes that provide overvoltage protection and the fuses that pro- L x x x ov ov NULL vide protection from short circuit. ih 7 L L ov Ov NULL The driver can be externally powered down by applying a logic H H L H Vaur | + Vrer Low high to the STROBE input pin. If this feature is not being used, the H H H L + Vrer | - Veer HIGH pin should be tied to ground. H H H H ov ov NULL Vner +Vv Ca four TT TT f {-~-~----- ~--, en ch oa our | Ty | LEVEL SHIFTER DRIVER (A) | | AND SLOPE | b| CONTROL (A) Pourn/2 | | CLOCK Tl l_ | | t | | sync = | | Ta oA | LI Tt | i } LEVEL SHIFTER Rou Fa | DATA (B) AND SLOPE oy | CONTROL (8 | | + ] DRIVER (8) { | l | | VA 4 CURRENT | OVER- | ly REGULATOR | vourace | l Ld I GND -V Ge Bour FIGURE 2. FUNCTIONAL BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS meme heneereninH wean mee Fr nent cien oe nen a Pee cee ate ret nare te iE Neamt nARM RG RAE EgonHI-8382 Pin Descriptions SYMBOL | FUNCTION DESCRIPTION SYMBOL | FUNCTION DESCRIPTION VREF POWER | THE REFERENCE VOLTAGE USED TO DETER- _V POWER | 15v 4 10% MINE THE OUTPUT VOLTAGE SWING. oD pOwER tow STROBE INPUT A LOGIC HIGH ON THIS INPUT PLACES THE +V POWER | +15V 410% DRIVER IN POWER DOWN MODE. Bour OUTPUT | ARINC OUTPUT TERMINAL B. SYNC INPUT SYNCHRONIZES DATA INPUTS. Cp INPUT CONNECTION POR DATA (B) SLEW-RATE DATA (A) INPUT DATA INPUT TERMINAL A. CAPACITOR. CA INPUT CONNECTION FOR DATA (A) SLEW-RATE DATA @) INPUT | DATA INPUT TERMINAL B. CAPACITOR. CLOCK INPUT SYNCHRONIZES DATA INPUTS Aour OUTPUT | ARINC OUTPUT TERMINAL A. Vi POWER | 5V 5% a Absolute Maximum Ratings Vop = +15V de +10%, All Voltages Referenced to GND PARAMETER SYMBOL CONDITIONS OPERATING RANGE | MAXIMUM | UNIT Differential Voltage Vor Vokage Between + V and V terminals 0 Vv Supply Voltages +V + 10.8 to + 16.5 v -V - 10.8 w- 16.5 v v1 +5 410% +7 v Voltage Reference VREF For ARINC 429 +5 45% 6 v For Applications Other Than ARINC 0 to 6 6 v Input Voltage Range VN 2 GND -03 v < Vi +603 v Output Short-Circuit Duration See NOTE: 1 Output Overvoltage Protection See NOTE: 2 Operating Temperature Range Ta 16 PIN DIP & 28 PIN LCC 55 to +125 c 28 PIN PLCC -40 wo +85 Cc Storage Temperature Range TstG Soldering, 10 seconds -65 w +150 +275 "Cc Lead Temperature c Junction Temperature - Ty +175 "Cc Power Dissipation @ + 25C Pp 16 PIN DIP Soe NOTE: 3 1.725 Ww 28 PIN LCC See NOTE: 3 1.120 Ww 28 PIN PLCC See NOTE: 3 2.143 w Thermal Resistance, DIA 16 PIN DIP 865 Cw Junction - to - Ambient 28 PIN LCC 133.7 CIW 28 PIN PLCC 70.0 Cw NOTE 1 ~ Heatsinking may be required for Output Short Circuit at + 125C and for LOOKBPS at + 125C. NOTE 2 The Fuses used for Output Overvoltage Protection may be blown by a fault at each output of greater than + 6.5V relative to GND. NOTE 3 Derate above + 25C, 11.5 mW/C for 16 PIN DIP, 7.5mW/C for 28 PIN LCC and 14.2mW/C for 28 PIN LCC. NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. 3 HOLT INTEGRATED CIRCUITSHI-8382 | oo DC Electrical Characteristics Ta = Operating Temperature Range (unless otherwise specified) PARAMETER SYMBOL CONDITIONS LIMITS UNIT MIN TYP MAX Supply Current, + V (Operating) Iocop (+V) | No Load (0 100KBPS) +11 mA Supply Current V (Operating) Iccop (-V) | No Load (0~ 100KBPS) -11 mA Supply Current V1 (Operating) Icocop (V1) No Load (0 ~ 100KBPS) 500 pa Supply Cusrent VREF (Operating) Icoop (Vrer) | No Load (0 100KBPS) 500 pA Supply Current + V (Power Down) Iccpp (+V) | STROBE = HIGH ~415 475 | pA Supply Current V (Power Down) Iccep (-V) STROBE = HIGH ~475 415 pa . Supply Current V (During Short Circuit Test) Isc (-V) Short to Ground See NOTE: 1 ~150 | mA Supply Current + V (During Shost Circuit Tost) Ise (+V) Shart to Ground See NOTE: 1 +150 | mA Output Short Cirenit Carrent (Output High) louse Short to Ground =Vean=0 Ses NOTE: 2 ~% mA Outpt Short Ciouit Current (Output Low) lous Short to Ground VMIN=0 See NOTE: 2 +90 mA Input Current (input High) In 10 pA Input Current (ingot Low) in 1.0 pa Output Voltage High (Output to Ground) Vou No Load (0 - 100KBPS) + var +Vear v - + Outpat Voltage Low (Output to Ground) Vou No Load (0 - 100KBPS) ~via vane v 7. + Output Voltage Null VNULL No Load (0 - 100KBPS) 750 +250 mV Input Capacitance Cn 15 pF NOTE: 1 Not tested, but characterized et initial device design and after major process and/or design change which affects this parameter. NOTE: 2 Interchangeability of force and sense is accoptable. Ree AC Electrical Characteristics +V = 15V, -V = -15V, Vi = Vrer = 5.0V, Ta = Operating Temperature Range (unless otherwise specified) PARAMETER SYMBOL CONDITIONS LIMITS UNIT : MIN__TYP MAX Rise Time (AouT, Bout) tR Ca = Cy = 7SpF . 1.0 20 ps Fall Time (Aout, Bout) tr Ca = Cp = 75pF 1.0 2.0 ys Propagation Delay Input to Outpat tPLH Ca = Cp = 75pF 3.0 ps Propagation Delay Input to Output (PHL Ca = Cp = 75pF 3.0 pis MTA (A) Far mJ m1 1 ow DATA, ov | ot Feel rm m1 ov / | ev Ca o + 475V TO +825V Aout OV Noe | t + Ver _____. ~ A75V TO ~5.25V NOTE: OUTPUTS UNLOADED FIGURE 3. SWITCHING WAVEFORMS HOLT INTEGRATED CIRCUITS 4HI-8382 HI-8382 Standard Packaging TERMINAL CONNECTIONS 16 PIN DIP 28 PIN LEADLESS CHIP CARRIER (LCC) PIN FIN 28 PIN PLASCTIC J-LEADED CHIP CARRIER (PLCC) 1 VREF 9 +V PIN PIN PIN PIN 2 STROBE 10 NAC 1 VREF g Nw 1S GND 22 Cg 3 SYNC 11 Bout 2 NIC Ca 16 +V 23 DATA (B) 4 DATA (A) 12 Ca 3 STROBE 10 N/C 17 Bour 24 NI 5 Ca 13 DATA @) 4 SYNC 1k NAC 18 NIC 25 CLOCK 6 AouT 14 CLOCK 5 NC 12 NC 19 NIC 26 NC 7 -Vv 15 NIC 6 DATA (A) 13 AOUT 20 NC 27 NI 8 GND 16 Vi 7 NIC 14 ~V 21 NIC 28 Vi 16 PIN DIP 840 MAK (21.34) MAX 200 MAX _ 005 MIN (5.06) MAX ina : a7 (130) MIN { : . Ti t } PLANE 265 + 045 | (673 4 1.14) O11 + 003 t (028 + 0.08) / oss ., | 205 + 015 \ me alky O14 ian : 097 O19 he + 100 BSC (778 + 0.3m) (1.92 038) (048 0.13) (254 BSC 28 PIN LEADLESS CHIP CARRIER (LCC) 020 INDEX osninpex f " eases | - rp 060 + 005 (27 019 4 AST t 460 MAX = (11.48 & 0.23) (1168) MAX 060 BAC T (1.27) BSC 4} ek 0O9R + .006 025 + 003 ~ 040 X45" 3PLS (0.29R + 0.18) as) 00 it (0.64 ;: 0.08) (1.02 X45" SPLS (ae t 025) 28 PIN PLASTIC J-LEADED CHIP CARRIER (PLCC) 045 X45" 045 X45" P PINS (1:03) a5 108 & 015 ame | gar + oan L q b iar emen q | ) 450 + .006 q p 490 + 008 faa 2 0.180) 4 + D 2.446 0.452) 028 + 002 q D (0.711 = 0.051) | TOR MEW 172 + 008 ven we | bk (4300 ; 0.208) (11.43 + 0.152) 490 + 006 (12.446 + 0.153) HOLT INTEGRATED CIRCUITSHI-8382 a Ordering Information . INDUSTRIAL TEMPERATURE RANGE (-40C to +85C) HI-8382C - 16 pin Ceramic DIP, Industrial Screen HI-8382J - 28 pin Plastic J-leaded PLCC, Industrial Screen HI-8382S - 28 pin Ceramic LCC, Industrial Screen MILITARY TEMPERATURE RANGE (-55C to +125C) HI-8382CT - 16 pin Ceramic DIP, Industrial Screen HI-8382JT - 28 pin Plastic PLCC, Industrial Screen HI-8382CM - 16 pin Ceramic DIP, w/o burn-in HI-8382ST - 28 pin Ceramic LCC, Industrial Screen HI-8382CM-01 - 16 pin Ceramic DIP, with bum-in HI-8382SM __- 28 pin Ceramic LCC, w/o bum-in HI-8382CM-02 - 16 pin Ceramic DIP, DESC HI-8382SM-0L - 28 pin Ceramic LCC, with burn-in (SMD #5962-868790 LEC) HI-8382SM-02 - 28 pin Ceramic LCC, DESC (SMD #5962-86879013C) Additional packaging and screening options are available upon request. Vendor CAGE Namber: 44270 NOTES: HOLT: INTEGRATED CIRCUITS Information given by HOLT is believed to be accurate and reliable. However, HOLT reserves the right to change product specifications at my time without notice. All devices sold by HOLT are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. HOLT makes no warranty, express, statutory, implied or by description regarding the information set herein or regarding the freedom of the described devices from patent infringement. Holt Integrated Circuits, Inc. / 45 Parker, Irvine, CA 92718 / (714) 859-8800 or (800) 222-HOLT 10/92/B HOLT INTEGRATED CIRCUITS 6SHNDUD GI1WwOIINI TTOH al (9L0' F 8Ih) Wo TOL) + (80S F FIP'OT) TOF OIF > (1S0 89") WO + SPT a (1S0 LS) , a) nonoonon , c 5 ds soso) aso" 8 AD : S zi" 9vyz1) Wo tle S00 + OOF fF 4 WOT & 5 Cc 5 (Is0 FL71) } ij | WO + 0s0" SPX SHO XK Sex so INI 1O id 1ON Nid { oyeusiseq odd] s8eyoug Pesee-IH / P28E8-1H IOTd DOLLS V'Id Nid-83/85/92 GLD HOLT. INTEGRATED CIRCUITS HI~8382J7 PIN ASSIGNMENTS (28-Pin J-Lead Plastic PLCC Package) PIN PIN PIN PIN NO. FUNCTION NO FUNCTION Ll VREF 15 GND 2 N/C 16 +V 3 STROBE 17 Bout 4 SYNC 13 . N/C 5 N/C 19 N/C 6 DATA (A) 20 N/C 7 N/C 21 N/C 8 N/C 22 CB 9 Ca 23 DATA (B) 10 N/C 24 N/C 11 N/C 25 CLOCK 12 N/C 26 N/C 13 Aout 27 N/C 14 -V 28 Vi 45 Parker, Irvine, CA 92718 (714) 859-8800 Fax #(714) 859-964332-PIN J-LEAD CERQUAD ~ HI-8382U / HI-8383U SERIES mimi ae - Cificirifg ~~ Ff F i C 1 317 1 32 T rl iC r] 0.488 0.450 0.420 +008 +008 +012 20 7 : C r C C | \ Y sooooooon |} =) 0.588 . | +.008 0.550 i +009 - , Flake ak | oe +009 0.040 0.019 0.050 typ. +.003 typ. M4. 9.520 +012 SIZE | FSCM/CAGE NO. | DOC. NO. REV. New A 44270 SCALE: None SHEET_2 OF 2PIN ASSIGNMENTS HI-8383U Series Packages PIN # FUNCTION 1 VREF 2 STROBE 3 SYNC 4 N/C 5 N/C 6 N/C 7 N/C 8 DATA (A) 9 C, 10 N/C 11 N/C 12 N/C 13 AOUT 14 N/C 15 -V 16 N/C 17 GND 18 +V 19 N/C 20 N/C 21 BOUT 22 N/C 23 N/C 24 C, 25 DATA (B) 26 N/C 27 N/C 28 N/C 29 N/C 30 CLOCK 31 V1 32 N/C