1
Features
•Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02/04
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•Internally Organized 256 x 8 (2K), 512 x 8 (4K)
•Two-wire Serial Interface
•Schmitt Trigger, Filtered Inputs for Noise Suppression
•Bidirectional Data Transfer Protocol
•100 kHz (1.8V) and 400 kHz (2.5V, 2.7V, 5V) Clock Rate
•8-byte Page (2K), 16-byte Page (4K) Write Modes
•Partial Page Writes Allowed
•Self-timed Write Cycle (5 ms Max)
•High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
•Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free Devices
Available
•8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP and 8-ball dBGA2 Packages
•Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers.
Description
The AT24C02A/04A provides 2048/4096 bits of serial electrically erasable and program-
mable read-only memory (EEPROM) organized as 256/512 words of 8 bits each. The
device is optimized for use in many industrial and commercial applications where low-
power and low-voltage operation are essential. The AT24C02A/04A is available in
space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TSSOP pack-
ages and is accessed via a two-wire serial interface. In addition, the entire family is
available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Table 1. Pin Configuration
Pin Name Function
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No-connect
Two-wire Serial
EEPROM
2K (256 x 8)
4K (512 x 8)
AT24C02A
AT24C04A
Rev. 0976Q–SEEPR–8/05
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-lead PDIP
8-lead SOIC
8-lead TSSOP
8-lead MAP
Bottom View
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
GND
8-ball dBGA2
Bottom View
2AT24C02A/04A
0976Q–SEEPR–8/05
Figure 1. Block Diagram
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that must be hardwired for the AT24C02A. As many as eight 2K devices
may be addressed on a single bus system. (Device addressing is discussed in detail
under Device Addressing, page 8).
Absolute Maximum Ratings*
Operating Temperature........................................ −40°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
STA R T
STOP
LOGIC
3
AT24C02A/04A
0976Q–SEEPR–8/05
The AT24C04A uses the A2 and A1 inputs for hardwire addressing, and a total of four
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
WRITE PROTECT (WP): The AT24C02A/04A have a WP pin that provides hardware
data protection. The WP pin allows normal read/write operations when connected to
ground (GND). When the WP pin is connected to VCC, the write protection feature is
enabled and operates as shown.
Table 2. Write Protect
Memory Organization AT24C02A, 2K SERIAL EEPROM: The 2K is internally organized with 32 pages of 8
bytes each. Random word addressing requires an 8-bit data word address.
AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16
bytes each. Random word addressing requires a 9-bit data word address.
Note: 1. This parameter is characterized and is not 100% tested.
WP Pin Status
Part of the Array Protected
24C02A 24C04A
At VCC Upper Half (1K) Array Upper Half (2K) Array
At GND Normal Read/Write Operations
Table 3. Pin Capacitance(1)
Applicable over recommended operating range from TAI = 25°C, f = 1.0 MHz, VCC = +1.8V
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
4AT24C02A/04A
0976Q–SEEPR–8/05
Note: 1. VIL min and VIH max are reference only and are not tested.
Table 4. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3Supply Voltage 2.7 5.5 V
VCC4 Supply Voltage 4.5 5.5 V
ICC Supply Current VCC = 5.0V READ at 100 kHz 0.4 1.0 mA
ICC Supply Current VCC = 5.0V WRITE at 100 kHz 2.0 3.0 mA
ISB1 Standby Current VCC = 1.8V VIN = VCC or VSS 0.6 3.0 µA
ISB2 Standby Current VCC = 2.5V VIN = VCC or VSS 1.4 4.0 µA
ISB3Standby Current VCC = 2.7V VIN = VCC or VSS 1.6 4.0 µA
ISB4 Standby Current VCC = 5.0V VIN = VCC or VSS 8.0 18.0 µA
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
ILO Output Leakage Current VOUT = VCC or VSS 0.05 3.0 µA
VIL Input Low Level (1) −0.6 VCC x 0.3V
VIH Input High Level (1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V
5
AT24C02A/04A
0976Q–SEEPR–8/05
Note: 1. This parameter is characterized and is not 100% tested.
Table 5. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted)
Symbol Parameter
1.8-volt 2.5, 2.7, 5.0-volt
UnitsMin Max Min Max
fSCL Clock Frequency, SCL 100 400 kHz
tLOW Clock Pulse Width Low 4.7 1.2 µs
tHIGH Clock Pulse Width High 4.0 0.6 µs
tINoise Suppression Time(2) 100 50 ns
tAA Clock Low to Data Out Valid 0.1 4.5 0.1 0.9 µs
tBUF
Time the bus must be free before
a new transmission can start(1) 4.7 1.2 µs
tHD.STA Start Hold Time 4.0 0.6 µs
tSU.STA Start Set-up Time 4.7 0.6 µs
tHD.DAT Data In Hold Time 0 0 µs
tSU.DAT Data In Set-up Time 200 100 ns
tRInputs Rise Time(1) 1.0 0.3µs
tFInputs Fall Time(1) 300 300 ns
tSU.STO Stop Set-up Time 4.7 0.6 µs
tDH Data Out Hold Time 100 50 ns
tWR Write Cycle Time 5 5 ms
Endurance(1) 5.0V, 25°C, Page Mode 1M 1M Write Cycles
6AT24C02A/04A
0976Q–SEEPR–8/05
Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 2). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
Figure 2. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 3).
Figure 3. Start and Stop Definition
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words.. The EEPROM sends a “0” to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02A/04A/08A/16A features a low-power standby mode
that is enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the com-
pletion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
1. Clock up to 9 cycles
2. Look for SDA high in each cycle while SCL is high
3. Create a start condition as SDA is high.
7
AT24C02A/04A
0976Q–SEEPR–8/05
Figure 4. Bus Timing
Figure 5. Write Cycle Timing
Notes: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 6. Output Acknowledge
twr
(1)
STOP
CONDITION
START
CONDITION
WORDn
ACK
8th BIT
SCL
SDA
8AT24C02A/04A
0976Q–SEEPR–8/05
Device Addressing The 2K and 4K EEPROM devices require an 8-bit device address word following a start
condition to enable the chip for a read or write operation, as shown in Figure 7.
Figure 7. Device Address
The device address word consists of a mandatory “1”, “0” sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM.
These three bits must compare to their corresponding hardwired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corre-
sponding hardwired input pins. The A0 pin is no-connect.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the chip will return to a standby state.
Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgement. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as
a microcontroller, must terminate the write sequence with a stop condition. At this time,
the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All
inputs are disabled during this write cycle, and the EEPROM will not respond until the
write is complete, see Figure 8 on page 8.
Figure 8. Byte Write
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K device
is capable of 16-byte page writes.
MSB
2K
LSB
1A2A0
A1R/W
4K 1A2P0
A1R/W
0
0
0
0
1
1
S
T
A
R
T
M
S
B
M
S
B
L
S
B
S
T
O
P
W
R
I
T
E
SDA LINE
DEVICE
ADDRESS WORD ADDRESS DATA
L
S
B
A
C
K
A
C
K
A
C
K
R
/
W
9
AT24C02A/04A
0976Q–SEEPR–8/05
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) or fifteen (4K) more data words. The EEPROM will respond with a “0” after each
data word received. The microcontroller must terminate the page write sequence with a
stop condition, see Figure 9.
Figure 9. Page Write
The data word address lower three (2K) or four (4K) bits are internally incremented fol-
lowing the receipt of each data word. The higher data word address bits are not
incremented, retaining the memory page row location. When the word address, inter-
nally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (2K) or sixteen (4K) data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will
be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0” allowing the read or write sequence to continue.
S
T
A
R
T
M
S
B
S
T
O
P
W
R
I
T
E
SDA LINE
DEVICE
ADDRESS WORD ADDRESS (n) DATA (n) DATA (n + 1) DATA (n + x)
L
S
B
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
R
/
W
10 AT24C02A/04A
0976Q–SEEPR–8/05
Read Operations Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to “1”. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the read/write select bit set to “1” is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input “0” but does generate a following
stop condition, see Figure 10.
Figure 10. Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a “0” but does generate a following stop condition, see Figure 11.
Figure 11. Random Read
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
S
T
A
R
T
R
E
A
D
M
S
B
S
T
O
P
SDA LINE
DEVICE
ADDRESS
DATA
L
S
B
A
C
K
N
O
A
C
K
R
/
W
S
T
A
R
T
S
T
A
R
T
M
S
B
S
T
O
P
W
R
I
T
E
R
E
A
D
SDA LINE
DEVICE
ADDRESS
DUMMY WRITE
WORD
ADDRESS n
DEVICE
ADDRESS
DATA n
L
S
B
A
C
K
A
C
K
A
C
K
N
O
A
C
K
R
/
W
M
S
B
L
S
B
M
S
B
L
S
B
12 AT24C02A/04A
0976Q–SEEPR–8/05
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green Package + RoHS compliant
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM Marketing.
AT24C02A Ordering Information(1)
Ordering Code Package Operation Range
AT24C02A-10PI-2.7
AT24C02AN-10SI-2.7
AT24C02A-10TI-2.7
8P3
8S1
8A2
Industrial Temperature
(−40°C to 85°C)
AT24C02A-10PI-1.8
AT24C02AN-10SI-1.8
AT24C02A-10TI-1.8
8P3
8S1
8A2
Industrial Temperature
(−40°C to 85°C)
AT24C02A-10PU-2.7(2)
AT24C02A-10PU-1.8(2)
AT24C02AN-10SU-2.7(2)
AT24C02AN-10SU-1.8(2)
AT24C02A-10TU-2.7(2)
AT24C02A-10TU-1.8(2)
AT24C02AY1-10YU-1.8(2)
AT24C02AU3-10UU-1.8(2)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT24C02A-W2.7-11(3)
AT24C02A-W1.8-11(3)
Die Sale
Die Sale
Industrial Temperature
(−40°C to 85°C)
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8U3-1 8-ball, die Ball Grid Array Package (dBGA2)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
13
AT24C02A/04A
0976Q–SEEPR–8/05
Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green Package + RoHS compliant
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM Marketing.
AT24C04A Ordering Information(1)
Ordering Code Package Operation Range
AT24C04A-10PI-2.7
AT24C04AN-10SI-2.7
AT24C04A-10TI-2.7
8P3
8S1
8A2
Industrial Temperature
(−40°C to 85°C)
AT24C04A-10PI-1.8
AT24C04AN-10SI-1.8
AT24C04A-10TI-1.8
8P3
8S1
8A2
Industrial Temperature
(−40°C to 85°C)
AT24C04A-10PU-2.7(2)
AT24C04A-10PU-1.8(2)
AT24C04AN-10SU-2.7(2)
AT24C04AN-10SU-1.8(2)
AT24C04A-10TU-2.7(2)
AT24C04A-10TU-1.8(2)
AT24C04AY1-10YU-1.8(2)
AT24C04AU3-10UU-1.8(2)
8P3
8P3
8S1
8S1
8A2
8A2
8Y1
8U3-1
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
AT24C04A-W2.7-11(3)
AT24C04A-W1.8-11(3)
Die Sale
Die Sale
Industrial Temperature
(−40°C to 85°C)
Package Type
8P3 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8Y1 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8U3-1 8-ball, die Ball Grid Array Package (dBGA2)
Options
−2.7 Low Voltage (2.7V to 5.5V)
−1.8 Low Voltage (1.8V to 5.5V)
14 AT24C02A/04A
0976Q–SEEPR–8/05
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A
–
–
0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005
–
–
3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Top View
Side View
End View
15
AT24C02A/04A
0976Q–SEEPR–8/05
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0° – 8°
∅
Top View
End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
16 AT24C02A/04A
0976Q–SEEPR–8/05
8A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
5/30/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
8A2 B
Side View
End View
Top View
A2
A
L
L1
D
123
E1
N
b
Pin 1 indicator
this corner
E
e
17
AT24C02A/04A
0976Q–SEEPR–8/05
8U3-1 – dBGA2
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
PO8U3-1 A
6/24/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
A 0.71 0.81 0.91
A1 0.10 0.15 0.20
A2 0.40 0.45 0.50
b 0.20 0.25 0.30
D 1.50 BSC
E 2.00 BSC
e 0.50 BSC
e1 0.25 REF
d 1.00 BSC
d1 0.25 REF
1. Dimension “b” is measured at the maximum solder ball diameter.
This drawing is for general information only.
Bottom View
8 SOLDER BALLS
b
D
E
Top View
PIN 1 BALL PAD CORNER
A
Side View
A
2
A
1
4
5
PIN 1 BALL PAD CORNER
31
e
2
67
8
d
(e1)
(d1)
1.
18 AT24C02A/04A
0976Q–SEEPR–8/05
8Y1 – MAP
A – – 0.90
A1 0.00 – 0.05
D 4.70 4.90 5.10
E 2.80 3.00 3.20
D1 0.85 1.00 1.15
E1 0.85 1.00 1.15
b 0.25 0.30 0.35
e 0.65 TYP
L 0.50 0.60 0.70
PIN 1 INDEX AREA
D
E
A
A1 b
876
e
5
L
D1
E1
PIN 1 INDEX AREA
1234
A
Top View End View Bottom View
Side View
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1 C
8Y1
2/28/03
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN NOM MAX
NOTE
19
AT24C02A/04A
0976Q–SEEPR–8/05
Y5 – MAP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8Y5, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Mini-Map, Dual
No Lead Package (DFN) A
8Y5
11/12/03
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 2.00 BSC
E 3.00 BSC
D2 1.40 1.50 1.60
E2 1.75 1.85 1.95
A – – 0.90
A1 0.0 0.02 0.05
A2 – – 0.85
A3 0.20 REF
L 0.20 0.30 0.40
e 0.50 BSC
b 0.20 0.25 0.30 2
Pin 1
Index
Area
E
D
A3
A
A2 A1
D2 b
(8x)
Pin 1 ID
E2
L (8x)
e (6x)
1.50 REF.
Bottom View
Top View
Side View
Printed on recycled paper.
0976Q–SEEPR–8/05
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