ANALOG DEVICES [_ Quad 12-Bit Microprocessor- Compatible D/A Converter AD390 FEATURES Four Complete 12-Bit DACs in One IC Package Linearity Error + 1/2LSB Tyun Tmax (AD390K, T) Factory-Trimmed Gain and Offset Buffered Voltage Output Monotonicity Guaranteed Over Full Temperature Range Double-Buffered Data Latches includes Reference and Buffer Fast Settling: 84s max to + 1/2LSB PRODUCT DESCRIPTION The AD390 contains four 12-bit high speed voltage-output digital-to-analog converters in a compact 28-pin hybrid package. The design is based on a proprietary latched 12-bit DAC chip which reduces chip count and provides high reliability. The AD390 is ideal for systems requiring digital control of many analog voltages where board space is at a premium. Such appli- cations include automatic test equipment, process controllers, and vector-scan displays. The AD390 is laser-trimmed to + 1/2LSB max nonlinearity (AD390KD, TD) and absolute accuracy of +0.05 percent of full scale. The high initial accuracy is made possible by the use of thin-film scaling resistors on the monolithic DAC chips. The internal buried Zener voltage reference provides excellent tem- perature drift characteristics (20ppm/C) and an initial tolerance of +0.03% maximum. The internal reference buffer allows a single common reference to be used for multiple AD390 devices in large systems. The individual DACs are accessed by the CS1-through CS4 control inputs and the AO and Al lines, These control signals permit the registers of the four DACs to be loaded sequentially and the outputs to be simultaneously updated. The AD390 outputs are calibrated for a + 10V output range with positive-true offset binary input coding. A 0 to + 10V version is available on special order. The AD390 is packaged in a 28-lead ceramic package and is specified for operation over the 0 to + 70C and 55C to + 125C temperature range. REV. A FUNCTIONAL BLOCK DIAGRAM Ve Ve GND" AbD eo a 1 ihm? LATCH . Bi ier vaten_ | a rn : aca P+ 8) Yours i 12 LATCH 12-T LATCH 3 sciased 1) Vou pc 12-87 LATCH mat ht o 17) RGF Yo 12-8 LATCH TO ALL 5 (ae ~~ coms canes PRODUCT HIGHLIGHTS 1. The AD390 offers a dramatic reduction in printed circuit board space requirements in systems using multiple DACs. 2. Each DAC is independently addressable, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level-triggered. 3. The output voltage is trimmed to a full scale accuracy of + 0.05%. Settling time to + 1/2LSB is 8 microseconds maximum. 4. An internal 10 volt reference is available or an external reference can be used. With an.external reference, the AD390 gain TC is +S5ppm/C maximum. 5. The proprietary monolithic DAC chips provide excellent linearity and guaranteed monotonicity over the full operating temperature range. 6. The 28-pan double-width hybrid package provides extremely high fugictional density. No external components or adjustments are required to provide the complete function. 7. The AD390SD and AD390TD feature guaranteed accuracy and linearity over the 55C to + 125C temperature range.AD390 SPECIFICATION (Il, = +25C, , = + 15 unless otherwise indicsted, specifications guaranteed after 10 minute warmup) Model AD390)D/SD ADI90KD/TD Min Typ Max Min Typ Max Units DATA INPUTS (Pins 1-12 and 23-28)! TTLor 5 VoltCMOS Input Voltage Bit ON (Logic 1") +2.0 +5.5 +2.0 +5.5 Vv Bit OFF (Logic 0) +0.8 +08 V Input Current (Pin 24 is 3 x Larger) Bit ON (Logic 1) 500 1200 500 1200 pA Bit OF F (Logic 0") 150 400 150 400 pA RESOLUTION 12 12 Bits OUTPUT? Voltage Range? +10 +10 Vv Current 5 5 mA Settling Time (to + 4.LSB) 4 8 4 8 ps ACCURACY Gain Error (w/ext. 10.000V reference) +0.05 0.1 +0.025 +0.05 % of FSR Offset +0.025 +0.05 0.012 +0.025 | %ofFSR Linearity Error +1/4 + 3/4 +18 + 1/2 LSB Differential Linearity Error +2 + 3/4 +1/4 +1/2 LSB TEMPERATURE DRIFT Gain (internal reference) +40 +20 ppmC (external reference) +10 +5 ppm/*C Zero +10 +5 ppm/C Linearity Error T pin Tmax + 1/2 +3/4 + 1/4 +1/2 LSB Differential Linearity MONOTONICITY GUARANTEED OVER FULL TEMPERATURE RANGE CROSSTALK? 0.1 0.1 LSB REFERENCE OUTPUT Voltage (without load) 9.997 10.000 10.003 9.997 10,000 10.003 Vv Current (available for external use) 2.5 3.5 2.5 3.5 mA REFERENCE INPUT Input Resistance 10! 10 n Voltage Range 5 1] 5 11 Vv POWER REQUIREMENTS Voluge +13.5 +15 + 16.5 +13.5 +15 + 16.5 Vv Current +Vs 20 35 20 35 mA -Vs 85 - 100 85 - 100 mA POWER SUPPLY GAIN SENSITIVITY +Vs5 0.002 0.006 0.002 0.006 %FS% -Vs 0.0025 0.006 0.0025 0.006 %FS/% TEMPERATURE RANGE Operating (Full Specifications)J, K 0 +70 0 +70 C $,T -55 +125 -55 +125 C Storage -65 +150 -65 +150 C NOTES Timing specifications appear in Table 2. ?The AD390 ourputs are guaranteed stable for losd capacitances up to 300pF. > = 10V range is standard, A 0 to 10V version is also available. Toorder, use the following part numbers: ADSO207-1 JGrade ADS0207-2 K Grade ADS0207-3 S Grade ADS0207-4 T Grade ADS0207-7 S/883B Grade ADS0207-8 T/883B Grade FSR means Full Scale Range and is equal to 20V fora + 10V range. *Crosstalk is defined as the change in any one output as a result of any other output being driven from = 10V to + 10V intoa 2k?N load. The AD390 can be used with supply voltage as low as + 11.4V, Figure 10. Specifications subject to change without notice. REV. A[ AD390 ABSOLUTE MAXIMUM RATINGS Analog Outputs (Pins 16, 18-21) Veto DOND 5 so 6 cen we ne 8) cows Oto +1BV wee ee ee ee Indefinite Short to AGND or DGND -VstoDGND ... 0 eee ee ene Oto 18V Momentary Short to + Vs Digital Inputs (Pins 1-12, 23-28)to DGND.... 1to +7V Storage Temperature ............- -65C to + 150C Ref Inte DGND: : 2 2 e255 4 Sk Ee Bees +Vs Lead Temperature (Soldering, 10 Seconds) ...... + 300C AGND toDGND.......... 0.20228 ee es $06V ORDERING GUIDE Temperature GainError | Linearity Error | Package Model Range 25C Train T max Option* AD390jD Oto + 70C +4LSB +3/4LSB DH-28 AD390KD | 0to +70C +2LSB + 1/2LSB DH-28 AD390SD -55Cto +125C | +4LSB +3/4LSB DH-28 AD390TD 55Cto +125C | +2LSB + 1/2LSB DH-28 *DH-28 = Side Brazed Ceramic DIP for Hybrid. For outline information see Package Information section. PIN CONFIGURATION (tsB)o80 [7 | za) oS4 p81 (= a7} ai oaz (3 | [26] C52 DB3 je (3B) csi pes eq a4) Ra oT come 86 DES (Not to Scale) zz] +Vs DB? P27) Yours oes OF PB] Van DBS & 9) Voura pe10 [11 18} Your (mse) oat [12 a7] REFIN DGNo {7 [16] REFOUT -Vs [14] [is] AGNO