GS864218(B)/GS864236(B)/GS864272(C)
4M x 18, 2M x 36, 1M x 72
72Mb S/DCD Sync Burst SRAMs
300 MHz–167 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
119- & 209-Pin BGA
Commercial Temp
Industrial Temp
Rev: 1.04a 2/2009 1/36 © 2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V +10%/–10% core power supply
• 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
• RoHS-compliant 119- and 209-bump BGA packages available
Functional Description
Applications
The GS864218/36/72 is a 75,497,472-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although
of a type originally developed for Level 2 Cache applications
supporting high performance CPUs, the device now finds
application in synchronous SRAM applications, ranging from
DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS864218/36/72 is a SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD
SRAMs pipeline disable commands to the same degree as read
commands. SCD SRAMs pipeline deselect commands one stage
less than read commands. SCD RAMs begin turning off their
outputs immediately after the deselect command has been
captured in the input registers. DCD RAMs hold the deselect
command for one full cycle and then begin turning off their
outputs just after the second rising edge of clock. The user may
configure this SRAM for either mode of operation using the SCD
mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Parameter Synopsis
-300 -250 -200 -167 Unit
Pipeline
3-1-1-1
tKQ(x18/x36)
tKQ(x72)
tCycle
2.3
3.0
3.3
2.5
3.0
4.0
3.0
3.0
5.0
3.4
3.4
6.0
ns
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
400
480
590
340
410
520
290
350
435
260
305
380
mA
mA
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
5.5
6.5
6.5
7.5
7.5
8.0
8.0
ns
ns
Curr (x18)
Curr (x36)
Curr (x72)
285
330
425
245
280
370
220
250
315
210
240
300
mA
mA
mA
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 2/36 © 2004, GSI Technology
209-Bump BGA—x72 Common I/O—Top View (Package C)
12345678910 11
ADQGDQGAE2 ADSP ADSC ADV E3 ADQBDQBA
BDQGDQGBC BG NC BW ABB BF DQBDQBB
CDQGDQGBH BD NC E1 NC BE BA DQBDQBC
DDQGDQGVSS NC NC GGW NC VSS DQBDQBD
EDQPGDQPCVDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPFDQPBE
FDQCDQCVSS VSS VSS ZQ VSS VSS VSS DQFDQFF
GDQCDQCVDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQFDQFG
HDQCDQCVSS VSS VSS MCL VSS VSS VSS DQFDQFH
JDQCDQCVDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQFDQFJ
KNC NC CK NC VSS MCL VSS NC NC NC NC K
LDQHDQHVDDQ VDDQ VDD FT VDD VDDQ VDDQ DQADQAL
MDQHDQHVSS VSS VSS MCL VSS VSS VSS DQADQAM
NDQHDQHVDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQADQAN
PDQHDQHVSS VSS VSS ZZ VSS VSS VSS DQADQAP
RDQPDDQPHVDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPADQPER
TDQDDQDVSS NC NC LBO NC NC VSS DQEDQET
UDQDDQDAAAAAAADQEDQEU
VDQDDQDAAAA1 A A A DQEDQEV
WDQDDQDTMS TDI AA0 ATDO TCK DQEDQEW
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 3/36 © 2004, GSI Technology
GS864272 209-Bump BGA Pin Description
Symbol Type Description
A0, A1IAddress field LSBs and Address Counter Preset Inputs.
An IAddress Inputs
DQA
DQB
DQC
DQD
DQE
DQF
DQG
DQH
I/O Data Input and Output pins
BA, BBIByte Write Enable for DQA, DQB I/Os; active low
BC,BDIByte Write Enable for DQC, DQD I/Os; active low
BE, BF, BG,BHIByte Write Enable for DQE, DQF, DQG, DQH I/Os; active low
NC —No Connect
CK IClock Input Signal; active high
GW IGlobal Write Enable—Writes all bytes; active low
E1IChip Enable; active low
E3IChip Enable; active low
E2IChip Enable; active high
GIOutput Enable; active low
ADV IBurst address counter advance enable; active low
ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low
ZZ ISleep Mode control; active high
FT IFlow Through or Pipeline mode; active low
LBO ILinear Burst Order mode; active low
SCD ISingle Cycle Deselect/Dual Cycle Deselect Mode Control
MCH IMust Connect High
MCL Must Connect Low
BW IByte Enable; active low
ZQ IFLXDrive Output Impedance Control
(Low = Low Impedance [High Drive], High = High Impedance [Low Drive])
TMS IScan Test Mode Select
TDI IScan Test Data In
TDO OScan Test Data Out
TCK IScan Test Clock
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 4/36 © 2004, GSI Technology
VDD ICore power supply
VSS II/O and Core Ground
VDDQ IOutput driver power supply
GS864272 209-Bump BGA Pin Description (Continued)
Symbol Type Description
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 5/36 © 2004, GSI Technology
119-Bump BGA—x36 Common I/O—Top View
1234567
AVDDQ A A ADSP A A VDDQ A
BNC A A ADSC A A NC B
CNC A A VDD A A NC C
DDQCDQPCVSS ZQ VSS DQPBDQBD
EDQCDQCVSS E1 VSS DQBDQBE
FVDDQ DQCVSS GVSS DQBVDDQ F
GDQC2 DQCBC ADV BB DQBDQBG
HDQCDQCVSS GW VSS DQBDQBH
JVDDQ VDD NC VDD NC VDD VDDQ J
KDQDDQDVSS CK VSS DQADQAK
LDQDDQDBD SCD BA DQADQAL
MVDDQ DQDVSS BW VSS DQAVDDQ M
NDQDDQDVSS A1 VSS DQADQAN
PDQDDQPDVSS A0 VSS DQPADQAP
RNC ALBO VDD FT ANC R
TNC AAAAAZZ T
UVDDQ TMS TDI TCK TDO NC VDDQ U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 6/36 © 2004, GSI Technology
119-Bump BGA—x18 Common I/O—Top View
1234567
AVDDQ A A ADSP A A VDDQ A
BNC A A ADSC A A NC B
CNC A A VDD A A NC C
DDQBNC VSS ZQ VSS DQPANC D
ENC DQBVSS E1 VSS NC DQAE
FVDDQ NC VSS GVSS DQAVDDQ F
GNC DQBBB ADV NC NC DQAG
HDQBNC VSS GW VSS DQANC H
JVDDQ VDD NC VDD NC VDD VDDQ J
KNC DQBVSS CK VSS NC DQAK
LDQBNC NC SCD BA DQANC L
MVDDQ DQBVSS BW VSS NC VDDQ M
NDQBNC VSS A1 VSS DQANC N
PNC DQPBVSS A0 VSS NC DQAP
RNC ALBO VDD FT ANC R
TAAAAAAZZ T
UVDDQ TMS TDI TCK TDO NC VDDQ U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 7/36 © 2004, GSI Technology
GS864218/36 119-Bump BGA Pin Description
Symbol Type Description
A0, A1IAddress field LSBs and Address Counter Preset Inputs
An IAddress Inputs
DQA
DQB
DQC
DQD
I/O Data Input and Output pins
BA, BB, BC, BDIByte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
NC —No Connect
CK IClock Input Signal; active high
BW IByte Write—Writes all enabled bytes; active low
GW IGlobal Write Enable—Writes all bytes; active low
E1IChip Enable; active low
G I Output Enable; active low
ADV IBurst address counter advance enable; active low
ADSP, ADSC IAddress Strobe (Processor, Cache Controller); active low
ZZ ISleep mode control; active high
FT IFlow Through or Pipeline mode; active low
LBO ILinear Burst Order mode; active low
ZQ IFLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low
Drive])
SCD ISingle Cycle Deselect/Dual Cyle Deselect Mode Control
TMS IScan Test Mode Select
TDI IScan Test Data In
TDO OScan Test Data Out
TCK IScan Test Clock
VDD ICore power supply
VSS II/O and Core Ground
VSS II/O and Core Ground
VDDQ IOutput driver power supply
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 8/36 © 2004, GSI Technology
GS864218/36 Block Diagram
A1
A0 A0
A1
D0
D1 Q1
Q0
Counter
Load
DQ
DQ
Register
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
E1
G
ZZ Power Down
Control
Memory
Array
36 36
4
A
QD
E2
E3
DQx1–DQx9
Note: Only x36 version shown for simplicity.
BA
BB
BC
BD
FT
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 9/36 © 2004, GSI Technology
Note:
There arepull-up devices on the ZQ, SCD, and FT pins and pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name Pin
Name State Function
Burst Order Control LBO LLinear Burst
HInterleaved Burst
Output Register Control FT LFlow Through
H or NC Pipeline
Power Down Control ZZ L or NC Active
H Standby, IDD = ISB
Single/Dual Cycle Deselect Control SCD LDual Cycle Deselect
H or NC Single Cycle Deselect
FLXDrive Output Impedance Control ZQ LHigh Drive (Low Impedance)
H or NC Low Drive (High Impedance)
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 10/36 © 2004, GSI Technology
Notes:
1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.
2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.
3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
4. Bytes “C” and “D” are only available on the x32 and x36 versions.
Byte Write Truth Table
Function GW BW BABBBCBDNotes
Read H H X X X X 1
Write No Bytes H L H H H H 1
Write byte a H L L H H H 2, 3
Write byte b H L H L H H 2, 3
Write byte c H L H H L H 2, 3, 4
Write byte d H L H H H L 2, 3, 4
Write all bytes HLLLLL2, 3, 4
Write all bytes L X X X X X
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 11/36 © 2004, GSI Technology
Synchronous Truth Table
Operation Address
Used
State
Diagram
Key
E1E2E3ADSP ADSC ADV WDQ3
Deselect Cycle, Power Down None X L X H X L X X High-Z
Deselect Cycle, Power Down None X L L X X L X X High-Z
Deselect Cycle, Power Down None X L X H L X X X High-Z
Deselect Cycle, Power Down None X L L X L X X X High-Z
Deselect Cycle, Power Down None X H X X X L X X High-Z
Read Cycle, Begin Burst External R L H L L X X X Q
Read Cycle, Begin Burst External R L H L H L X F Q
Write Cycle, Begin Burst External W L H L H L X T D
Read Cycle, Continue Burst Next CR X X X H H L F Q
Read Cycle, Continue Burst Next CR H X X X H L F Q
Write Cycle, Continue Burst Next CW X X X H H L T D
Write Cycle, Continue Burst Next CW H X X X H L T D
Read Cycle, Suspend Burst Current X X X H H H F Q
Read Cycle, Suspend Burst Current H X X X H H F Q
Write Cycle, Suspend Burst Current X X X H H H T D
Write Cycle, Suspend Burst Current H X X X H H T D
Notes:
1. X = Don’t Care, H = High, L = Low
2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1
3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.
7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 12/36 © 2004, GSI Technology
Simplified State Diagram
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
XX
X
Simple Synchronous OperationSimple Burst Synchronous Operation
CR
R
CW CR
CR
Notes:
1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and
that ADSP is tied high and ADSC is tied low.
3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 13/36 © 2004, GSI Technology
Simplified State Diagram with G
First Write First Read
Burst Write Burst Read
Deselect
R
W
CRCW
X
X
WR
R
WR
X
X
X
CR
R
CW CR
CR
W
CW
W
CW
Notes:
1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.
3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 14/36 © 2004, GSI Technology
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol Description Value Unit
VDD Voltage on VDD Pins –0.5 to 4.6 V
VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V
VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 ( 4.6 V max.) V
VIN Voltage on Other Input Pins –0.5 to VDD +0.5 ( 4.6 V max.) V
IIN Input Current on Any Pin +/–20 mA
IOUT Output Current on Any I/O Pin +/–20 mA
PDPackage Power Dissipation 1.5 W
TSTG Storage Temperature –55 to 125 oC
TBIAS Temperature Under Bias –55 to 125 oC
Power Supply Voltage Ranges
Parameter Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V
2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V
3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V
2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 15/36 © 2004, GSI Technology
VDDQ3 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 2.0 —VDD + 0.3 V 1
VDD Input Low Voltage VIL –0.3 —0.8 V 1
VDDQ I/O Input High Voltage VIHQ 2.0 —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.8 V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
VDDQ2 Range Logic Levels
Parameter Symbol Min. Typ. Max. Unit Notes
VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V 1
VDD Input Low Voltage VIL –0.3 —0.3*VDD V 1
VDDQ I/O Input High Voltage VIHQ 0.6*VDD —VDDQ + 0.3 V1,3
VDDQ I/O Input Low Voltage VILQ –0.3 —0.3*VDD V1,3
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V.
Recommended Operating Temperatures
Parameter Symbol Min. Typ. Max. Unit Notes
Ambient Temperature (Commercial Range Versions) TA025 70 C 2
Ambient Temperature (Industrial Range Versions) TA–40 25 85 C 2
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 16/36 © 2004, GSI Technology
Note:
These parameters are sample tested.
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter Symbol Test conditions Typ. Max. Unit
Input Capacitance CIN VIN = 0 V 4 5 pF
Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF
AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
Output load Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
20% tKC
VSS – 2.0 V
50%
VSS
VIH
Undershoot Measurement and Timing Overshoot Measurement and Timing
20% tKC
VDD + 2.0 V
50%
VDD
VIL
DQ
VDDQ/2
5030pF*
Output Load 1
* Distributed Test Jig Capacitance
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 17/36 © 2004, GSI Technology
DC Electrical Characteristics
Parameter Symbol Test Conditions Min Max
Input Leakage Current
(except mode pins) IIL VIN = 0 to VDD –2 uA 2 uA
ZZ Input Current IIN1
VDD VIN VIH
0 V VIN VIH
–1 uA
–1 uA
1 uA
100 uA
FT, SCD, ZQInput Current IIN2
VDD VIN VIL
0 V VIN VIL
–100 uA
–1 uA
1 uA
1 uA
Output Leakage Current (x36/x72) IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output Leakage Current (x18) IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA
Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —
Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V —
Output Low Voltage VOL IOL = 8 mA —0.4 V
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 18/36 © 2004, GSI Technology
Notes:
1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation.
2. All parameters listed are worst case scenario.
Operating Currents
Parameter Test Conditions Mode Symbol
-300 -250 -200 -167
Unit
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
0
to
70°C
–40
to
85°C
Operating
Current
Device Selected;
All other inputs
VIH or VIL
Output open
(x72)
Pipeline IDD
IDDQ
520
70
540
70
460
60
480
60
385
50
405
50
340
40
360
40 mA
Flow
Through
IDD
IDDQ
375
50
385
50
330
40
340
40
285
30
295
30
270
30
280
30 mA
(x32/
x36)
Pipeline IDD
IDDQ
420
60
440
60
360
50
380
50
310
40
330
40
270
35
290
35 mA
Flow
Through
IDD
IDDQ
300
30
320
30
255
25
275
25
230
20
250
20
220
20
240
20 mA
(x18)
Pipeline IDD
IDDQ
370
30
390
30
315
25
335
25
270
20
290
20
240
20
260
20 mA
Flow
Through
IDD
IDDQ
270
15
290
15
230
15
250
15
205
15
225
15
195
15
215
15 mA
Standby
Current ZZ VDD – 0.2 V —
Pipeline ISB 100 120 100 120 100 120 100 120 mA
Flow
Through ISB 100 120 100 120 100 120 100 120 mA
Deselect
Current
Device Deselected;
All other inputs
VIH or VIL
—
Pipeline IDD 150 165 140 155 130 146 125 140 mA
Flow
Through IDD 135 150 125 140 120 135 120 135 mA
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 19/36 © 2004, GSI Technology
Notes:
1. These parameters are sampled and are not 100% tested.
2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter Symbol -300 -250 -200 -167 Unit
Min Max Min Max Min Max Min Max
Pipeline
Clock Cycle Time tKC 3.3 —4.0 —5.0 —6.0 —ns
Clock to Output Valid
(x18/x36) tKQ —2.3 —2.5 —3.0 —3.4 ns
Clock to Output Valid
(x72) tKQ —3.0 —3.0 —3.0 —3.4 ns
Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —ns
Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —ns
Setup time tS 1.1 —1.2 —1.4 —1.5 —ns
Hold time tH 0.1 —0.2 —0.4 —0.5 —ns
Flow
Through
Clock Cycle Time tKC 5.5 —6.5 —7.5 —8.0 —ns
Clock to Output Valid tKQ —5.5 —6.5 —7.5 —8.0 ns
Clock to Output Invalid tKQX 3.0 —3.0 —3.0 —3.0 —ns
Clock to Output in Low-Z tLZ13.0 —3.0 —3.0 —3.0 —ns
Setup time tS 1.5 —1.5 —1.5 —1.5 —ns
Hold time tH 0.5 —0.5 —0.5 —0.5 —ns
Clock HIGH Time tKH 1.0 —1.3 —1.3 —1.3 —ns
Clock LOW Time tKL 1.2 —1.5 —1.5 —1.5 —ns
Clock to Output in
High-Z (x18/x36) tHZ11.5 2.3 1.5 2.5 1.5 3.0 1.5 3.0 ns
Clock to Output in
High-Z (x72) tHZ11.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns
G to Output Valid
(x18/x36) tOE —2.3 —2.5 —3.0 —3.5 ns
G to Output Valid
(x72) tOE —3.0 —3.0 —3.0 —3.5 ns
G to output in Low-Z tOLZ10—0—0—0—ns
G to output in High-Z
(x18/36) tOHZ1—2.3 —2.5 —3.0 —3.0 ns
G to output in High-Z
(x72) tOHZ1—3.0 —3.0 —3.0 —3.0 ns
ZZ setup time tZZS25—5—5—5—ns
ZZ hold time tZZH21—1—1—1—ns
ZZ recovery tZZR 20 —20 —20 —20 —ns
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 20/36 © 2004, GSI Technology
Pipeline Mode Timing (SCD)
Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect
tHZ
tKQXtKQ
tLZtH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tHtS
tS
tH
tS
tHtS
tH
tS
Burst ReadBurst ReadSingle Write
tKCtKC
tKLtKL
tKH
Single WriteSingle Read
tKH
Single Read
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)
ABC
Deselected with E1
E1 masks ADSP
E2 and E3 only sampled with ADSP and ADSC
ADSC initiated read
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 21/36 © 2004, GSI Technology
Flow Through Mode Timing (SCD)
Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect
tHZ
tKQX
tKQ
tLZ
tH
tS
tOHZtOE
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
ABC
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
E2 and E3 only sampled with ADSC
ADSC initiated read
Deselected with E1
Fixed High
CK
ADSP
ADSC
ADV
A0–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 22/36 © 2004, GSI Technology
Pipeline Mode Timing (DCD)
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 23/36 © 2004, GSI Technology
Flow Through Mode Timing (DCD)
Begin Read A Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C Deselect
tHZ
tKQX
tLZ
tH
tS
tOHZ
tOE
tKQ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tHtS
tH
tS
tH
tS
tH
tS
tKCtKC
tKLtKL
tKHtKH
ABC
Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)
E2 and E3 only sampled with ADSP and ADSC
E1 masks ADSP
ADSC initiated read
Deselected with E1
E1 masks ADSP
Fixed High
CK
ADSP
ADSC
ADV
Ao–An
GW
BW
Ba–Bd
E1
E2
E3
G
DQa–DQd
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 24/36 © 2004, GSI Technology
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after ZZ recovery time.
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing
Application Tips
Single and Dual Cycle Deselect
SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with
the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually
assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste
bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at
bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
tZZR
tZZHtZZS
Hold
Setup
tKLtKL
tKHtKH
tKCtKC
CK
ADSP
ADSC
ZZ
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 25/36 © 2004, GSI Technology
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG Pin Descriptions
Pin Pin Name I/O Description
TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS Test Mode Select In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
TDI Test Data In In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDO Test Data Out Out
Output that is active depending on the state of the TAP state machine. Output changes in
response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 26/36 © 2004, GSI Technology
JTAG TAP Block Diagram
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Die
Revision
Code
Not Used I/O
Configuration
GSI Technology
JEDEC Vendor
ID Code
Presence Register
Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1
x36 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1
x18 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1
x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1
Instruction Register
ID Code Register
Boundary Scan Register
012
0
····
31 30 29 12
0
Bypass Register
TDI TDO
TMS
TCK Test Access Port (TAP) Controller
108
·
10
·
·· ······
Control Signals
·
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 27/36 © 2004, GSI Technology
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
0
1
0
1
1
0
0
1
1
1
0
0
1
1
0
00
0
1
1
0 0
110
0
0
1
111
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 28/36 © 2004, GSI Technology
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-
tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-
ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-
ated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-
Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 29/36 © 2004, GSI Technology
JTAG TAP Instruction Set Summary
Instruction Code Description Notes
EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1
IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2
SAMPLE-Z 010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU 011 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
SAMPLE/
PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO. 1
GSI 101 GSI private instruction. 1
RFU 110 Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1
BYPASS 111 Places Bypass Register between TDI and TDO. 1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 30/36 © 2004, GSI Technology
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter Symbol Min. Max. Unit Notes
3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1
3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1
2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1
2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1
TMS, TCK and TDI Input Leakage Current IINHJ –300 1uA 2
TMS, TCK and TDI Input Leakage Current IINLJ –1100 uA 3
TDO Output Leakage Current IOLJ –1 1 uA 4
Test Port Output High Voltage VOHJ 1.7 —V5, 6
Test Port Output Low Voltage VOLJ —0.4 V5, 7
Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8
Test Port Output CMOS Low VOLJC —100 mV V5, 9
Notes:
1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ VIN VDDn
3. 0 V VIN VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG Port AC Test Conditions
Parameter Conditions
Input high level VDD – 0.2 V
Input low level 0.2 V
Input slew rate 1 V/ns
Input reference level VDDQ/2
Output reference level VDDQ/2
DQ
VDDQ/2
5030pF*
JTAG Port AC Test Load
* Distributed Test Jig Capacitance
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 31/36 © 2004, GSI Technology
JTAG Port Timing Diagram
Boundary Scan (BSDL Files)
For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications
Engineering Department at: apps@gsitechnology.com.
JTAG Port AC Electrical Characteristics
Parameter Symbol Min Max Unit
TCK Cycle Time tTKC 50 —ns
TCK Low to TDO Valid tTKQ —20 ns
TCK High Pulse Width tTKH 20 —ns
TCK Low Pulse Width tTKL 20 —ns
TDI & TMS Set Up Time tTS 10 —ns
TDI & TMS Hold Time tTH 10 —ns
tTH
tTS
tTKQ
tTH
tTS
tTH
tTS
tTKLtTKLtTKHtTKHtTKCtTKC
TCK
TDI
TMS
TDO
Parallel SRAM input
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 32/36 © 2004, GSI Technology
Package Dimensions—119-Bump FPBGA (Package B, Variation 2)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1 2 3 4 5 6 7 7 6 5 4 3 2 1
A1 TOP VIEW A1
BOTTOM VIEW
1.27
7.62
1.27
20.32
14±0.10
22±0.10
B
A
0.20(4x)
Ø0.10
Ø0.30
C
C A B
S
SØ0.60~0.90 (119x)
C
SEATING PLANE
0.15 C
0.50~0.70
1.86.±0.13
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
SS
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 33/36 © 2004, GSI Technology
Package Dimensions—209-Bump BGA (Package C)
14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array
C
11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
Ø0.10
Ø0.30
C
C A B
M
M
Ø0.50~0.70 (209x)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1.0
1.0
18.0
22.0
B
14.0
A
0.20(4x)
1.0 1.0
10.0
1 2 3 4 5 6 7 8 9 10 11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
A1 CORNER TOP VIEW
SEATING PLANE
0.15 C
0.40~0.60
1.70 MAX.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 34/36 © 2004, GSI Technology
Ordering Information for GSI Synchronous Burst RAMs
Org Part Number1Type Package Speed2
(MHz/ns) TA3
4M x 18 GS864218B-300 SCD/DCD; PL/FT 119 BGA (var.2) 300/5.5 C
4M x 18 GS864218B-250 SCD/DCD; PL/FT 119 BGA (var.2) 250/6.5 C
4M x 18 GS864218B-200 SCD/DCD; PL/FT 119 BGA (var.2) 200/7.5 C
4M x 18 GS864218B-167 SCD/DCD; PL/FT 119 BGA (var.2) 167/8 C
2M x 36 GS864236B-300 SCD/DCD; PL/FT 119 BGA (var.2) 300/5.5 C
2M x 36 GS864236B-250 SCD/DCD; PL/FT 119 BGA (var.2) 250/6.5 C
2M x 36 GS864236B-200 SCD/DCD; PL/FT 119 BGA (var.2) 200/7.5 C
2M x 36 GS864236B-167 SCD/DCD; PL/FT 119 BGA (var.2) 167/8 C
1M x 72 GS864272C-300 SCD/DCD; PL/FT 209 BGA 300/5.5 C
1M x 72 GS864272C-250 SCD/DCD; PL/FT 209 BGA 250/6.5 C
1M x 72 GS864272C-200 SCD/DCD; PL/FT 209 BGA 200/7.5 C
1M x 72 GS864272C-167 SCD/DCD; PL/FT 209 BGA 167/8 C
4M x 18 GS864218B-300I SCD/DCD; PL/FT 119 BGA (var.2) 300/5.5 I
4M x 18 GS864218B-250I SCD/DCD; PL/FT 119 BGA (var.2) 250/6.5 I
4M x 18 GS864218B-200I SCD/DCD; PL/FT 119 BGA (var.2) 200/7.5 I
4M x 18 GS864218B-167I SCD/DCD; PL/FT 119 BGA (var.2) 167/8 I
2M x 36 GS864236B-300I SCD/DCD; PL/FT 119 BGA (var.2) 300/5.5 I
2M x 36 GS864236B-250I SCD/DCD; PL/FT 119 BGA (var.2) 250/6.5 I
2M x 36 GS864236B-200I SCD/DCD; PL/FT 119 BGA (var.2) 200/7.5 I
2M x 36 GS864236B-167I SCD/DCD; PL/FT 119 BGA (var.2) 167/8 I
1M x 72 GS864272C-300I SCD/DCD; PL/FT 209 BGA 300/5.5 I
1M x 72 GS864272C-250I SCD/DCD; PL/FT 209 BGA 250/6.5 I
1M x 72 GS864272C-200I SCD/DCD; PL/FT 209 BGA 200/7.5 I
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864218B-167IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 35/36 © 2004, GSI Technology
1M x 72 GS864272C-167I SCD/DCD; PL/FT 209 BGA 167/8 I
4M x 18 GS864218GB-300 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 C
4M x 18 GS864218GB-250 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 C
4M x 18 GS864218GB-200 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 C
4M x 18 GS864218GB-167 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 167/8 C
2M x 36 GS864236GB-300 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 C
2M x 36 GS864236GB-250 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 C
2M x 36 GS864236GB-200 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 C
2M x 36 GS864236GB-167 SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 167/8 C
1M x 72 GS864272GC-300 SCD/DCD; PL/FT RoHS-compliant 209 BGA 300/5.5 C
1M x 72 GS864272GC-250 SCD/DCD; PL/FT RoHS-compliant 209 BGA 250/6.5 C
1M x 72 GS864272GC-200 SCD/DCD; PL/FT RoHS-compliant 209 BGA 200/7.5 C
1M x 72 GS864272GC-167 SCD/DCD; PL/FT RoHS-compliant 209 BGA 167/8 C
4M x 18 GS864218GB-300I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 I
4M x 18 GS864218GB-250I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 I
4M x 18 GS864218GB-200I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 I
4M x 18 GS864218GB-167I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 167/8 I
2M x 36 GS864236GB-300I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 300/5.5 I
2M x 36 GS864236GB-250I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 250/6.5 I
2M x 36 GS864236GB-200I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 200/7.5 I
2M x 36 GS864236GB-167I SCD/DCD; PL/FT RoHS-compliant 119 BGA (var.2) 167/8 I
1M x 72 GS864272GC-300I SCD/DCD; PL/FT RoHS-compliant 209 BGA 300/5.5 I
1M x 72 GS864272GC-250I SCD/DCD; PL/FT RoHS-compliant 209 BGA 250/6.5 I
1M x 72 GS864272GC-200I SCD/DCD; PL/FT RoHS-compliant 209 BGA 200/7.5 I
1M x 72 GS864272GC-167I SCD/DCD; PL/FT RoHS-compliant 209 BGA 167/8 I
Ordering Information for GSI Synchronous Burst RAMs (Continued)
Org Part Number1Type Package Speed2
(MHz/ns) TA3
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS864218B-167IB.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
GS864218(B)/GS864236(B)/GS864272(C)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2009 36/36 © 2004, GSI Technology
72Mb Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content Page;Revisions;Reason
8642xx_r1 • Creation of new datasheet
8642xx_r1; 8642xx_r1_01 Content • Changed “E” package to “F”
• Added Pb-Free information
8642xx_r1_01;
8642xx_r1_02 Content • Removed F package entirely
• (rev. 1.02a): Changed 36Mb to 72Mb in front page banner
8642xx_r1_02;
8642xx_r1_03 Content
• Changed 167 MHz tKQ to 3.4 ns (pg. 1, 19)
• Changed Pb-free to RoHS-compliant (entire document)
• Added status to ordering information table (pg. 33, 34, 35)
8642xx_r1_03;
8642xx_r1_04 Content
• Updated Truth Tables
• Rev1.04a: updated coplanarity for 209 BGA mechanical,
removed Status column from Ordering Information table,
Removed “Preliminary” banner due to MP status