Enpirion® Power Datasheet
EN2340QI 4A Pow er SoC
Volt age M ode Synchr onous
PWM Buck with In tegrated Inductor
Description
The EN2340QI is a Power System on a Chip
(Pow erS oC) DC-DC converter. I t i ntegrates M OS FET
switches, small-signal control circuits, compensation
and an integrated inducto r in an advance d 8x 11x3mm
QFN module. It offers high efficiency, excellent line
and load regulation over temperature and up to the
full 4A load range. The EN2340QI operates over a
wide input voltage range and is specifically designed
to meet the precise voltage and fast transient
requirements of high-performance products. The
EN2340 features frequency synchronization to an
external clock, power OK output voltage monitor,
programmable soft-start along with thermal and over
current protection. The device’s advanced circuit
design, ultra high sw itchi ng frequenc y and prop rieta ry
integrated inductor technology delivers high-quality,
ultra compact, non-isolated DC-DC conversion.
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufactur ing environments.
Features
• Integrated Inductor, M OS FETs, Controller
• Wide Input Voltage Range: 4.5V – 14V
• Guaranteed 4A IOUT at 85°C with No A irflow
• Frequency S ynchro niz ati on (Ex ternal Clock)
• 1% Initial VOUT Accuracy
• High Efficiency (Up to 95%)
• Output E nable Pin and P ow er OK signal
• Program m able S oft-Start Time
• Pi n C om patible with the E N2360QI (6A)
• Under Voltage Lockout Protection (UVLO)
• Programmable Over Current Protection
• Therm al S hutdown and S hort Circuit Protection
• RoHS Com pliant, M S L Level 3, 260oC Reflow
Applications
• Space Constrained Applications
• Distributed Power Architectures
• Output Voltage Ripple Sensitive Applications
• Beat Frequency S ensitive Applications
• Servers, Em bedded Com puting System s,
LAN/SAN Adapter Cards, RAI D Storage Systems,
Industrial Automation, Test and M easurement,
and Telecommunications
Figure 1. S i m pl i fied Appl i cat i ons Ci rcui t
(Footprint Optimized)
Figure 2. Hi ghest Effi ciency i n Sm al l est Sol ut i on Si ze
V
OUT
V
IN
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
2x
22µF
0805
AVINO
PG BTMP
EN2340QI
SS
VDDB BGND
FADJ
R
VB
4.75k
1µF
0.22µF
22nF
R
FS
R
CLX
1µF
OFF
ON
R
PG
560
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 4
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 5.0V
VOUT = 1.8V
CONDITIONS
V
IN
= 12.0V
Dual Supply
Actual Sol ution Si z e
200mm
2
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06878 October 9, 2013 Rev E
EN2340QI
Ordering Information
Part Num ber
Package Markings
TAMBIENT Ratin g ( °C)
Package Description
EN2340QI
EN2340QI
-40 to +85
68-pin (8mm x 11mm x 3mm) QFN T&R
EVB-EN2340QI
EN2340QI
QF N E valuati on B oard
Pac king and Ma rking Inf o r m at ion : www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
VOUT
VOUT
NC
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
NC
NC
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
AVINO
PG
BGND
VDDB
S_IN
BTMP
S_OUT
NC
NC
NC
NC
NC
NC(SW)
NC(SW)
FQADJ
NC
RCLX
SS
EAOUT
VFB
AGND
AGND
AVIN
ENABLE
POK
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
69
PGND
KEEP OUT
KEEP OUT
KEEP OUT
AGND
NC(SW)
Figure 3: P i n O ut Di agram (Top V i ew)
NOTE A: NC pins are not to be electrically connect ed to each other or to any external signal , ground, or voltage. All pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the P CB. Refer t o F i gure 15 for detai l s.
NOTE C : White ‘ dot’ on top left i s pi n 1 i ndi cator on t op of t he device package.
Pin Description
I/O Legend: P=Power G=Ground NC=No Connect I=Input O=Output I/O=Input/Output
PIN
NAME
I/O
FUNCTION
1-15,
25-26,
59, 64-
68
NC NC NO CONNECT – T hese pins may be internally connec ted. Do not connect them to each
other or to any other electrical signal . Failure to follow this guidelin e may result in device
damage.
16-24 VOUT O
Regulated converter output. C onnect these pins to the load and place output capacit or
between these pins and PGND pins 29-34.
27-28,
NC(SW)
NC
NO CONNECT – T hese pins ar e internally connected to the com mon switchi ng node of the
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06878 October 9, 2013 Rev E
EN2340QI
PIN
NAME
I/O
FUNCTION
61-63
internal MOSFET s. T hey are not to be electrically connect ed to any ex ternal signal, gr ound,
or voltage. Failure to follow this guideline may r esul t in damage to the device.
29-34 PGND G
I nput/output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions f or more details.
35-41 PVIN P
I nput power supply. Connect to input pow er supply. Decouple with input capacitor to
PGND pins 29-34.
42 AVINO O
I nternal 3.3V linear regulator output. Connect this pin to AVI N (Pin 51) f or applications
where operation f rom a single input voltage (PVIN ) is r equired. I f AVINO is being used,
place a 1µF, X5R/X7R, capacitor between AV INO and AGND as cl ose as possible to
AVINO.
43 PG I/O
PMOS gate. Place a 22nF, X5R/X7R, capacitor between thi s pin and BT MP . A 560Ω
damping resistor may be connected f rom PVIN to PG to reduce noise inside the control ler
in extreme ambient conditions.
44
BTMP
I/O
Bottom plate ground. See pin 43 descripti on.
45 VDDB O
I nternal regulated voltage used for the internal control circuitr y. Place a 0.22µF, X5R/X7R,
capacitor between this pin and BGND.
46
BGND
G
Ground f or VDDB. See pin 45 description.
47 S_IN I
Digital synchronization input. This pin accepts either an input clock to phase lock the
internal sw itching fr equency or a S_OUT signal from another EN2340QI. Leave this pin
f loating if not used.
48 S_OUT O
Digital synchronization output . PWM signal is output on this pin. Leave this pin floating if
not used.
49 POK O
Power OK is an open drain transistor (pulled up to AVIN or simi lar voltage) used for pow er
system state indicatio n. POK is logic high when VOUT is w ithin -10% of VOUT nominal.
Leave this pin floating if not used.
50 ENABLE I
Output enable. Applying a logic high to this pin enables the outpu t and initi ates a soft-start.
Applying a logic low disables the output. E NAB LE logic cannot be higher than AV IN (refer t o
Absolute Maxim um R atings). Do not leave floating. See Power U p/Down Sequencing
section for details.
51 AVIN P
3.3V Input power supply f or the controller. Place a 1µF, X5R/X7R, capacitor between AVI N
and AGND.
52, 53,
60
AGND G
Analog ground. T his is the ground r eturn for the controller. All AGND pins need to be
connected to a quiet ground.
54 VFB I/O
External feedback input. T he f eedback loop is cl osed thr ough this pin. A voltage divider at
VOUT is used to set the output voltage. T he mid-point of the divider is connected to V FB. A
phase lead network f rom this pin to VOUT is also required to st abilize the loop.
55
EAOUT
O
Optional error amplifier output. Allows for customi zat ion of the control loop.
56 SS I/O
Soft-start node. T he sof t-start capacitor is connecte d between this pin and AGND. T he
value of this capacitor determ ines the st artup ti me.
57 RCLX I/O
Programmable over-current protection. Placement of a resistor on this pin will adjust the
over-current protection threshold. See T able 2 for the recommended RCLX Value to set
OCP at the nominal value specified in the Electri cal Characterist ics tab le. No current limit
protection when this pin is left f loating.
58 FADJ I/O
Adding a resistor (R
FS
) to this pin will adjust the switchi ng f requency of the EN2340QI. See
T able 1 f or suggested resistor values on RFS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave f loating.
69 PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes.
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06878 October 9, 2013 Rev E
EN2340QI
Absolute Maximum Ratings
CAUTION: Absolute M axi mum ratings are stress rati ngs only. Functional operati on beyond the recom m ended operat i ng
conditions is not implied. Stress beyond t he absol ute m axi m um rati ngs m ay i m pai r device l i fe. E xpos ure t o absolute
m axi m um rat ed conditi ons for extended peri ods m ay affect device rel i abi l i t y.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVI N , VO U T, PG
-0.5
15
V
Voltages on: ENABLE, POK
-0.3
AV
IN
+0.3
V
Dual Supply PVIN Rising and Falling Sl ew Rate (Note 1)
0.3
25
V/ms
Single Supply PVIN R isi ng and Falling Sle w Rate (Note 1)
0.3
6
V/ms
Pin Voltages – AVINO, AVIN, S_IN, S_OUT
2.5
6.0
V
Pin Voltages – VFB, SS, EAOU T, R C L X, FADJ , VDDB, BT MP
-0.5
2.75
V
Storage T emperature Range
T
STG
-65
150
°C
Maximum Operating Junc tion T emperature
T
J-ABS Max
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
PVIN
4.5
14
V
AVIN : Controller Supply Voltage
AVIN
2.5
5.5
V
Output Voltage Range (N ote 2)
V
OUT
0.75
5
V
Output Current
I
OUT
4
A
Operating Ambient T emperature
T
A
-40
+85
°C
Operating Junction T emperature
T
J
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to Ambie nt (0 LFM) (Note 3)
θ
JA
18
°C/W
T hermal Resistance: Junction to Case ( 0 LFM)
θJC
2
°C/W
T hermal Shutdown
T
SD
160
°C
T hermal Shutdown Hysteresi s
T
SDH
35
°C
Note 1: PVIN rising and falling slew rates cannot be outside of s peci ficati on. F or ac curate power up s equencing, use a
fast ENA BLE l ogi c after both AV IN and PVIN is hi gh.
No te 2: Maximum VOUT ≤ VIN - 2.5V
Note 3: Based on 2oz. external copper layers and proper thermal design in line with EIJ /JEDEC JESD51-7 st andard for
high therm al conducti vity boards.
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06878 October 9, 2013 Rev E
EN2340QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient t em perature range (-40°C ≤ TA ≤ +85°C)
unl es s ot herwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating I nput Voltage
PVIN
4.5
14.0
V
Controller I nput Voltage
AVIN
2.5
5.5
V
AVIN Under Voltage
Lock-Out Rising AVINUVLOR
Voltage above which UVLO is not
asserted 1.7 2.2 2.4 V
AVIN Under Voltage
Lock-Out Falling AVINOVLOF
Voltage below which U VLO is
asserted 1.7 2.1 2.3 V
AVIN pin Input Current
I
AVIN
7
mA
I nternal Linear
Regulator Output AVINO 3.3 V
Shut-Dow n Supply
Current
IPVIN
S
PVIN=12V, AVIN=3.3V, ENABLE=0V
500
µA
IAVIN
S
PVIN=12V, AVIN=3.3V, ENABLE=0V
100
µA
Feedback Pin Voltage
V
FB
V
IN
= 12V, I
LOAD
= 0, T
A
= 25°C Only
0.7425
0.750
0.7575
V
Feedback Pin Voltage
V
FB
4.5V ≤ V
IN
≤ 14V; 0A ≤ I
LOAD
≤ 4A
0.735
0.750
0.765
V
Feedback Pin Input
Leakage Current IFB
VFB pin input leakage cur rent
(Note 4) -5 5 nA
V
OUT
R ise Time
t
RISE
C
SS
= 47nF (Note 5 and Note 6)
3.2
ms
Soft-Start Capacitor
Range CSS_RANGE 10 47 68 nF
Continuous Output
Current IOUT_CONT 0 4 A
Over Current T rip Level
I
OCP
Ref erence T able 2
6
A
Disable T hreshold
V
DISABLE
ENABLE pin logic Low
0.0
0.95
V
ENABLE T hreshold
V
ENABLE
ENABLE pin logic H igh
1.25
AVIN
V
ENABLE Lockout T ime
T
ENLOCKOUT
8
ms
ENABLE I nput Current
I
ENABLE
370k internal pull-down (N ote 4)
4
µA
Switching Frequency
F
SW
R
FS
=3kΩ
1.0
MHz
External SYNC C lock
Frequency Lock Range FPLL_LOCK
Range of SYNC clock f requency (See
Tabl e 1) 0.8 1.8 MHz
S_IN Threshold – Low
V
S_IN_LO
S_IN clock logic low level (Note 4)
0.8
V
S_IN Threshold – High
V
S_IN_HI
S_IN clock logic high level (Note 4)
1.8
2.5
V
S_OUT Threshold – Low
V
S_OUT_LO
S_OUT clock logic low level (Note 4)
0.8
V
S_OUT Threshold –
High VS_OUT_HI S_OUT clock logic high level (Note 4) 1.8 2.5 V
POK Lower T hreshold
POK
LT
V
OUT
/ V
OUT_NOM
90
%
POK Output low Voltage
V
POKL
With 4mA current sink into PO K
0.4
V
POK Output Hi Voltage
V
POKH
PVIN range: 4.5V ≤ V
IN
≤ 14V
AVIN
V
POK Pin V
OH
Leakage
Current IPOKL POK High (Note 4) 1 µA
No te 4: Param et er not producti on tested but i s guaranteed by desi gn.
No te 5: Ri se ti m e calculation begi ns when A V IN > V UVLO and ENABLE = HIGH.
No te 6: VOUT Ri se Ti m e A ccuracy does not i ncl ude soft -s tart capac i tor tolerance.
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06878 October 9, 2013 Rev E
EN2340QI
Typical Performance Curves
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 4
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Effic ie ncy vs. Output Current
VOUT = 5.0V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
50
55
60
65
70
75
80
85
90
95
100
00.5 11.5 22.5 33.5 4
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Effic ie ncy vs. Output Current
VOUT = 5.0V
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.2V
VOUT = 1.2V
CONDITIONS
V
IN
= 8.0V
CONDITIONS
V
IN
= 8.0V
AVIN = 3.3V
Dual Supply
50
55
60
65
70
75
80
85
90
95
100
00.5 11.5 22.5 33.5 4
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Effic ie ncy vs. Output Current
VOUT = 2.5V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 8.0V
CONDITIONS
V
IN
= 5.0V
AVIN = 3.3V
Dual Supply
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 4
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Effic ie ncy vs. Output Current
DUAL SUPPLY VOUT = 5.0V
SINGLE SUPPLY VOUT = 5.0V
DUAL SUPPLY VOUT = 1.0V
SINGLE SUPPLY VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
0.990
0.992
0.994
0.996
0.998
1.000
1.002
1.004
1.006
1.008
1.010
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
O UTPUT VOLTAGE (V)
O UTPUT CURRENT ( A )
Output Voltage vs. Output Current
VIN = 5V
VIN = 8V
VIN = 12V
CONDITIONS
V
IN
= 5.0V
CONDITIONS
V
OUT_NOM
= 1. 0V
3.290
3.292
3.294
3.296
3.298
3.300
3.302
3.304
3.306
3.308
3.310
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
O UTPUT VOLTAGE (V)
O UTPUT CURRENT ( A )
Output Voltage vs. Output Current
VIN = 8V
VIN = 12V
CONDITIONS
VOUT_NOM = 3.3V
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06878 October 9, 2013 Rev E
EN2340QI
Typical Performance Curves (Continued)
0.990
0.995
1.000
1.005
1.010
1.015
1.020
246810 12 14 16
O UTPUT VOLTAGE (V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
Load = 0A
Load = 1A
Load = 2A
Load = 3A
Load = 4A
CONDITIONS
V
OUT_NOM
= 1. 0V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
2 4 6 8 10 12 14 16
O UTPUT VOLTAGE (V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
Load = 0A
Load = 1A
Load = 2A
Load = 3A
Load = 4A
CONDITIONS
V
OUT_NOM
= 3. 3V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 8V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 10V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 12V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 14V
V
OUT_NOM
= 1. 2V
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06878 October 9, 2013 Rev E
EN2340QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Output Ripple at 20MHz Ba ndwidth
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 2A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(A C C ouple d)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 2A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 4A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(A C C ouple d)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 4A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
ENABLE
Enable Startup/Shutdown Waveform (0A)
CONDITIONS
VIN = 12V, VOUT = 1.0V, No Load, Css = 47nF
CIN = 2 x 22µF (1206), COUT = 2 x 47 µF (1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (4A)
CONDITIONS
VIN = 12V, VOUT = 1.0V, LOAD = 4A, Css = 47nF
CIN = 2 x 22µF (1206), COUT = 2 x 47 µF (1206)
VOUT
POK
LOAD
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06878 October 9, 2013 Rev E
EN2340QI
Typical Performance Characteristics (Continued)
VOUT = 1V
(AC Coupled)
20mV / DIV
Load Transient from 50mA to 2A
CONDITIONS
VIN = 12V, VOUT = 1V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
VOUT = 1V
(AC Coupled)
50mV / DIV
Load Transient from 50mA to 4A
CONDITIONS
VIN = 12V, VOUT = 1V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
VOUT = 1.8V
(AC Coupled)
100mV / DIV
Load Transient from 2A to 4A
CONDITIONS
VIN = 12V, VOUT = 1.8V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
VOUT = 1.8V
(AC Coupled)
100mV / DIV
Load Transient from 50mA to 4A
CONDITIONS
VIN = 1 2V, VOUT = 1.8V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
VOUT = 3.3V
(AC Coupled)
100mV / DIV
Load Transient from 50mA to 3A
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
VOUT = 3.3V
(AC Coupled)
100mV / DIV
Load Transient from 50mA to 3A
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 22µF (1206)
COUT = 2 x 47µF (1206)
Best Perfor mance Configuration
LOAD
www.altera.com/enpirion, Page 9
06878 October 9, 2013 Rev E
EN2340QI
Functional Block Diagram
Soft Start
Power
Good
Logic
Band Gap
Reference
Voltage Reference Generator
Compensation
Network
Thermal Limit
UVLO
Current Limit Gate Drive
PLL/Sawtooth
Generator
FADJ
ENABLE
SS
AGND
POK
AVIN
VFB
PGND
VOUT
NC(SW)
PVIN
S_IN
Error
Amp
PWM
Comp
(+)
(-)
(-)
(+)
Digital I/O
S_OUT
To PLL
EN2340QI
Linear
Regulator AVINO
300k
370k
EAOUT
PG
BTMP
BGND
VDDB
Figure 4: F uncti onal B l ock Di agram
Functional Description
Synchr onous Buck Conver ter
The EN2340QI is a highly integrated synchronous,
buck converter with integrated controller, power
M OS FET switches and inductor. The nom inal input
voltage (PVIN) range is 4.5V to 14V and can
support up to 4A of continuous output current. The
output voltage is programmed using an external
resistor divider network. T he control loop u t ilizes a
Type IV Voltage-Mode compensation network and
maximizes on a low-noise PWM topology. Much of
the com pensation circuitry is internal to the device.
However , a phase lead capacitor is required along
with the output voltage feedback resistor divider to
complete the Type IV compensation network.. The
high switching frequency of the EN2340QI enables
the use of small size input and output filter
capacitors, as well as a wide loop bandwidth within
a small foot print.
Protection Features:
The power supply has the following protection
features:
• Programmable Over-Current Protection
• Thermal Shutdow n with Hysteresis.
• Under-Voltage Lockout Protection
Additional Features:
• Sw i tching Frequency Synchr oni z ation .
• Program m able S oft-Start
• Pow er OK Output M onitoring
www.altera.com/enpirion, Page 10
06878 October 9, 2013 Rev E
EN2340QI
Power Up Sequence
The EN2340QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2340QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN) :
Figure 5: Single Input S uppl y Schem ati c
The EN2340QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN2340QI. In this application, the
following external components ar e r equired: Place
a 1µF, X5R/X7R capacitor between AVINO and
AGND as close as possible to AVINO. Place a
1µF, X5R/X7R capacitor between AVIN and AGND
as close as possible to AVIN. In addition, place a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recom m ends RVB=4.75kΩ. In this
application, ENABLE cannot be asserted before
PVIN. See diagram below for a recommended
startup and shutdown sequencing.
Fi gure 6: S i ngl e S uppl y S t art up/Shutdown S equence
If no external enable signal is used, a resister
divider (see Figure 5) from PVIN to ENABLE and
then to ground can be used to enable and disable
the device at a programmed PVIN voltage level.
The lower resistor (4.02k) can be adjusted to set
startup and shutdown at a specific PVIN voltage
level. See EN A BLE and DI S AB LE thresholds in the
Electrical Characteristics table.
Dual Input Supply Application (PVIN and AVIN) :
Figure 7: Dual Input S uppl y Schemati c
I n this application, place a 1µF, X5R/X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 7 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. There are tw o com m on acceptable turn-
on sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE must be toggled last, after
AVIN is asserted. Do not turn off AVIN before PVIN
and ENABLE during shutdown. Doing so will
disable the internal controller while there may still
be energy in the system. The device will not soft-
shutdown properly and damage may occur. See
diagram below for a recommended startup and
shutdown sequencing.
Fi gure 8: Dual Suppl y Start up/Shutdown S equenci ng
V
OUT
V
IN
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
2x
22µF
0805
AVINO
PG BTMP
EN2340QI
SS
VDDB BGND
FADJ
R
VB
4.75k
1µF
0.22µF
22nF
R
FS
R
CLX
1µF
10k
4.02k
R
PG
560
PVIN
ENABLE
0V
12V
3.3V
0V
VOUT
Soft Start Time ≈ 2ms
w/Css=47nF
Delay from ENABLE rising
edge to soft start begin
~ 1ms
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
PVIN –Recommended
to be ramped down
after the Vout soft-
shutdown occurs
PVIN slew rate limitations
as per datasheet
V
OUT
V
IN
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF VFB
R
A
R
B
R
CA
C
A
RCLX
2x
22µF
0805
AVINO
PG BTMP
EN2340QI
SS
VDDB BGND
FADJ
1µF
0.22µF
22nF
R
FS
R
CLX
V
AVIN
R
PG
560
AVIN
PVIN
ENABLE
0V
12V
3.3V
0V
3.3V
0V
VOUT
Soft Start Time ≈ 2ms
w/Css=47nF
Delay from ENABLE rising
edge to soft start begin
~ 1ms
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
AVIN powered up before PVIN
PVIN powered
down before AVIN
PVIN/AVIN –
Recommended
to be ramped down
after the Vout soft-
shutdown occurs
PVIN slew rate limitations
as per datasheet
www.altera.com/enpirion, Page 11
06878 October 9, 2013 Rev E
EN2340QI
En able Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the EN A BLE pin is asserted (high )
the device will under go a nor mal soft-start. A lo gic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Tim e (8ms) in order for the device to be re-
enabled. To ensure accurate startup sequencing
the E N A BLE/DISABLE signal shoul d be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a del ayed startup and shutdo wn response.
Pre-Bias Precautio n
The EN2340QI is not desi gned to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2340QI is not pre-biased when the EN2340QI is
first enabled.
Frequency Synchroniz ation
The switching frequency of the EN2340QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2340QI can be
phase locked to a clock signal applied to the S_IN
pin. A n activity detector recognizes the prese n c e of
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8M H z to 1.8M Hz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN2340QI for
various P VIN /VOUT com binations can be optim ize d
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2340QI.
Figure 9. Typical RFS vs. S wi t chi ng F requency
PVIN
VOUT
RFS
Typ ical fsw
12V
5.0V
30k
1.7 MHz
3.3V
15k
1.38 MHz
2.5V
10k
1.3 MHz
1.8V
4.87k
1.15 MHz
1.2V
1.65k
0.95 MHz
<1.0V
1.3k
0.8 MHz
5V
2.5V
22.1k
1.4 MHz
1.8V
10k
1.3 MHz
1.5V
6.65k
1.25 MHz
1.2V
4.87k
1.15 MHz
<1.0V
3.01k
1.0 MHz
Table 1: Rec om m ended RFS Values
Spread Spectrum Mode
The external clock frequency may be swept
between 0.8MHz and 1.8MHz at repetition rates of
up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin (pin
56) and the AGND pin (pin 52). During start-up of
the converter, the reference voltage to the error
amplifier is linearly increased to its final level by an
internal current sour ce of approx im ately 10µA. The
soft-start time is measured from when VIN > VUVLOR
and ENABLE pin voltage crosses its logic high
threshold to when VOUT reaches its programmed
value. The total soft-star t tim e can be calculated by:
Soft Start T ime (ms): TSS ≈ Css [nF] x 0.067
0.600
0.800
1.000
1.200
1.400
1.600
1.800
0 2 4 6 8 10 12 14 16 18 20 22
SWIT CHING FREQ UENCY (MHz)
R
FS
RESISTOR VALUE (kΩ)
Rfs v s. SW Frequency
CONDITIONS
V
IN
= 6V to 12V
V
OUT
= 0.8V to 3.3V
www.altera.com/enpirion, Page 12
06878 October 9, 2013 Rev E
EN2340QI
Typical soft-start time is approximately 3.2ms with
SS capacitor value of 47nF.
P OK Op e ra t io n
The POK signal is an open dr ain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over-Current Protection (OCP)
The current limit function is achieved by sensing
the current flowing through a sense PFET. When
the sensed current exceeds the current limit for
more than 32 cycles, both power FET s are turned
off for the rest of the switching cycle. If the over-
current condition is removed, the over-current
protection circuit will re-enable PWM operation. In
the event the OCP circuit trips consistently in
norm al operation, the device enters a hiccup m ode .
While in hiccup mode, the device is disabled for a
short while and restarted with a normal soft-start.
The hiccup time is approximately 32ms. This cycle
can continue i ndefinitely as long as the over curr en t
condition persists. The OCP trip point depends on
PVIN, VOUT and the RCL X r es is tor.
Generally, the higher the RCLX value, the higher
the current limit threshold for a given input and
output voltage condition.
Note: If the RCLX pin is left open, the output
current will be unlimited and the device will not
have current limit protection.
Reference Table 2 for a list of recommended
resistor values on RCLX that will set the OCP trip
point at the typical value of 6A, also specified in the
Electrical Characteristics table. Contact
www.altera.com/mysupport for specific RCLX
values to be use for special cases.
Figure 10. Typical RCLX vs. Output V ol tage
PVIN VOUT Range
R
CLX
Value
Current
Limit
5V
0.75V < VOUT ≤ 1.2V
30.1kΩ
6A
1.2V < VOUT ≤ 2.0V
31.6kΩ
6A
2.0V < VOUT ≤ 2.5V
33.2kΩ
6A
8V
0.75V < VOUT ≤ 1.2V
30.9kΩ
6A
1.2V < VOUT ≤ 2.0V
32.4kΩ
6A
2.0V < VOUT ≤ 3.0V
35.7kΩ
6A
3.0V < VOUT ≤ 4.0V
38.3kΩ
6A
4.0V < V
OUT
≤
5.0V
40.2kΩ
6A
12V
0.75V < VOUT ≤ 1.2V
31.6kΩ
6A
1.2V < V
OUT
≤
2.0V
33.2kΩ
6A
2.0V < V
OUT
≤
3.0V
36.5kΩ
6A
3.0V < VOUT ≤ 4.0V
39.2kΩ
6A
4.0V < VOUT ≤ 5.0V
41.2kΩ
6A
Table 2: Recommended RCLX Values and Current Li m i t
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 160°C. After a thermal shutdown
event, when the junction temperature drops by
approx 35°C, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leadin g edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
26
28
30
32
34
36
38
40
42
44
0.5 11.5 22.5 33.5 44.5 55.5
RCLX V AVLUE (kΩ))
O UTPUT VOL TAG E ( V)
Recommended R
CLX
Value
PVIN = 12V
PVIN = 8V
PVIN = 5V
CONDITIONS
Cu rren t Lim it ≈ 6A
T
A
= 25 C
www.altera.com/enpirion, Page 13
06878 October 9, 2013 Rev E
EN2340QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2340QI output voltage is progra m m ed usin g
a simple resistor divider network. A phase lead
capacitor (CA) plus a resistor (RCA) are r equired for
stabilizing the loop. Figure 11 shows the required
components and the equations to calculate their
values. The values recommended for CA and RCA
will vary with each PVIN and VOUT combination.
The EN2340 solution can be optimized for either
smallest size or highest performance. Please see
Table 6 for a list of recommended CA and RCA
values for each solution option.
The EN2340QI output voltage is determ ined by the
voltage pr esented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB. Since VFB
is a sensitive node, do not touch the VFB node
while the device is in operation as doing so may
introduce parasitic capa citance into the contr ol loop
that causes the device to behave abnor mally and
damage may occur.
The EN2340QI uses a Type IV compensation
network. Most of this network is integrated.
However a phase lead capacitor and a resistor are
required in parallel with the upper resistor of the
external feedback network (see Figure 11). Tota l
compensation is optimized for either low output
ripple or sm all solution siz e, and will result in a wide
loop bandwidth and excellent load transient
perform ance for m ost appl ication s. See Table 6 for
compensation values for both options based on
input and output voltage conditions.
In some cases modifications to the compensation
may be required. The EN2340QI provides the
capability to modify the control loop response to
allow for customization for specific applications.
For more information, contact Altera MySupport
(www.altera.com/mysupport).
VOUT
VFB
RACA
RCA
RB
Figure 11 : External Feedb ack
Compensation. See T able 6 for details.
Inpu t Cap acitor Selectio n
The EN2340QI requires a 22µF/1206 input
capacitor. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or eq ui val ent dielec tric formulations
must not be used as these lose too much
capacitance with f requency, temperat ure and
bias voltage. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling. Table 3 contains a list of
recommended input capacitors.
Recommended Input C apacitors
Description
MFG
P/N
22µF, 16V,
X5R, 10%,
1206 Murata GRM31CR61C226ME15
22µF, 16V,
X5R, 20%,
1206
Taiyo Yuden EMK316ABJ226ML-T
Table 3: Rec om m ended Input Capac i tors
Output Cap acitor S electio n
As seen from Table 6, the EN2340QI has been
optimized for use with either two 47µF /1206 or two
22µF/0805 output capacitors. Low ESR ceramic
capacitors are required with X5R or X7R rated
dielectric form ulation. Y5V or eq ui val ent diel ect ri c
formulations must not be used as these lose
too much capacitance with frequency,
tem pera tu re and bia s vo lt ag e. Tab le 4 contains a
list of recommended output capacitors. In some
applications, extra bulk capacitance is required at
−
×
=
Ω=
nominal
0.75V is
)(
value.calculated the
n higher tha valuestandard
closest toup R Round
)kin (R
180
A
A
FB
FBOUT
AFB
B
A
V
VV RV
R
VOUT
R
www.altera.com/enpirion, Page 14
06878 October 9, 2013 Rev E
EN2340QI
the load. In this case, up to 1000µF of bulk
capacitance m ay be used at the load as long as the
minimum ESR between the device output and the
bulk capacitance is maintained. Table 4 shows the
recommended compensation components for
applications that require bulk capacitance at the
load.
PVIN (V)
VOUT (V)
Min. ESR
Compensation
4.5 to 14
≥2.5
4mΩ
COUT = 2x47µF/1206
Bulk Cap ≤ 1000µF
CA = 100pF
RA = 250kΩ
RCA = 5kΩ
≥10
0.6 to 1.5
9mΩ
1.5 to 2.5
7mΩ
<10
0.6 to 1.5
12mΩ
1.5 to 2.5
9mΩ
Table 4: M i nimum E SR for B ul k Capaci tance at Load
Output ripple voltage is determined by the
aggregate output capacitor impedance. Capacitor
impedance, denoted as Z, is comprised of
capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal ZZZZ 1
...
111
21
+++=
Recommended Output Capacitors
Description
MFG
P/N
47µF, 6.3V , X5R,
20%, 1206 Murata GRM31CR60J476ME19L
47µF, 10V, X5R,
20%, 1206 Taiyo
Yuden LMK316BJ476ML-T
22µF, 10V, X5R,
20%, 0805 Panasonic ECJ-2FB1A226M
22µF, 10V, X5R,
20%, 0805 Taiyo
Yuden LMK212BJ226MG-T
Ta bl e 5: Rec om m ended O ut put Capaci tors
www.altera.com/enpirion, Page 15
06878 October 9, 2013 Rev E
EN2340QI
Low V OUT Ripple
Sma lle st Solution Size
CIN = 1 x 22µF/1206
C
OUT
= 2 x 47µF/1206
RA= 180/(Vout
0.5
) kΩ
C
IN
= 1 x 22µF/1206
COUT = 2 x 22µF/0805
PVIN VOUT CA (pF) RCA
(kΩ)
Nominal
Ripple
(mV)
Nominal
Deviation
(mV)
(Note 7)
RA (kΩ) CA (pF) RCA
(kΩ)
Nominal
Ripple
(mV)
Nominal
Deviation
(mV)
(Note 7)
14V
≤1.0V
10
30
≤5
≤47
75
27
0.1
≤10
≤34
1.2V
12
27
6
48
43
39
0.1
13
33
1.5V
15
27
5
53
56
39
0.1
15
38
1.8V
22
27
6
54
56
39
0.1
18
41
2.5V
27
24
8
55
51
39
0.1
26
59
3.3V
39
18
11
63
51
33
0.1
35
63
5.0V
47
8.2
18
97
75
22
5.1
42
115
12V
≤1.0V
18
22
≤4
≤48
27
47
0.1
≤10
≤35
1.2V
22
22
5
49
75
47
0.1
13
37
1.5V
27
20
5
53
75
47
0.1
15
38
1.8V
33
20
6
54
75
47
0.1
17
44
2.5V
47
18
7
54
56
47
0.1
25
59
3.3V
56
15
10
66
51
39
0.1
32
63
5.0V
56
10
16
99
75
22
5.1
39
128
10V
≤1.0V
33
18
≤3
≤45
27
82
0.1
≤9
≤35
1.2V
39
18
4
46
30
100
0.1
13
39
1.5V
47
18
5
54
30
100
0.1
14
43
1.8V
56
16
6
56
30
100
0.1
17
50
2.5V
68
12
7
57
75
56
0.1
26
70
3.3V
82
10
9
68
56
47
0.1
30
83
5.0V
100
4.3
14
98
75
33
5.1
33
140
8.0V
≤1.0V
100
8.2
≤3
≤51
100
100
0.1
≤10
≤41
1.2V
100
8.2
4
51
100
100
0.1
12
43
1.5V
100
8.2
4
54
100
100
0.1
14
46
1.8V
100
8.2
5
57
100
100
0.1
16
53
2.5V
100
8.2
6
64
91
82
0.1
23
71
3.3V
100
8.2
8
70
75
56
0.1
25
85
5.0V
100
8.2
10
110
75
56
5.1
30
127
6.6V
≤1.0V
100
8.2
≤3
≤60
100
100
0.1
≤9
≤46
1.2V
100
8.2
4
63
100
100
0.1
12
51
1.5V
100
8.2
4
65
100
100
0.1
14
56
1.8V
100
8.2
5
68
100
100
0.1
16
61
2.5V
100
8.2
5
75
100
100
0.1
19
83
3.3V
100
8.2
6
85
91
82
0.1
22
106
5V
≤1.0V
100
8.2
≤3
≤73
100
100
0.1
≤9
≤56
1.2V
100
8.2
3
75
100
100
0.1
11
63
1.5V
100
8.2
4
76
100
100
0.1
13
70
1.8V
100
8.2
4
80
100
100
0.1
13
78
2.5V
100
8.2
4
88
100
100
0.1
14
98
Table 6: RA, C A, and R CA Values f or Various PVI N/V OUT C ombinations: Low VOUT Ripple vs. Smallest Solution Size. See
Figure 11. Use the equations in Figure 11 to calcul ate RA (for low VOUT ripple option) and RB.
Note 7: Nom i nal Devi at i on i s for a 2A l oad t ransi ent step.
Note 8: For compensati on values of output voltage in between the specif ied output voltages, choose co mpensat ion valu es
of the l ower out put voltage setti ng.
www.altera.com/enpirion, Page 16
06878 October 9, 2013 Rev E
EN2340QI
Thermal Considerations
Therm al consideratio ns are im porta nt power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN2340QI DC-DC converter is
packaged in an 8x11x3mm 68-pin QFN package.
The QF N package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The r ecommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
The EN2340QI is guaranteed to support the full 4A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN2340QI.
Example:
VIN = 12V
VOUT = 3.3V
IOUT = 4A
First calculate the output power.
POUT = 3.3V x 4A = 13.2W
Next, determine the input power based on the
efficiency (η) shown in Figure 12.
Fi gure 12: Effici ency vs. Output Current
For VIN = 12V, VOUT = 3.3V at 4A, η ≈ 91%
η = POUT / PIN = 91% = 0.91
PIN = POUT / η
PIN ≈ 13.2W / 0.9 ≈ 14.51W
The pow er dissipati on (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 14.51W – 13.2W ≈ 1.31W
With the pow er dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how m uch the tem perature will rise in the device for
every watt of power dissipation. The EN2340QI has
a θJA value of 18 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 1.31W x 18°C/W = 23.5°C ≈ 24°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temper ature to be 25° C.
TJ = TA + ΔT
TJ ≈ 25°C + 24°C ≈ 49°C
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
m ax i m um am bient tem perature (TAMAX) all ow ed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 24°C ≈ 101°C
The m ax im um am bient tem perature the device can
reach is 101°C given the input and output
conditions. Note that the efficiency will be slightly
low er at higher tem peratur es and this calculation is
an estimate.
0
10
20
30
40
50
60
70
80
90
100
00.5 11.5 22.5 33.5 4
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
CONDITIONS
VIN = 12.0V
91%
www.altera.com/enpirion, Page 17
06878 October 9, 2013 Rev E
EN2340QI
Layout Recommendation
Fi gure 14: Top Layer Layout with Cri t i cal Com ponents
(Top Vi ew). See Figure 13 for corresponding schematic.
This l ayout only shows the critical com ponents and
top layer traces for m ini mum footprint in single-
supply m ode. A lternate ci rcuit configur atio ns &
other low-power pins need to be connected and
routed according to custom er application. Please
see the Gerber files at www.altera.com for details
on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2340QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes . The +V a n d
GND traces between the capacitors and the
EN2340QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to pr ovide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
conti nuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The therm al pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vi as m ust have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output curre nt loops. If vias cannot
be placed under the capacitor s, then place them on
both sides of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 14 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 14.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC conver ter, try not to run sensitive signal or
control li nes underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor . Keep t h e
sense trace short in order to avoid noise coupling
into the node. Contact Altera MySupport for any
remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 14). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pins 52
and 53 instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provide s schem atic and layou t
reviews for all customer designs. Contact Altera
MySupport
for detailed support
(www.altera.com/mysupport).
www.altera.com/enpirion, Page 19
06878 October 9, 2013 Rev E
EN2340QI
Design Considerations for Lead-Frame Based Modules
Expose d Me tal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
I n the assem bly process lead fram e construction requ ires that, for m echanica l suppor t, som e of the lead-frame
canti levers be ex posed at the point w here wire-bond or internal passives are attached. This r esults in several
small pads being exposed on the bottom of the package, as shown in F igure 15.
Only the therm al pad and the perim eter pads are to be m echani ca lly or electrica lly connected to the PC board.
The PC B top layer under the EN2340QI should be clear of any m etal (copper pou rs, tra ces, or vias) ex cept for
the therm al pad. The “shaded-ou t” are a in Figure 15 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area r uns the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB gr ound pad. T his will prevent excess solder fr om
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
Enpir ion Manufacturing Application Note for more details and recommendations.
Fi gure 15: Lead-Fram e exposed m etal (B ottom Vi ew)
Shaded area hi ghl i ght s ex posed m etal that i s not to be m echani cal l y or el ectri cal l y connect ed t o the PCB .
www.altera.com/enpirion, Page 20
06878 October 9, 2013 Rev E
EN2340QI
Contact Information
Altera Corporation
101 Innovation Dr ive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
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www.altera.com/enpirion, Page 23
06878 October 9, 2013 Rev E
