CY2CC810OI - Cypress Semiconductor

1:10 Clock Fanout Buffe

CY2CC810

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-07056 Rev. *E Revised September 5, 2006

Features

• Low-voltage operation

•V

DD range from 2.5V to 3.3V

• 1:10 fanout

• Over voltage tolerant input hot swappable

• Drives either a 50-Ohm or 75-Ohm transmissi on line

• Low-input capacitance

• 250 ps typical output-to-output skew

• 19 ps typical DJ jitter

• Typical propagation delay < 3.5 ns

• High-speed opera tion > 500 MHz

• Industrial versions available

• Available packages include: SOIC, SSOP

Description

The Cypress series of network circuits are produced using

advanced 0.35-micron CMOS technology, achieving the

industry’s fastest logic and buffers.

The Cypress CY2CC810 fanout buffer features one input and

ten outputs. Designed for data communications clock

management applications, the large fanout from a single input

reduces loading on the input clock.

AVCMOS-type outputs dynamically adjust for variable

impedance matchi ng and reduce noise overall.

Block Diagram Pin Configuration

OUTPUT

(AVCMOS)

Q10

GND

VDD

INPUT

CY2CC810

20 pin SOIC/ SS OP

VDD

Q10

GND

VDD

GND

VDD

GND

VDD

GND

Pin Description

Pin Number Pin Name Description

1 IN Input LVCMOS

2, 6, 10, 13, 17 GND Ground Power

4, 8, 15, 20 VDD Power Supply Power

3, 5, 7, 9, 11, 12, 14, 16, 18, 19 Q1... Q10 Output AVCMOS

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CY2CC810

Document #: 38-07056 Rev. *E Page 2 of 9

Absolute Maximum Conditions[1, 2]

Parameter Description Min. Max. Unit

VDD VDD Ground Supply voltage –0.5 4.6 V

VIN Input Supply Voltage to Ground Potential –0.5 5.8 V

VOUT Output Supply Voltage to Ground Potential –0.5 VDD +1 V

TSTemperature, Storage –65 150 °C

TATemperature, Operating Ambient –40 85 °C

Power Dissipation 0.75 W

DC Electrical Characteristics @ 3.3V (see Figure 5)

Parameter Description Conditions Min. Typ. Max. Unit

VOH Output High Voltage VDD = Min., VIN = VIH or VIL IOH = –12 mA 2.3 3.3 V

VOL Output Low Voltage VDD = Min. , VIN = VIH or VIL IOL = 12 mA 0.2 0.5 V

VIH Input High Voltage Guaranteed Logic High Level 2 5.8 V

VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V

IIH Input High Current VDD = Max. VIN = 2.7V 1 µA

IIL Input Low Current VDD = Max. VIN = 0.5V –1 µA

IIInput High Current VDD = Max., VIN = VDD(Max.) 20 µA

VIK Clamp Diode Voltage VDD = Min., IIN = –18 mA –0.7 –1.2 V

IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA

OOFF Power down Disable VDD = GND, VOUT = < 4.5V 100 µA

VHInput Hysteresis VDD = Min., VIN = VIH or VIL 80 mV

DC Electrical Characteristics @ 2.5V (see Figure 1)

Parameter Description Conditions Min. Typ. Max. Unit

VOH Output High Voltage VDD = Min., VIN = VIH or VIL IOH = –7 mA 1.8 V

IOH = 12 mA 1.6 V

VOL Output Low Voltage VDD = Min., V IN = VIH or VIL IOL = 12 mA 0.65 V

VIH Input High Voltage Guaranteed Logic High Level 1.6 5.0 V

VIL Input Low Voltage Guaranteed Logic Low Level 0.8 V

IIH Input High Current VDD = Max. VIN = 2.4V 1 µA

IIL Input Low Current VDD = Max. VIN = 0.5V –1 µA

IIInput High Current VDD = Max., VIN = VDD(Max.) 20 µA

VIK Clamp Diode Voltage VDD = Min. , IIN = –18 mA –0.7 –1.2 V

IOK Continuous Clamp Current VDD = Max., VOUT = GND –50 mA

OOFF Power-down Disable VDD = GND, VOUT = < 4.5V 100 µA

VHInput Hysteresis 80 mV

Note

1. S tresses great er than those listed u nder absolute maximum ratings may cause pe rmanent damage t o the devi ce. This is intended to be a stress rat ing only and

functional operat ion of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure

to absolute maximum rating conditions fo r extended periods may affect reliability.

2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during powe r-up. Power supply sequencing is NOT requi red.

Capacitance

Parameter Description Test Conditions Min. Typ. Max. Unit

Cin Input Capacitance VIN = 0V 2.5 pF

Cout Output Capacitance VOUT = 0V 6.5 pF

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CY2CC810

Document #: 38-07056 Rev. *E Page 3 of 9

Power Supply Characteristics (see Figure 5)

Parameter Descripti on Test Conditio ns Min. Typ. Max. Unit

∆ICC Delta ICC Quiescent Power

Supply Current (IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD = Max.

and VIN = VDD – 0.6V) 50 µA

ICCD Dynamic Power Supply

Current VDD = Max.

Input toggling 50% Duty Cycle, Outputs Open 0.63 mA/

MHz

ICTotal Power Supply Current VDD = Max.

Input toggling 50% Duty Cycle, Outputs Open

fL = 40 MHZ

25 mA

tPU Power-up time for all VDDs Power-up to reach minimum specified voltage

(power ramp must be monotonic) 0.05 500 ms

High-frequency Parametrics

Parameter Description Test Conditions Min. Typ. Max. Unit

DJJitter, Deterministic 50% duty cycle tW(50–50)

The “point to point load circuit”

Output Jitter – Input Jitter

2.5V 23 35 ps

3.3V 19 30 ps

Fmax(3.3V) Maximum frequency

VDD = 3.3V 50% duty cycle tW(50–50)

Standard Load Circuit. See Figure 5 160 MHz

50% duty cycle tW(50–50)

The “point to point load circuit” See Figure 7 650

Fmax(2.5V Maximum frequency

VDD = 2.5 V The “point to point load circuit”

VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 7 200 MHz

Fmax(20) Maximum frequency

VDD = 3.3 V 20% duty cycle tW(20–80)

The “point to point load circuit”

VIN = 3.0V/0.0V VOUT = 2.3V/0.4V

See Figure 7 250 MHz

Maximum frequency

VDD = 2.5 V The “point to point load circuit”

VIN = 2.4V/0.0V VOUT = 1.7V/0.7V See Figure 3 200 MHz

tWMinimum pulse

VDD = 3.3 V The “point to point load circuit”

VIN = 3.0V/0.0V F = 100 MHz

VOUT = 2.0V/0.8V

See Figure 7 1ns

Minimum pulse

VDD = 2.5 V The “point to point load circuit”

VIN = 2.4V/0.0V F = 100 MHz

VOUT = 1.7V/0.7V

See Figure 3 1

AC Switching Characteristics @ 3.3V, VDD = 3.3V ±5%, Temperature = –40°C to +85°C

Parameter Description Min. Typ. Max. Unit

tPLH Propagation Delay – Low to High See Figure 4 1.5 2.7 3.5 ns

tPHL Propagation Delay – High to Low 1.5 2.7 3.5 ns

tROutput Rise Time 0.8 V/ns

tFOutput Fall Time 0.8 V/ns

tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.25 0.38 ns

tSK(p) Pulse Skew: Skew between opposite transitions of the same output

(tPHL – tPLH). See Figure 9 0.2 ns

tSK(t) Package Skew: Skew between outputs of different packages at the

same power supply voltage, temperature and package type. See Figure 11 0.42 ns

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CY2CC810

Document #: 38-07056 Rev. *E Page 4 of 9

Parameter Measurement Information: VDD @2.5V

Figure 1. Load Circuit [3,4,5]

Figure 2. Voltage Waveforms Pulse Duration[6]

Figure 3. Point to Point Lo ad Circuit[3,4,5]

AC Switching Characteristics @ 2.5V, VDD = 2.5V ±5%, Temperature = –40°C to +85°C

Parameter Description Min. Typ. Max. Unit

tPLH Propagation Delay – Low to High See Figure 4 1.5 2.0 3.5 ns

tPHL Propagation Delay – High to Low 1.5 2.0 3.5 ns

tROutput Rise Time 0.8 V/ns

tFOutput Fall Time 0.8 V/ns

tSK(0) Output Skew: Skew between outputs of the same package (in phase) See Figure 10 0.25 0.38 ns

tSK(p) Pulse Skew: Skew between opposite transitions of the same output

(tPHL – tPLH). See Figure 9 0.4 ns

tSK(t) Package Skew: Skew between outputs of different packages at the

same power supply voltage, temperature and package type. See Figure 11 0.65 ns

Notes

3. CL includes probe and jig capacitance.

4. All input pulses are supplied by generators having the f ollowing characteristics: PRR < 100 MHz, Z0 = 50W, tR < 2.5 nS, tF < 2.5 nS.

5. The outputs are measured one at a time with one transition per measurement.

6. TPLH and TPHL are the same as tpd..

F ro m Ou tp u t

U nder Test

CL = 50 pF 500 ohm

2.0 V

0 V

Input tw(20-80)

2.0 V

0 V

1.25 V 1.25 V

Input tw(50-50)

1.25 V

From O utput

Under Test

CL = 3 pF 500 ohm

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CY2CC810

Document #: 38-07056 Rev. *E Page 5 of 9

Figure 4. Voltage WaveformsPropagation Delay Times[4]

Parameter Measurement Information: VDD @3.3V

Figure 5. Load Circuit [3,4,5]

Figure 6. Voltage Waveforms–Pulse Duration[6]

Figure 7. Point to Point Lo ad Circuit[3,4,5]

Figure 8. Voltage Waveforms Propagation Delay Times[4]

1.25 V

1.25 V 1.25 V

1.25 V

tPLH tPHL

2.0 V

VOH

VOL

0 VInput

Output

From O utput

Under Test

CL = 50 pF 500 ohm

2.7V

0 V

Input tw(20-80)

2.7V

0 V

1.5V 1.5V

Input tw(50-50)

1.5V

From Output

Under Test

CL = 3 pF 500 ohm

1.5V

1.5V 1.5V

1.5V

tPLH tPHL

2.7V

VOH

VOL

0 VInput

Output

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CY2CC810

Document #: 38-07056 Rev. *E Page 6 of 9

Figure 9. Pulse Skew–tsk(p)

Figure 10. Output Skew–tsk(0)

Figure 11. Package Skew–tsk(t)

INPUT

OUTPUT

tPLH tPHL

tsk(P) = l tPHL - tPLH l

1.5V

VOH

1.5V

VOL

INPUT

OUTPUT 1

tPLH1 tPHL1

tsk(P) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l

1.5V

VOH

1.5V

VOL

OUTPUT 2

VOH

1.5V

VOL

tsk(O) tsk(O)

tPLH 2 tPLH 2

INPUT

PACKAGE 1 OUTPUT

tPLH1 tPHL1

tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l

1.5V

VOH

1.5V

VOL

PACKAGE 2 OUTPUT

VOH

1.5V

VOL

tsk(t) tsk(t)

tPLH 2 tPLH 2

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CY2CC810

Document #: 38-07056 Rev. *E Page 7 of 9

Package Drawing and Dimensions

Figure 12. 20-Lead (300-Mil) SOIC S20.3/SZ20.3

Ordering Information

Part Number Package Type Product Flow

CY2CC810OI 20-pin SSOP Industrial, –40°C to 85°C

CY2CC810OIT 20-pin SSOP–Tape and Reel Industrial, –40°C to 85°C

CY2CC810OC 20-pin SSOP Commercial, 0°C to 70°C

CY2CC810OCT 20-pin SSOP–Tape and Reel Commercial, 0°C to 70°C

Lead-free

CY2CC810OXC 20-pin SSOP Commercial, 0°C to 70°C

CY2CC810OXCT 20-pin SSOP–Tape and Reel Commercial, 0°C to 70°C

CY2CC810OXI 20-pin SSOP Industrial, –40°C to 85°C

CY2CC810OXIT 20-pin SSOP–Tape and Reel Industrial, –40°C to 85°C

PIN 1 ID

SEATING PLANE

0.497[12.623]

0.513[13.030]

110

11 20

0.291[7.391]

0.300[7.620]

0.394[10.007]

0.419[10.642]

0.050[1.270]

TYP.

0.092[2.336]

0.105[2.667]

0.004[0.101]

0.0118[0.299]

0.0091[0.231]

0.0125[0.317]

0.015[0.381]

0.050[1.270]

0.013[0.330]

0.019[0.482]

0.026[0.660]

0.032[0.812]

0.004[0.101]

PART #

S20.3 STANDARD PKG.

SZ20.3 LEAD FREE PKG.

MIN.

MAX.

NOTE :

1. JEDEC STD REF MO-119

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE

3. DIMENSIONS IN INCHES

4. PACKAGE WEIGHT 0.55gms

DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.

51-85024-*C

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CY2CC810

Document #: 38-07056 Rev. *E Page 8 of 9

© Cypress Semi con duct or Cor po ra tion , 2006. The informati on con tained herein i s su bj ect to change without no ti ce. Cypress Semiconductor Corpo ration assu mes no respo nsibility for the use

of any circuitry other than circuitry em bo died i n a C yp re ss pro duct. Nor does it convey or im ply any license under patent or other ri g hts. Cypress products are not w a rr a nte d no r intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Figure 13. 20-lead (5.3-mm) Shrunk Small Ou tlin e Package O20

All product and company names mentioned in this document are the trademarks of their respective holders.

51-85077-*C

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CY2CC810

Document #: 38-07056 Rev. *E Page 9 of 9

Document History Page

Document Titl e: CY2CC810 1:10 Clock Fanout Buffer

Document #: 38-07056

REV. ECN NO. Issue Date Orig. of

Change Description of Cha nge

** 107081 06/07/01 IKA Convert from IMI to Cypress

*A 114315 05/09/02 TSM ∆ IDD Validation

*B 119117 10/07/02 RGL Added 5.8 as the Max. value of VIH in the DC Electrical Characteristics

@3.3V table.

Changed the Max. value of VIH from 1.8 to 5.0 in the DC Electrical Charac-

teristics @2.5V table.

*C 122743 12/14/02 RBI Added power up requirements to maximum ratings information.

*D 387761 See ECN RGL Added typical values

Updated jitter and skew specs.

Removed devices with SOIC package

Added Lead-free SSOP package

*E 499991 See ECN RGL Added tpu parameter in the Power Supply Characteristics table

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