MK22FN1M0AVLK12 - FREESCALE - Datasheet.Directory

Kinetis K22F Sub-Family Data

Sheet

120 MHz ARM® Cortex®-M4-based Microcontroller with FPU

The K22 product family members are optimized for cost-sensitive

applications requiring low-power, USB connectivity, processing

efficiency with floating point unit. It shares the comprehensive

enablement and scalability of the Kinetis family. This product

offers:

• Up to 1 MB of flash memory with up to 128 KB of SRAM

• Small package with high memory density

• Run power consumption down to 279 μA/MHz. Static

power consumption down to 5.1 μA with full state retention

and 5 μs wakeup. Lowest Static mode down to 268 nA

• USB LS/FS OTG 2.0 with embedded 3.3 V, 120 mA LDO

voltage regulator

Performance

• Up to 120 MHz ARM Cortex-M4-based core with DSP

instructions delivering 1.25 Dhrystone MIPS per MHz

Memories and memory interfaces

• Up to 1 MB program flash memory and 128 KB RAM

• 4 KB FlexRAM and 128 KB FlexNVM on FlexMemory

devices

• FlexBus external bus interface

System peripherals

• Multiple low-power modes; low leakage wakeup unit

• Memory protection unit with multi-master protection

• 16-channel DMA controller

• External watchdog monitor and software watchdog

Security and integrity modules

• Hardware CRC module

• 128-bit unique identification (ID) number per chip

Analog modules

• Two 16-bit SAR ADCs

• One 12-bit DAC

• Three analog comparators (CMP)

• Voltage reference

Communication interfaces

• USB full-/low-speed On-the-Go controller

• USB Device Charger detect

• Controller Area Network (CAN) module

• Three SPI modules

• Three I2C modules

• Six UART modules

• Secure Digital host controller (SDHC)

• I2S module

Timers

• Two 8-channel Flex-Timers (PWM/Motor Control)

• Two 2-channel Flex-Timers (PWM/Quad Decoder)

• Periodic interrupt timers and 16-bit low-power timer

• Carrier modulator transmitter

• Real-time clock

• Programmable delay block

Clocks

• 3 to 32 MHz and 32 kHz crystal oscillator

• PLL, FLL, and multiple internal oscillators

Operating Characteristics

• Voltage range: 1.71 to 3.6 V

• Flash write voltage range: 1.71 to 3.6 V

• Temperature range (ambient): –40 to 105°C

MK22FX512AVLK12

MK22FN1M0AVLK12

80 LQFP

12 x 12 x 1.6 mm Pitch 0.5 mm

Freescale Semiconductor, Inc. K22P80M120SF5V2

Data Sheet: Technical Data Rev 5, 03/2015

Freescale reserves the right to change the detail specifications as may be required to

Ordering Information 1

Part Number Memory Maximum number of I\O's

Flash (KB) SRAM (KB)

MK22FX512AVLK12 512 KB 128 52

MK22FN1M0AVLK12 1 MB 128 52

1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number

search.

Related Resources

Type Description Resource

Selector

Guide

The Freescale Solution Advisor is a web-based tool that features

interactive application wizards and a dynamic product selector.

Solution Advisor

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

K20PB1

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

K22P80M50SF5V2RM1

Data Sheet The Data Sheet includes electrical characteristics and signal

connections.

K22P80M50SF5V21

Package

drawing

Package dimensions are provided in package drawings. • LQFP 80-pin:

98ASS23174W1

1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.

2Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

Memories and Memory Interfaces

Program

flash RAM

12-bit DAC

6-bit DAC

CRC

Programmable

Analog Timers Communication InterfacesSecurity

and Integrity

SPI

Carrier

modulator

transmitter

FlexMemory

Clocks

Frequency-

Core

Debug

interfaces DSP

Interrupt

controller

comparator

Analog

Voltage

reference

Secure

Digital

Low power

timer

Human-Machine

Interface (HMI)

GPIO

System

protection

Memory

DMA

Internal

watchdogs

and external

Low-leakage

wakeup

locked loop

Serial

programming

interface

Phase-

locked loop

reference

Internal

clocks

delay block

timers

interrupt

Periodic

External

bus

real-time

Independent

clock

oscillators

Low/high

frequency

UART

Cortex™-M4ARM

Available only in K21

LEGEND

Kinetis K21/22F Family

Tamper

detect

Random

Number

Generator

Hardware

Encryption

USB charger

detect

USB voltage

regulator

USB OTG

LS/FS/HS

USB LS/FS

transceiver

Floating-

point unit

Timers

x4 (20ch)

CAN

16-bit ADC

Figure 1. K20 block diagram

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 3

Freescale Semiconductor, Inc.

Table of Contents

1 Ratings....................................................................................5

1.1 Thermal handling ratings................................................. 5

1.2 Moisture handling ratings................................................ 5

1.3 ESD handling ratings.......................................................5

1.4 Voltage and current operating ratings............................. 5

2 General................................................................................... 6

2.1 AC electrical characteristics.............................................6

2.2 Nonswitching electrical specifications..............................7

2.2.1 Voltage and current operating requirements.....7

2.2.2 LVD and POR operating requirements............. 8

2.2.3 Voltage and current operating behaviors.......... 8

2.2.4 Power mode transition operating behaviors......10

2.2.5 Power consumption operating behaviors.......... 10

2.2.6 EMC radiated emissions operating behaviors...14

2.2.7 Designing with radiated emissions in mind....... 15

2.2.8 Capacitance attributes...................................... 15

2.3 Switching specifications...................................................15

2.3.1 Device clock specifications............................... 15

2.3.2 General switching specifications....................... 16

2.4 Thermal specifications.....................................................17

2.4.1 Thermal operating requirements....................... 17

2.4.2 Thermal attributes............................................. 17

3 Peripheral operating requirements and behaviors.................. 19

3.1 Core modules.................................................................. 19

3.1.1 Debug trace timing specifications..................... 19

3.1.2 JTAG electricals................................................ 19

3.2 System modules.............................................................. 22

3.3 Clock modules................................................................. 22

3.3.1 MCG specifications........................................... 22

3.3.2 Oscillator electrical specifications..................... 25

3.3.3 32 kHz oscillator electrical characteristics.........27

3.4 Memories and memory interfaces................................... 27

3.4.1 Flash (FTFE) electrical specifications............... 27

3.4.2 EzPort switching specifications......................... 32

3.4.3 Flexbus switching specifications....................... 33

3.5 Security and integrity modules........................................ 36

3.6 Analog............................................................................. 36

3.6.1 ADC electrical specifications.............................37

3.6.2 CMP and 6-bit DAC electrical specifications.....41

3.6.3 12-bit DAC electrical characteristics................. 43

3.6.4 Voltage reference electrical specifications........ 46

3.7 Timers..............................................................................47

3.8 Communication interfaces............................................... 47

3.8.1 USB electrical specifications............................. 47

3.8.2 USB DCD electrical specifications.................... 48

3.8.3 USB VREG electrical specifications..................48

3.8.4 CAN switching specifications............................ 49

3.8.5 DSPI switching specifications (limited voltage

range)................................................................49

3.8.6 DSPI switching specifications (full voltage

range)................................................................51

3.8.7 I2C switching specifications.............................. 52

3.8.8 UART switching specifications.......................... 53

3.8.9 SDHC specifications......................................... 53

3.8.10 I2S switching specifications.............................. 54

4 Dimensions............................................................................. 66

4.1 Obtaining package dimensions....................................... 66

5 Pinout......................................................................................67

5.1 K22 Signal Multiplexing and Pin Assignments.................67

5.2 K22 Pinouts..................................................................... 71

6 Revision History...................................................................... 72

7 Copyright................................................................................. 0

8 Legal....................................................................................... 0

4Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

1 Ratings

1.1 Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.2 Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

1.3 ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model -2000 +2000 V 1

VCDM Electrostatic discharge voltage, charged-device

model

-500 +500 V 2

ILAT Latch-up current at ambient temperature of 105°C -100 +100 mA 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

1.4 Voltage and current operating ratings

Ratings

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 5

Freescale Semiconductor, Inc.

Symbol Description Min. Max. Unit

VDD Digital supply voltage –0.3 3.8 V

IDD Digital supply current — 185 mA

VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V

VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V

IDMaximum current single pin limit (applies to all digital pins) –25 25 mA

VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

VUSB0_DP USB0_DP input voltage –0.3 3.63 V

VUSB0_DM USB0_DM input voltage –0.3 3.63 V

VBAT RTC battery supply voltage –0.3 3.8 V

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

2 General

2.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

80%

20%

50%

VIL

Input Signal

VIH

Fall Time

High

Low

Rise Time

Midpoint1

The midpoint is VIL + (VIH - VIL) / 2

Figure 2. Input signal measurement reference

All digital I/O switching characteristics assume:

1. output pins

• have CL=30pF loads,

• are configured for fast slew rate (PORTx_PCRn[SRE]=0), and

• are configured for high drive strength (PORTx_PCRn[DSE]=1)

2. input pins

• have their passive filter disabled (PORTx_PCRn[PFE]=0)

General

6Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

2.2 Nonswitching electrical specifications

2.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol Description Min. Max. Unit Notes

VDD Supply voltage 1.71 3.6 V

VDDA Analog supply voltage 1.71 3.6 V

VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V

VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V

VBAT RTC battery supply voltage 1.71 3.6 V

VIH Input high voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.71 V ≤ VDD ≤ 2.7 V

0.7 × VDD

0.75 × VDD

—

VIL Input low voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.71 V ≤ VDD ≤ 2.7 V

—

0.35 × VDD

0.3 × VDD

VHYS Input hysteresis 0.06 × VDD — V

IICDIO Digital pin negative DC injection current — single pin

• VIN < VSS-0.3V -5 — mA

IICAIO Analog2, EXTAL, and XTAL pin DC injection current

— single pin

• VIN < VSS-0.3V (Negative current injection)

• VIN > VDD+0.3V (Positive current injection)

-5

—

IICcont Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

• Negative current injection

• Positive current injection

-25

—

+25

VODPU Open drain pullup voltage level VDD VDD V4

VRAM VDD voltage required to retain RAM 1.2 — V

VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT — V

1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode

connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN

(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC

injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.

2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL

and XTAL are analog pins.

General

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 7

Freescale Semiconductor, Inc.

3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or

greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|

IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection

currents.

4. Open drain outputs must be pulled to VDD.

2.2.2 LVD and POR operating requirements

Table 2. VDD supply LVD and POR operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V

VLVDH Falling low-voltage detect threshold — high

range (LVDV=01)

2.48 2.56 2.64 V

VLVW1H

VLVW2H

VLVW3H

VLVW4H

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

VHYSH Low-voltage inhibit reset/recover hysteresis —

high range

— 80 — mV

VLVDL Falling low-voltage detect threshold — low

range (LVDV=00)

1.54 1.60 1.66 V

VLVW1L

VLVW2L

VLVW3L

VLVW4L

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

VHYSL Low-voltage inhibit reset/recover hysteresis —

low range

— 60 — mV

VBG Bandgap voltage reference 0.97 1.00 1.03 V

tLPO Internal low power oscillator period — factory

trimmed

900 1000 1100 μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR_VBAT Falling VBAT supply POR detect voltage 0.8 1.1 1.5 V

General

8Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

2.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol Description Min. Typ Max. Unit Notes

VOH Output high voltage — high drive strength

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -8mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA

VDD – 0.5

—

Output high voltage — low drive strength

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA

VDD – 0.5

—

IOHT Output high current total for all ports — — 100 mA

VOL Output low voltage — high drive strength

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA

—

0.5

Output low voltage — low drive strength

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 0.6mA

—

0.5

IOLT Output low current total for all ports — — 100 mA

IIND Input leakage current, digital pins

• VSS ≤ VIN ≤ VIL

• All digital pins

• VIN = VDD

• All digital pins except PTD7

• PTD7

—

0.002

0.004

0.5

μA

2, 3

IIND Input leakage current, digital pins

• VIL < VIN < VDD

• VDD = 3.6 V

• VDD = 3.0 V

• VDD = 2.5 V

• VDD = 1.7 V

—

μA

IIND Input leakage current, digital pins

• VDD < VIN < 5.5 V

—

μA

IOZ Hi-Z (off-state) leakage current (per pin) — — 0.25 μA

RPU Internal pullup resistors 20 35 50 kΩ 4

RPD Internal pulldown resistors 20 35 50 kΩ 5

1. Open drain outputs must be pulled to VDD.

2. Measured at VDD=3.6V

3. Internal pull-up/pull-down resistors disabled.

4. Measured at VDD supply voltage = VDD min and Vinput = VSS

General

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 9

Freescale Semiconductor, Inc.

5. Measured at VDD supply voltage = VDD min and Vinput = VDD

2.2.4 Power mode transition operating behaviors

All specifications except tPOR, and VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 100 MHz

• Bus clock = 50 MHz

• FlexBus clock = 50 MHz

• Flash clock = 25 MHz

Table 5. Power mode transition operating behaviors

Symbol Description Min. Max. Unit Notes

tPOR After a POR event, amount of time from the point VDD

reaches 1.71 V to execution of the first instruction

across the operating temperature range of the chip.

— 300 μs

• VLLS0 → RUN — 183 μs

• VLLS1 → RUN — 183 μs

• VLLS2 → RUN — 105 μs

• VLLS3 → RUN — 105 μs

• LLS → RUN — 5.0 μs

• VLPS → RUN — 4.4 μs

• STOP → RUN — 4.4 μs

2.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

IDDA Analog supply current — — See note mA 1

IDD_RUN Run mode current — all peripheral clocks

disabled, code executing from flash

—

33.57

33.51

36.2

36.1

Table continues on the next page...

General

10 Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

Table 6. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

• @ 1.8V

• @ 3.0V

IDD_RUN Run mode current — all peripheral clocks

enabled, code executing from flash

• @ 1.8V

• @ 3.0V

• @ 25°C

• @ 125°C

—

46.36

46.31

57.4

50.1

49.9

—

3, 4

IDD_WAIT Wait mode high frequency current at 3.0 V — all

peripheral clocks disabled

— 18.2 — mA 2

IDD_WAIT Wait mode reduced frequency current at 3.0 V

— all peripheral clocks disabled

— 7.2 — mA 5

IDD_VLPR Very-low-power run mode current at 3.0 V — all

peripheral clocks disabled

— 1.21 — mA 6

IDD_VLPR Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

— 1.88 — mA 7

IDD_VLPW Very-low-power wait mode current at 3.0 V — all

peripheral clocks disabled

— 0.80 — mA 8

IDD_STOP Stop mode current at 3.0 V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

0.528

1.6

5.2

2.25

IDD_VLPS Very-low-power stop mode current at 3.0 V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

498

1300

700

2400

3600

μA

IDD_LLS Low leakage stop mode current at 3.0 V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

5.1

124

300

μA

IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

3.1

14.5

63.5

7.5

195

μA

IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V

• @ –40 to 25°C —

—

2.0

6.9

μA

Table continues on the next page...

General

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 11

Freescale Semiconductor, Inc.

Table 6. Power consumption operating behaviors (continued)

Symbol Description Min. Typ. Max. Unit Notes

• @ 70°C

• @ 105°C

— 30 112 μA

IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

1.25

6.5

2.1

18.5

108

μA

IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

0.745

6.03

1.65

108

μA

IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

0.268

3.7

22.9

1.25

μA

IDD_VBAT Average current with RTC and 32kHz disabled

at 3.0 V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

0.19

0.49

2.2

0.22

0.64

3.2

μA

IDD_VBAT Average current when CPU is not accessing

RTC registers

• @ 1.8V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

• @ 3.0V

• @ –40 to 25°C

• @ 70°C

• @ 105°C

—

0.68

1.2

3.6

0.81

1.45

4.3

0.8

1.56

5.3

0.96

1.89

6.33

μA

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for

PEE mode. All peripheral clocks disabled.

3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE

mode. All peripheral clocks enabled.

4. Max values are measured with CPU executing DSP instructions.

General

12 Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI

mode.

6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled. Code executing from flash.

7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks enabled but peripherals are not in active operation. Code executing from flash.

8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral

clocks disabled.

9. Includes 32kHz oscillator current and RTC operation.

2.2.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in PEE mode at greater than 100 MHz frequencies

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Figure 3. Run mode supply current vs. core frequency

General

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 13

Freescale Semiconductor, Inc.

Figure 4. VLPR mode supply current vs. core frequency

2.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors

Symbol Description Frequency

band

(MHz)

Typ. Unit Notes

VRE1 Radiated emissions voltage, band 1 0.15–50 23 dBμV 1, 2

VRE2 Radiated emissions voltage, band 2 50–150 27 dBμV

VRE3 Radiated emissions voltage, band 3 150–500 28 dBμV

VRE4 Radiated emissions voltage, band 4 500–1000 14 dBμV

VRE_IEC IEC level 0.15–1000 K — 2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement

of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.

General

14 Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,

from among the measured orientations in each frequency range.

2. VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method

2.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

2.2.8 Capacitance attributes

Table 8. Capacitance attributes

Symbol Description Min. Max. Unit

CIN_A Input capacitance: analog pins — 7 pF

CIN_D Input capacitance: digital pins — 7 pF

2.3 Switching specifications

2.3.1 Device clock specifications

Table 9. Device clock specifications

Symbol Description Min. Max. Unit Notes

Normal run mode

fSYS System and core clock — 120 MHz

fSYS_USB System and core clock when Full Speed USB in

operation

20 — MHz

fBUS Bus clock — 60 MHz

FB_CLK FlexBus clock — 50 MHz

fFLASH Flash clock — 25 MHz

fLPTMR LPTMR clock — 25 MHz

VLPR mode1

fSYS System and core clock — 4 MHz

fBUS Bus clock — 4 MHz

Table continues on the next page...

General

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 15

Freescale Semiconductor, Inc.

Table 9. Device clock specifications (continued)

Symbol Description Min. Max. Unit Notes

FB_CLK FlexBus clock — 4 MHz

fFLASH Flash clock — 0.8 MHz

fERCLK External reference clock — 16 MHz

fLPTMR_pin LPTMR clock — 25 MHz

fLPTMR_ERCLK LPTMR external reference clock — 16 MHz

fFlexCAN_ERCLK FlexCAN external reference clock — 8 MHz

fI2S_MCLK I2S master clock — 12.5 MHz

fI2S_BCLK I2S bit clock — 4 MHz

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

2.3.2 General switching specifications

These general purpose specifications apply to all pins configured for:

• GPIO signaling

• Other peripheral module signaling not explicitly stated elsewhere

Table 10. General switching specifications

Symbol Description Min. Max. Unit Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5 — Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

100 — ns 3

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

16 — ns 3

External reset pulse width (digital glitch filter disabled) 100 — ns 3

Mode select (EZP_CS) hold time after reset

deassertion

2 — Bus clock

cycles

Port rise and fall time (high drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

—

Port rise and fall time (low drive strength)

• Slew disabled

General

16 Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

Freescale Semiconductor, Inc.

Table 10. General switching specifications

Symbol Description Min. Max. Unit Notes

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses

may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter

pulses can be recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,

and VLLSx modes.

4. 75 pF load

5. 15 pF load

2.4 Thermal specifications

2.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol Description Min. Max. Unit

TJDie junction temperature –40 125 °C

TAAmbient temperature –40 105 °C

2.4.2 Thermal attributes

Board type Symbol Description 80 LQFP Unit Notes

Single-layer

(1s)

RθJA Thermal

resistance,

junction to

ambient

(natural

convection)

50 59 °C/W 1

Four-layer

(2s2p)

RθJA Thermal

resistance,

junction to

ambient

35 41 °C/W 1

Table continues on the next page...

General

Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015. 17

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Board type Symbol Description 80 LQFP Unit Notes

(natural

convection)

Single-layer

(1s)

RθJMA Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

39 48 °C/W 1

Four-layer

(2s2p)

RθJMA Thermal

resistance,

junction to

ambient (200

ft./min. air

speed)

29 35 °C/W 1

— RθJB Thermal

resistance,

junction to

board

19 23 °C/W 2

— RθJC Thermal

resistance,

junction to case

8 11 °C/W 3

—ΨJT Thermal

characterizatio

n parameter,

junction to

package top

outside center

(natural

convection)

2 3 °C/W 4

Notes

1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal

Test Method Environmental Conditions—Natural Convection (Still Air), or EIA/

JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method

Environmental Conditions—Forced Convection (Moving Air).

2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal

Test Method Environmental Conditions—Junction-to-Board.

3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,

Microcircuits, with the cold plate temperature used for the case temperature. The

value includes the thermal resistance of the interface material between the top of

the package and the cold plate.

4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal

Test Method Environmental Conditions—Natural Convection (Still Air).

General

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3 Peripheral operating requirements and behaviors

3.1 Core modules

3.1.1 Debug trace timing specifications

Table 12. Debug trace operating behaviors

Symbol Description Min. Max. Unit

Tcyc Clock period Frequency dependent

(limited to 50 MHz)

MHz

Twl Low pulse width 2 — ns

Twh High pulse width 2 — ns

TrClock and data rise time — 3 ns

TfClock and data fall time — 3 ns

TsData setup 3 — ns

ThData hold 2 — ns

TRACECLK

Twh

Tcyc

Twl

Figure 5. TRACE_CLKOUT specifications

Ts Ts Th

TRACE_CLKOUT

TRACE_D[3:0]

Figure 6. Trace data specifications

Peripheral operating requirements and behaviors

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3.1.2 JTAG electricals

Table 13. JTAG limited voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 2.7 3.6 V

J1 TCLK frequency of operation

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

MHz

J2 TCLK cycle period 1/J1 — ns

J3 TCLK clock pulse width

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

—

J4 TCLK rise and fall times — 3 ns

J5 Boundary scan input data setup time to TCLK rise 20 — ns

J6 Boundary scan input data hold time after TCLK rise 2.6 — ns

J7 TCLK low to boundary scan output data valid — 25 ns

J8 TCLK low to boundary scan output high-Z — 25 ns

J9 TMS, TDI input data setup time to TCLK rise 8 — ns

J10 TMS, TDI input data hold time after TCLK rise 1 — ns

J11 TCLK low to TDO data valid — 17 ns

J12 TCLK low to TDO high-Z — 17 ns

J13 TRST assert time 100 — ns

J14 TRST setup time (negation) to TCLK high 8 — ns

Table 14. JTAG full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 1.71 3.6 V

J1 TCLK frequency of operation

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

MHz

J2 TCLK cycle period 1/J1 — ns

J3 TCLK clock pulse width

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

12.5

—

Table continues on the next page...

Peripheral operating requirements and behaviors

20 Kinetis K22F Sub-Family Data Sheet, Rev5, 03/2015.

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Table 14. JTAG full voltage range electricals (continued)

Symbol Description Min. Max. Unit

J4 TCLK rise and fall times — 3 ns

J5 Boundary scan input data setup time to TCLK rise 20 — ns

J6 Boundary scan input data hold time after TCLK rise 0 — ns

J7 TCLK low to boundary scan output data valid — 25 ns

J8 TCLK low to boundary scan output high-Z — 25 ns

J9 TMS, TDI input data setup time to TCLK rise 8 — ns

J10 TMS, TDI input data hold time after TCLK rise 1.4 — ns

J11 TCLK low to TDO data valid — 22.1 ns

J12 TCLK low to TDO high-Z — 22.1 ns

J13 TRST assert time 100 — ns

J14 TRST setup time (negation) to TCLK high 8 — ns

J3 J3

J4 J4

TCLK (input)

Figure 7. Test clock input timing

J5 J6

Input data valid

Output data valid

TCLK

Data inputs

Data outputs

Figure 8. Boundary scan (JTAG) timing

Peripheral operating requirements and behaviors

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