uPD71051 Serial Control Unit January 1989 NECThe uPD71051 serial control unit is designed for serial data communications in microcomputer systems. On a system level, the uPD71051 is regarded as an ordinary peripheral device. Synchronous and asynchronous serial communications are possible using CPU programs. In the synchronous mode, operations in IBM's BSC system are also possible. The uPD71051 was fabricated using CMOS technology and consumes low power. Its power consumption is even lower in the stand-by mode. In the stand-by mode, the operation mode in which uPD71051 has been set is released and the serial control unit waits for a mode word for mode setting, which is to be sent from the CPU. When the CPU has written the mode word to the wuPD71051, the serial control unit is released from the stand-by mode, and enters in the specified operation mode. Features: o Synchronous/asynchronous operation modes * Synchronous mode i + 2 SYNC characters Internal/external synchronization Automatic SYNC character insertion Asynchronous mode Clock rate: Baud rate x 1, 16, 64 Send stop bits: 1, 1.5, 2 bits Break transmission Automatic break detection Error start bit detection o Directory connected to uPD70108-10 and uPp70116-10 with no wait state (uPD71051-10) o Baud rate uPp71051 : DC to 240K-bit/sec uPD71051-10: DC to 300K-bit/sec Full duplex, double buffered transmitter/receivero Parity generate/check Error detection: Parity, overrun, framing o 5 - 8 bit characters o Stand-by mode o CMOS technology o Single power supply Ordering Information Ordering Code Package Type Max. Frequency of Operation uPD71051 28-pin uPD71051C-10 28-pin uPD71051GB-384 44-pin uPP71051GB-10-3B4 44=<pin uPD71051GU0 28=-pin uPD71051G0-10 - 28-pin uPD710511L 28-pin uPD71051L-10 ' 28-pin plastic DIP plastic DIP plastic QOFP(2.70mm thick) plastic QFP(2.70mm thick) Plastic SOP plastic SOP PLCC PLCC -~ ii - 8MHz 10MHz 8MHz LOMEz 8MHz 10MHz 8MEz 10MHzPin Configuration (Top View) D2 i 28 bi D3 2 2? ht) RuDATA 3 26 Vim GKD 4 3 fatT eh ba 5 EE 24 DTK Ds 6 $s uTS D 7 @85 DSK nN? 8 oS a RESET TxCLk cL WR TaDATA tS TEMP cn crs iD SYNC/BRK RsRDY TzRDY 4 z = ; . Zee ze yiBGiveecee 1 40 39 % Ne M4 8 a4 40 39 38 37 Bu, Ke nc {2 32h NC TaDATA ==] 3 : 31h WR CLK -~)4 2 3ope TCLK RESET --1 5 a ppe 197 NC 16 & zap NC TSR onl 7 5 rib 16 RTS boa a 2 3 16 Dik \9 = p= IN nc =) ue NC Cil Bbeme NC x [22.13.14 15 36 17 38 19 20 21 22 Ne uo - *E i eers i 2 g = < & & a Zz2eee82 LEEP ELS 43 221 2 2 8 Da ewe oO 3 peeo CTR DS ow 6 24;eo BTR D6 oot 7 2peo RTS S1y7 10521. D? oomel 8 POTS 22beo TSR : o 9 2140 RESET WR oer 10 202 CLK roo 19 Joo T.DATA 120130 16) 98) 16178 4 4 i | biadadd meee se EF E oF ze2eK & = $ = nmuPD71051 Block Diagram data buffer RESET CLK car aq Status register ve Transmit ata buffer Internal 68-bit bus Status bus Transmitter TsDATA Tsithy TaEMP TRCLK RalATA Rakhy SYNC/BRK WaCrk eTs kTS DSH vYK CSBLOCK FUNCTION eeu teee ese eee see easeeeree tees ee eee e teste eawvene CONTENTS PIN FUNCTIONS eepeu see eae teep eae ecaeeaeee tees eaeee treet eeaeeateae CONNECTION WITH SYSTEM eaeseepeecese eee eane ence eee aeteenen DESCRIPTION OF THE uPD71051 OPERATIONS ..cceesccacees 4.1 Operating Procedure *eecesep eee peep esceseeecaepeeeteeeeuegeaesne 4.2 Mode Designation eaeptoeoetepePeeee eee seeaeseeaeeeeeeegeeveee 4.3 Commands and Operations ..ccseccraccrseeeeuceeen 4.4 Status eeeeeeeeceea ep eeee espe eee eee evteeeevn eo eee ece eB eeveoes STAND-BY MODE erate eueeseeeteecstoenvatovsuv,tescnsetpnvneaeveteonsnsnoepeee ELECTRICAL SPECIFICATIONS ..ssccseccassnccsccesescens PACKAGE INFORMATION 1-i 2-2 3-i 4-1 4-3 4-7 4-23 5-1 CG1. BLOCK FUNCTION 1.1 Control Logic The control logic sends control signals to the internal blocks and controls the operation of the uPD71051 in accordance with signals from the outside of the uPD71051 and internal status signals. 1.2 Status Register This is an 86-bit register that stores the uPD71051 states. The status register contains an error, data buffer, and general-purpose input pin states. The CPU can read the contents of this register anytime. 1.3 Receive Data Buffer The receive data buffer stores data which the receiver has received. The CPU receives receive data by reading the contents of this buffer. 1.4 Send Data Buffer The send data buffer stores send data which the CPU has written. The written send data is transferred from this send data buffer to the send buffer inside the transmitter and is output from Pin TXxDATA. 1.5 Control Word Register A control word (a mode word, SYNC character after a mode word, and command word) to designate the operation is shifted inside the uPD71051 via this register. 1-11.6 Synchronous Character Register This register stores one or two SYNC characters to be written in the control word register after the mode word in the SYNC mode. During transmitting the SYNC characters stored in this register are output from Pin TxDATA when data writing by the cpu is delayed and a TxEMP status is established. During receiving when the characters received and SYNC characters stored in this register coincide after a comparison is made, synchronization will be established. . 1.7. Transmitter The contents of the send data buffer are transferred to this transmitter and are output from Pin TXDATA after being parallel serial converted. The transmitter adds start, stop, and parity bits. , 1.8 Receiver The receiver converts serial data input from Pin RxDATA into parallel data and transfers parallel data to the receive data puffer to permit the CPU to read it. Detection of SYNC characters and checking of parity bits in the SYNC mode, as well as detection of start and stop bits and checking of parity bits in the asynchronous mode, are performec inside this receiver. In the asynchronous mode, receiving operation is not started unless one effective "1" (high level) is input to Pin RXDATA when the RECEIVE ENABLE (RxEN#1) status is first established after setting up the mode (start bit is not detected). 1.9 _ MODEM Control This block controls MODEM interface. Pins crs, RTS, DSR, and DIR are controlled by this block. But three pins other than CTS can be used as general-purpose input/output pins. 1-22. PIN FUNCTIONS 2.1 D7 - DO (Data Bus) ... 3 State Input/Output This is an 8-bit, 3=-state bi-directional data bus. The bus transfers data by connecting to the system data bus. It becomes active when CS = 0, and RD or WR is 0. Otherwise, it is ina high impedance state. 2.2 RESET (Reset) ... Input Inputting a high level to this pin resets uPD71051 and sets it to an idle state. The uPD71051 operates nothing in this mode. It is set to the stand~by mode when the signal falls from a high to a low level. The stand-by mode is released when the CPU writes a mode word in the uPD71051. At least 6 tcy is needed as the reset pulse width. {A clock must be input.) 2.3 CLK (Clock) ... Input This pin is a clock input pin to produce timing inside the uPp71051. To assure stable operations, the clock frequency should be more than 30 times the transmitter or receiver clock input (TxCLK, RXCLK) frequency in the synchronous mode or in the asynchronous mode with X1 ciock. The clock frequency should be more than 4.5 times in another asynchronous mode. 2.4 CS (Chip Select) ... Input CS is a signal to select the uPD71051. The uPD71051 is selected by establishing CS = 0. Selection is not possible when CS = 1, and the data bus (D7 - DO) becomes high impedance. The RD and WR signals are neglected. 2-1 C32.5 RD (Read Strobe) ... Input = 0 is established when reading data or status information from the uPD71051. 2.6 WR (Write Strobe) ... Input. WR = 0 is established when writing data or a control word in the uPp71051. 2.7 C/D (Control or Data) ... Input fhis signal regulates data type when accessing the uPD71051. c/B = 1: Control word/status c/D = 0: Character data This pin is normally connected to the least significant bit AO of the system address bus.Table 2-1 Control Signals and Operations _ a -_ . CPU cs RD WR c/D uPD71051 operation operation Receive data buffer Read 0 0 1 0 , receive Data bus data Status register 0 6 1 1. ; Read status Data bus Data bus Write 0 1 0 0 { transmit Transmit data buffer data Data bus Write 0 i 0 1 transmit Control word register data Data bus: 0 1 i * High impedance Data bus: 1 * * * High impedance 2.8 DSR (Data Set Ready) ... Input This is a general-purpose input pin. The status of this pin can be known by reading the status (bit 7). 2.9 DTR (Data Terminal Ready) ... Output This is a general-purpose output pin. The status of this pin can be controlled by Bit 1 of the command word. bit 1 = 1+ DTR = 0 bit 1 = 07 DTR=12.10 RTS {Request to Send) ... Output This is a general-purpose output pin. The status of this pin can be controlled by Bit 5 of the command word. bit 5 #1 RTS = 0 bit 5 = 0 RTS = 1 2.11 CTS (Clear to Send) ... Input This is an input pin to control transmission. uPD71051 will be able to send when setting up CTS = 0 while TxEN = 1 is established by the command word. When setting CTS = 1 during transmission, the sending operation is disabled after sending all the data currently written, and the level of Pin TxDATA becomes high. 2.12 TXxDATA (Transmit Data) ... Output This pin sends serial data. 2.13 TxRDY (Transmitter Ready) eee Output This signal notifies the CPU that the send data buffer in the uPD71051 is empty, that is, send data can be written. This pin signal is masked by the command word (TxEN bit) or CTS input. It can also be used as an interrupt signal of a data write request to the CPU. TxRDY can also be read by the status (Bit 0}, and polling is also possible. Note that TxRDY of the status is not masked. TxRDY is automatically cleared to 0 by the falling edge of WR during writing of send data in the uPD71051 by the CPU when the CPU writes in the uPD71051. Data in the send data buffer not yet sent is destroyed when send data is written in a TxXRDY = 0 status. .2.14 TxEMP (Transmitter Empty} ... Output . The uPpD71051 reduces the CPU overhead during the sending operation through a double buffer system using the send data buffer (second buffer) and send buffer (first buffer} in the transmitter. When the CPU writes send data in the send data buffer, which is the second buffer, the uPD71051 continues sending data by automatically transferring the contents of the second buffer to the first buffer after sending the contents of the first buffer in the transmitter. Thus, the second buffer becomes empty, and TxRDY is set to 1. TxEMP becomes 1 after the contents of the first buffer is sent while the second buffer is empty, showing that TxEMP = 1 indicates that both the first and second buffers are empty. In half-duplex communications, the timing to change from a sending operation to receiving operation can be known by TxXEMP = 1. When TxEMP = 1 is established in the asynchronous mode, the level of Pin TxDATA becomes high. When the CPU writes send data thereafter, TxEMP is automatically set to 0, and data sending is resumed. , When TXEMP = 1 is set in the synchronous mode, the uPD710S5i automatically loads SYNC characters from the SYNC character register and continues to send them through Pin TxDATA. TxEMP is set to 0 and resumes sending data after sending SYNC characters (one or two) sent when the CPU writes send data in this rate. 2.15 TxCLK (Transmitter Clock) ... Input Reference clock input to decide a transmission rate. Transmission is performed at the same rate as that of TxCLK in the SYNC mode. In the asynchronous mode, the TXCLK frequency can be at three levels, 1, 16 an 64 times of the transmission rate. Serial data from Pin TxDATA is performed by the falling edge of TxCLK. 2-5 13Examples) 19,000 baud in synchronous mode ... TXCLK: 19.2 kHz 2,400 baud in asynchronous mode x 1 elock ....e22+ TXCLK: 2.4 kHz x 16 clock ...... TxCLK: 38.4 kHz x 64 clock ...... TXCLK: 153.6 kHz 2.16 RxXDATA (Receive Data) ... Input Serial data is received through this pin. 2.17 RxXRDY (Receiver Ready) ... Output This signal becomes 1 when the uPD71051 receives data for one character and when that data is transferred to the receive Gata buffer, that is, when the receive data can be read. This signal can be used as an interrupt signal for a data read request to the CPU. The status of RxRDY can also be known by reading the status (Bit 1), and polling operation is also possible. RxRDY becomes 0 when the CPU reads receive data. An overrun error occurs, and the bit OVE of the status is set unless the CPU completes reading receive data after RxRDY = 1 is set, and before the next one character is received and transferred to the receive data buffer. The data in the receive data buffer not read is substituted by newly transferred data at that time. . RxRDY is fixed to a 0 state by establishing a receive disable state by changing the RxEN bit to 0 through the command word, RxXRDY becomes 1 after new characters are received and transferred to the receive data buffer when RxEN = 1 is set and receiving is possible. 142.18 SYNC/BRK (Synchronization/Break) ... Input/Output SYNC ... Input/Output SYNC is used to detect synchronization in the SYNC mode. Selection between internal and external detection as a sYNC detection method is selected by the mode word of the SYNC mode. The SYNC pin becomes output when detecting internal synchronization and becomes input when detecting external synchronization. The level becomes high when the uPD71051 detects a SYNC character in internal synchronization. When set to the double SYNC character, the level becomes high by the position of the last bit when bits for two characters are detected continuously. fhe SYNC signal can be known by reading the status (Bit 6), and both pin and status are cleared to 0 by the reading operation. In external synchronization, a high level of more than one period of RxCLK is input to Pin SYNC when the external circuit | detects synchronization. Upon detecting this high level, the uPD71051 starts receiving data beginning at the rising edge of the next RxCLK. The high level input may be removed after synchronization is released. * BRK ... Output BRK is a signal used only in the asynchronous mode and shows detection of a break state. The level of BRK becomes high when a low level signal is input to Pin RXDATA in more than two data blocks in a predetermined character bit length (including the start bit, parity bit, and a stop bit). As in the SYNC signal, the BRK signal can be checked by the status (Bit 6), but is not cleared by the read operation. The set BRK signal is cleared when the level of the RxDATA input returns to high, or when it is reset (hardware or software}. Fig. 3-1 shows the break state and BRK signal. 15The level of the SYNC/BRK pin becomes low regardless of the mode when it is reset. Fig. 2-1 Break Status and BRK Signal 8<bit character, no parity 3 -~_ -~ 43 a3 2 a 2 za 7 Character bits ee Character bits at = . i" ee! ei RuDATA a bo | ' \ \ , D7 aad no 1 ' . . \ art . jwe First data block =}- Second data block #1] =e BRK TL 6-bit character with parity -_ -_ -_~ 2 om ~ as 75 3s s 3 3 +e character bits 3S . Character bits 2 ~~ Vol ~ Bb (REI OOO a : fy 8 wide pb & 1 & - = ReDATA ] a Raed L 1 1 i 1 1 1 1 Xe Z Ds pe First data block e-+=-Second data block *i--| BRK 2 *1: When RxDATA bit goes high level in a stop bit of a second data block, the BRK signal may temporarily (one bit long at the most) become high or may not become high. *2; Only one bit of the stop bit is checked.2.19 RxCLK (Receiver Clock} ... Input This is a reference clock input decide the receiving rate. The receiving rate in the SYNC mode will be the same as that of RxcLK.- In the asynchronous mode, RxCLK can be 1, 16 or 64 multiplication relative to the receiving rate. . Serial data from RxDATA is input by the rising edge of RxCLkK,. 2.20 V, (Power) DD Positive power supply. 2.21 GND (Ground) Ground petential. 2.22 IC (Internally Connected) This pin must be left unconnected.3. Connection with System The CPU can handle the uPD71051 as a normal I/O device and uses it by allocating to two I/O addresses depending on the value of Pin C/D. One is when the level of the C/D input is high and becomes a port to transfer send and receive data. The other is when the level of the C/D input is low and becomes a port to write control words and to read the status. Generally, the least significant bit AQ of the address bus is connected to Pin C/D to obtain a continuous I/0 address. Even though it is not shown in Fig. 4-1, Pins TxRDY and RxRDY are connected to the CPU or the interrupt pin of the interrupt controller when interrupt is utilized. Fig. 3-1 System Configuration Address bus cru _" De- al 71051 MEM/IO oder " It Do cb ty RD ay Th WH 3-1 7 ~ 184. Description of the uPD71051 Operations This chapter describes the basic operating procedure, detailed control method, operating modes, etc. to operate the uPD71051. 4.1 Operating Procedure Start with hard resetting (set the level of Pin RESET to high) at all times as the status of the uPD71051 after switching ON the power. By doing this, the uPD71051 is set to the stand-by mode and queves for a mode word. By writing a mode word and setting a communication protocol mode in this state, the command word queue status is set when in the asynchronous mode. A queue state for writing one or two (determined by the mode word) SYNC characters is set in the SYNC mode. Note that c/BD = 1 should be set up in this case. After the SYNC characters are written, a command word queue status is established. In both modes, writing of send data, reading of receive data, reading of status, and writing of command words will be possible after writing the command words. The uPD71051 performs a reset operation, shifts to the stand-by mode, then returns to the mode word queve mode when software resetting is performed by the command word. 4-1 193Pig. 4-1 Hardware reset Write mode word Write sync Write sync character 1 character 1 Write syne character 2 a uPD71051 Operating Procedure Write command word a! Status: Data: Command: Read status Write/read data Write command word t This is done with C/D = 0. Others are operated with C/D = 1,4.2 Mode Designation Mode words have to be written in the uPD71051, which is in the stand-by mode, by resetting (hardware or software) when designating a mode for the uPD71051. By doing this, the stand-by mode is released, and a mode is designated for the uPD71051. The mode word format is shown in Figs. 4-2 and 4-3. The SYNC mode is set when both Bits 1 and 0 are 0. In other cases, the asynchronous mode is set up.Bl | BO Baud rate Oo |1 | x1 clock 1 |o | x16 clock 1 | 2 | x64 clock L1 | 10 Character length 0 |0 | 5=bit oO |2 |} 6-bit 1 |O | 7=bit 1 [1 | 8-bit P1|PO| Parity generate/check x {0 |No parity 0 {12 | oda parity 1 |1 | Even parity ST1 | STO | Transmit stop bits 0 | Use inhibited 9 2 | i=bit 1 | 0 [21/2 bit 1 | 1 | 2-bit x: don't care tt? toFig. 4-3 Mode Word for Setting Synchronous Mode c/pD =1 LO Character length 5<bit 6-bit Feobit B-bit Parity generate/check No parity Odd parity Even parity Sync detect Internally Externally ssc Sync characters 2 (BSC) 0 1 j1 x: don't care 4-5 oe) o3First, the bits that are common in both modes are described. Bits Pl and PO (parity) control parity bit generation {sending) and check (receiving) functions. The parity bit generation and check functions do not operate when PO = 0. Generation and checking of odd parity are performed when both Pl and PO are 01, and of even parity when both Pl and PO are 11. Bits Ll and LO (length) set the number of bits for one character. Additional bits such as a parity bit are not included in this number of bits. When set to n bits, the uPD71051 receives lower n bits of 8<-bit data written by the CPU. Upper & minus n bits of data which the CPU reads from the uPD71051 become 0. Special bits for the asynchronous mode are described next. Bits ST1 and STO {stop bits) designate the length of the stop bits (high level) which the uPp7051 adds during transmission. Bits Bl and BO (baud rate) reguiate the relationship between the baud rate for sending and receiving, and TxCLK and RxCLK. A selection is made of a multiplication rate of 1, 16 or 64 for the frequency of the sending and receiving clock relative to the baud rate. Normally, the multiplication of 1 is not used in the asynchronous mode. Note that data and clock have to he synchronized on the sending and receiving sides when using multiplication 1. Lastly, bits that are special to the SYNC mode are described. Bit SSC (single SYNC character) decides the number of SYNC characters. The number of characters is 1 if it is S&C = 1, two (BSC) if SSC = 0. After the mode word, SYNC characters in the number set by the SSC bit are written. Bit EXSYNC (external synchronization} decides whether SYNC detection during receiving should be internal or external detection. EXSYNC = 1 is for external detection, and EXCYNC = 0, for internal detection. tr ney4.3 Commands and Operations Commands are given by command words and control sending and receiving operations of the uPD71051. A command word is obtained by designating the mode by a mode word (after additionally writing SYNC characters in the SYNC mode) and writing C/D = 1. Fig. 4-4 Command Word Format Transmit enable Disabie Enable DTR pin control =i =0 Receive enable Disable Enable Send break TxDATA pin normal operation TxXDATA = 0 ECL Error clear 0 | No operation 1 |8rror flag clearThe EH bit is effective only in the the async mode. RTS RTS pin control 0 RTS = 1 1 RTS = 0 SRES Software reset 0 No operation 1 Reset operation EH* Enter hunt phase 0 | No operation 1 |Enter hunt phase syne mode. It will be not cared inBit EH (enter hunt phase) is set to 1 when entering the hunt phase to synchronize in the SYNC mode. Bit RxEN for receiver enable should also be set to 1 at that time. Data receiving starts automatically after escaping from the hunt phase when SYNC characters are detected and synchronization is released. Soft resetting is executed and SDA shifts to a stand-by mode, and is set to a mode word queve status, when Bit SRES (software reset) is set to 1. Bit RTS (request to send) controls the general-purpose output pin RTS. The level of RTS is low if RTS = 1, and becomes high if RTS = 0. When Bit ECL (error clear) is set to 1, error flags (PE, OVE and EE) in the status are cleared. Establish ECL = 1 at the same time when entering the hunt phase (EH = 1) or receiver enable (RxEN = 1) to clear the error flags as well. Bit SBRK (send break) sends a break. When SBRK = 1 is established, the data being currently sent is destroyed, and the level of Pin TXDATA becomes low. Set SBRK = 0 to release the break status. This function works in a send disable status as well. Bit RXEN (receiver enable) instructs receiver enable/disable. Receiver enable is established when RxEN 1. Receiver disable is established when RxEN = 0. Synchronization is lost when receiver disable is set during the SYNC mode. Bit DTR (data terminal ready) controls general-purpose output Pin DIR. The level of DTR becomes low when DTR = 1, and becomes high when DTR = 0. Bit TxEN (transmitter enable) instructs sending enable/disable. The transmitter is enabled when TxEN = l. When the transmitter is disabled by setting up TxEN = 0, sending is stopped and the level of Pin TxDATA becomes high (mark status) after all the data currently written is sent (when SBRK 1). 4-9 tr sl4.3.1 Asynchronous Mode Operation (1) Sending The level of Pin TxDATA is normally in a high state (marking) when data is not sent. When the CPU writes send data in the uPD71051, the uPD71051 transfers the send data from the send data buffer to the send buffer and sends the data from Pin TxDATA after automatically adding one start bit (low level) and programmed stop bit. When the parity is effective, a programmed even or odd parity bit is added between the character and stop bit. Serial data is sent by the falling edge of the signal which divided (1/1, 1/16, and 1/64 division) TxCLK. Fig. 4-5 Asynchronous. Mode Data Format No parity 0 Bi Vel ler Start = by Ape oe marx L_bit_| Data pits | stop l bitts) * With parity mark | bit | _ __ Data bits ; | arity | woe u : bit(s) nz: 4, 5, 6, 7 Stop bit: 1 bit, 1.5 bit, 2 bit Upon issuing a command that sets Bit SBRK at 1, the level of Pin TxDATA becomes low (break status), regardless of whether or not data is being sent. Fig. 4-6 shows an example of a program to send data in the asynchronous mode and output of Pin TxDATA. 4-16 t oASYNTX : TXSTART: TXDADR ASYNMOD: Fig. MOV OUT . MOV IN TEST1 BZ MOV ouT INC BNE DB DB MOV OUT ouT out MOV out MOV OUT ASYNMOD AL, 000100013 PCTRL, AL BW, OFFSET TXDADR . AL, PCTRL AL, 0 TXSTART CBW] PDATA, AL BW AL, 0 TXSTART 'NEC' 6 AL, 90 PCTRL, AL PCTRL, AL PCTRL, AL AL, 010000008 PCTRL, AL AL, 111110105 PCTRL, AL | ) ) | 4-6 Asynchronous Mode Transmit Example Set async mode Command Error flag clear Transmit enable Transmit data area Read status Wait until TxRDY = 1 Write transmit data Set next data address End if data = 0 fransmit data 4EH, 45H, 43H, OOH Write control words 3 times with 00H to accept the new command word unconditionally Software reset rite mode word Stop bit = 2-bit Even parity 7-bit/character x16 clockTxDATA Pin Output TDATA Mazk| ll ru Ul Af U | | | l _ Mark FY] ~ a vr) vf fe w per A Sn e 4EH ree oH of &h gH Fes OH SF & ed N bw Ee wae a Cc www ww w g"u a2 u 24a 2 (2) Receiving Fig. 4-7 Start Bit Detection RsDAT: $ @ habaTa Y Sampiing @ RePATa \ } i 4 4 ' Sampling Bit boundary 1 1 1 In the case of @, start bit is not recognized at the RxDATA is high at the sampling time. In the case of @, start bit is recognized as the RxDATA is low at the sampling time. The level of Pin RxDATA is normally maintained high when data is not received. The uPD71051 detects the falling edge of a low level signal when a low level signal enters it. The uPp71051 samples the level of RXxDATA input (only when x 16 and x 64 clocks are designated) in a position 1/2 bit behind the falling edge to check whether or not this low level is an effective start bit. The start bit is regarded effective when a low level is detected at that time. The bit is not regarded as a start bit when a high level is detected, and is returned to a low level input queue status again. When a start bit is detected, sampling points of the data bit, parity bit {when effective), and stop bit are G@Gecided by a bit counter, and data reading is started. The 30sampling is performed by this rising edge of the signal that divided (1/1, 1/16, and 1/64 division) RxCLK. Data for one character entering the receive buffer is transferred to the receive data buffer and becomes RxRDY = i, requesting the CPU to read the data. When the CPU reads the data the RxRDY automatically becomes 0. Only one stop bit is detected. When a high level (the correct stop bit) is detected, a queue status for the start bit of the next data is established. A framing error flag is set when a low level is detected in the stop bit. However, the receiving operation continues as if a high level has been detected as a stop bit. A parity error flag is set when a parity error is occurred. An overrun error flag is set when the CPU is slow in reading, and the next receiving data is transferred to the receive data buffer. The sending and receiving operation of the uPD71051 is not affected regardless of which error is caused. When a low level is input on Pin RxDATA for more than two data blocks in -time duration in a receiving operation, the situation is judged as a break state, and SYNC/BRK (pin, status) becomes 1. Start bit detection is not performed until a high level of more than one bit is input to Pin RxDATA when the asynchronous mode is set and receiving is enabled first after resetting. Fig. 4-8 shows an example of a program to receive the data sent in Fig. 4-6. 4-13Fig. 4-8 Asynchronous Mode Receive Program Example ASYNRX : CALL ASYNMOD Set async mode | MOV AL, 000101008 Command Error flag clear ouT PCTRL, AL Receive MOV BW, OFFSET RXDADR Data store area RXSTART: IN AL, PCTRL | Read status TEST1 AL, 1 Wait until RxRDY = 1 BZ RXSTART IN AL, PDATA Read and store the mov [Bw], AL receive data Inc) 8 oBW Set next store address CMP AL, 0 BNE RXSTART End if data = 0 RET | . RXDADR DB 256 DUP (?) Reserve receive data area Note: The frequencies of the TxCLK on the transmitter and the RxCLK on the receiver are the same. 4.3.2 Synchronous Mode Operation (1) Sending Pin TxDATA continues to be in a high level status until the CPU writes the first data (normally, SYNC characters) after the transmitter is enabled following its setting in the SYNC mode. When data is written, Pin TxDATA sends one bit for each rising edge of TxCLK when the level of CTS is low. Unlike the asynchronous mode, neither a start bit nor a stop bit is added. A parity bit can be set. 4-14 C3 toFig. 4-$ Synchronous Mode Data Format Character data without parity {po | pm | ff Pod | in Character data with parity [ np 7T m [| [ de-t | Dn | Parity | ns 4, 5, 6, 7 Once sending is started, the CPU must write data in the uPD71051 at the same rate as that of TxXCLK. If TxEMP = 1 is established after data writing by the CPU is delayed, the uPD71051 continues to automatically send one or two SYNC characters until the CPU writes data. TxEMP = 0 is established when data is written, and written data is sent as soon as sending of the SYNC characters finishes. Automatic sending of the SYNC characters becomes effective after the CPU rewrites data, and the SYNC characters are not sent automatically merely by enabling the transmitter. uPD71051 does not operate as specified when a command word is written while the uPD71051 is automatically sending SYNC characters. For this reason, when a command word has to be written during automatic sending (TxEMP = 1) of SYNC characters, the same data as that of the SYNC characters is written, and the command word is written while sending that data (See Pig. 4-11). Fig. 412 shows a program example for sending in the SYNC mode. 4-15| Lf O = NAXL puewmoy 9 30q S 83eq r 3280 e3ea z vaeg T 8220 oO 8209 UU 9 B3eq [zu SuASHt Tuo Sudg) 839g | Zuo oudg | TuHd Suds] > e3ea e3e8q t &eq 1 e300 I 0 e3q 42eH ALL eOFQewoyNE YpwsUeTy TSOTLGGn O12 (9Sa@) Z = 1a}9e1Ny9 Judg jo "On Buys, yyusuerzy apow ouds oO1-7~ Sta yA ADL (Rd) MOL VLVOEL 4-16Pig. 4-11 Command Issue during Transmitting Sync Characters No. of sync characters = 1 2 99g e By the uPD71051 By the uPD71051 By the CPU TsDATA | Data fSyne character|Sync character|Syne character TerDy | ee vee OE <CN @ We U LJ @ @ mo u Lu Confirm the auto-transmit of the syne character (TxEMP = 1} by status. Write syne character data Confirm the transmission start of the sync character written by the CPU by reading the status. Write command word 4-17Fig. 4-12 Synchronous Mode Transmit Program Example SYNTX TXDATA: SYNC1 SYNC2 LDLEN TXDADR BW, OFFSET TXDADR CALL SYNMOD MOV AL, 000100018 our PCTRL, AL MOV IN AL, PCTRL TEST1 AL,O BZ TXLEN MOV AL, LDLEN OUT PDATA, AL MOV CL, AL MOV CH, 0 IN| AL, PCTRL TEST1 AL, 0 *BZ TXSTART MOV AL, CBW) OUT PDATA, AL Inc BW DBNZ TXDATA MOV AL, 00010000B OUT PCTRL, AL RET DB? DB? DB? DB 255 DUP {?) } Command Set sync mode Error flag clear * Transmit enable Transmit data area Transmit No. of transmit data counter yest No. of transmit data to ~ Transmit data as much No. of , set in the counter Command Error flag clear * Transmit disable Syne character 1 Syne character 2 Set No. of data to be transmitted (1 to 255) Data to be transmitted C3 o>}SYNMOD: MOV AL,9 OUT PCTRL, AL Write control words 3 times with OOH to accept the new out PCTRL, AL command word unconditionally ouT PCTRL, AL MOV AL, 010000008 Software reset out PCTRL, AL Write mode word. Syne characters = 2 Internal sync detect Even parity B-bit/character MOV AL, 00111100B out PCTRL, AL MOV AL, SYNCi ouT PCTRL, AL Write syne character MOV AL, SYNC2 out PCTRL, AL (2) Receiving The first requirement for receiving in the SYNC mode is to synchronize with the sending side. For this reason, the first command after setting the SYNC mode and writing the SYNC character (C/B = 1) has to be EH = 1, ECL = 1, and RxEN = 1. When entering the hunt phase with this command, all the bits in the receive buffer are set to 1. In internal synchronization, data on Pin RxDATA is input to the receive buffer for each rising edge of RxcLK and is compared with the SYNC character at the same time. 4-19 a] G3Fig. 4-13 Internal Syne Detect Operation Example 5-bit character, No parity, 2 syne character Syne character 1 = 011008, Sync character 2 = 110015 *1 to *4: Byne character 1 Syne character 2 LSB . MSB LSE MSB Lo; 0:1: 3: 0 Bega Ss All bits are set *1 o2. a1 2 to 1 by EH = 1 CPU operation SYNC Receive buffer RxDATA input Command | EH=1 0 ; : r 1 eee 9 1} Mark 6 1 0 6 0 6 1} Sync character 1 6 i 0 6 i 8 0 6 0} Sync character 2 6 1 Read status 1 i 0 0 | Data : a3 a4 : 3 oe : Cleared by status read x i don't care As character is 5-bit, the part *1 of sync character register (lower 5-bit) is valid and the part *2 is doen't care. As to receive buffer, because of character is 5-bit and no parity, the part *3 is valid and the part *4 is not used. When the part *1 and the part %3 are matched, SYNC becomes 1. (With parity, the L.S.B of the part *4 is used for parity bit, but it is not used to compare with the syne character.) 4-20When the receive buffer and SYNC character coincide, the uPD71051 finishes the hunt phase and becomes SYNC = 1, becomes 1 in the center of the last bit of the SYNC character. When a parity exists, SYNC becomes 1 in the center of the parity bit. When synchronized, receiving starts beginning with the bit as data. In external SYNC detection, synchronization is achieved by giving a high level for more than one period of RxCLK to Pin SYNC by an external circuit, and the hunt phase is finished to start data receiving. At this time, the status SYNC bit becomes 1, and then becomes 0 when the status is read. The status SYNC bit is set to 1 when the SYNC input has a rising edge followed by a high level of more than one period of RxCLK even after synchronization is achieved. The uPD71051 can be made to regain synchronization anytime by giving an enter hunt phase command when it loses synchronization. After synchronization, a SYNC character is compared with each character regardless of whether it is internal or external detection. When coincided in comparison, SYNC (status only in external detection) becomes 1, indicating that a SYNC character has been received. in this case also, SYNC (status only in external detection) becomes 0 when the status is read. Overrun and parity errors are checked in the same method as that of the asynchronous mode, affecting the status flag only. Parity checking is not performed in the hunt phase. Fig. 4-14 illustrates a program example to show receiving of data sent in Fig. 4-12.Fig. 4-14 Synchronous Mode Receive Program Example SYNRX : CALL SYNMOD Set sync. mode Command MOV AL, 100101005 | Enter hunt phase Frror flag clear OUT PCTRL, AL Receive enable Mov BW, OFFSET RXDADR Set receive data store ~ address RXLEN : IN AL, PCTRL TEST1 AL, 1 , Receive the No. of receive data BZ RXLEN . IN AL, PDATA MOV STLEN, AL Set the No. of receive data Mov CL, AL + to both variable and counter MOV CH, 0 | . RXDATA: IN AL, PCTRL 7 TESTI AL, 1 BZ RXDATA Receive and store data as IN AL, PDATA > much No. of the counter MOV BW , AL Inc BW DBNZ RXDATA MOV AL, 000000008 } Command ouT PCTRL, AL Receive disable RET STLEN DB ? Set No. of receive data RXDADR DB 256DUP (0) Reserve receive data area Note: The frequencies of the TxCLK on the transmitter and the RxCLK on the receiver are the same. 404,4 Status The CPU can read the status of the uPD71051 during an operation of the uPD71051 (except in the stand-by mode). By doing this, the CPU can know data writing and reading timing, occurrence of errors during receiving, etc. The status is read after establishing c/D = 1. Status updating is disabled during reading of the status. Note that status updating is delayed a maximum 28 clock periods after an event affecting the status has taken place. tn tFig. 4-15 Status format C/D = 1 7 6 3 1 0 SYNC DSR /BRK PE RxRDY | TXRDY i Same as the output pin function with the same name. Transmit data TxRDY buffer state 0 Full 1 Empty - PE Parity error 0 No error 1 | Error OVE Overrun error 0 -|No error 1 Error FE Framing error 0 | No error 1 Error DSR DSR input pin state 0 DSR = 1 1 DSR = 0 4-24 ey toThe individual bits are described in the following. Bits TxEMP and RxRDY have the same meanings as those of the output pins of the same names. Bit SYNC/BRK has the same meaning as that of Pin SYNC/BRK in almost all instances. Its status does not coincide with the pin only in external synchronization of the SYNC mode. In this case, Pin SYNC becomes input, and the status becomes 1 when a rising edge is detected in this input. The status does not become 0 until it is read even when the level cf input changes to the low level. The status becomes 1 when a SYNC character is input with RXDATA input even when the input is in a low level state. Bit DSR (data set ready} shows the status of the general-purpose input Pin DSR. DSR = 1 is established when the level of DSR is low. Bit FE (framing error) becomes 1 when more than one effective stop bit is not detected at the end of each data block @uring receiving operation in the asynchronous mode, indicating that a framing error has occurred. 4-25 te 3Fig. 4-16 Framing Error 2 character = 5-bit, No parity, stop bits = l-bit (i) In the case of break state RaDATA Lp | LP fo" the break state \ scart pit NL start pit Vireo > Stop bit in Stop hit R normal operation) (ii) In the case of frequency difference between RxCLK and TXCLK is big. FE#)} RuDATA This is a pulse to sample stop bit. But because cf the i | Vy frequency of the FxtTK is Sampling pulse lower than that of TxtlK, -Start bit is sampled erroneously. (iii) When data is changed during transmit (Using less reliable transmission . TaDATA Woeuu lt Li! Start bit v Start bit iN Start bit Stop bit Stop bit RaDATA LF, ., UF LS, 1 | . pit change V "Cie change pit change Bit OVE (overrun error) becomes 1 when reading received data by CPU during receiving is delayed, and shows that an overrun error has occurred. In this case, one piece of data received previously is lost in the receive data buffer. 4-26 44Fig. 4-17 Overrun Error OVE RskDY cru Receive data buffer Receive buffer {Second buffer} (First buffer) Read character =~ Pees at eed ap Character 3 ys Ons ie - Character 1 -Gharacter 2 Character 7 6 6& os oo -~- 2 oO = ry re r . Py oS be nan 4 iF 2, ARs : ns s sale ee a ae - ~ 7 j Pees acd B = ey Char. 1 is not read by the CPU and discarded by receiving char. 2. Bit PE (parity error) becomes 1 when a parity error occurs while the parity is effective in a receive state. The foregoing three errors do not disable operations of the uPD71051. All these three error flags are cleared to 0 by a command that has the ECL bit set to 1. . Bit TxRDY (transmitter ready) always becomes 1 when the send data buffer is empty. The output pin of the same name becomes i when the send data buffer is empty, the level of CTS is low, and TxEN = 1, and the conditions of the status and pin setting will not be the same. Bit TXRDY = send data buffer empty Pin TxRDY = (send data buffer empty).(CTS = 0).(TxEN = 1) 4-275. STAND-BY MODE The uPD71051 consumes low power as it is based on CMOS fabrication technology. By entering into a stand-by mode, it restricts feeding of external input clocks (CLK, TxCLK and RxCLK) into the inside to consume less power. two methods can be used to enter a stand-by mode. One method is hard resetting. Inputting a4 high level to Pin RESET, the device enters a stand-by mode by the falling edge of the high level. The second method is soft resetting by a command. Writing of a mode word is the only way to escape from the stand-by mode. Fig. 5-1 shows timing patterns of these operations. 5-1 46Fig. 5-1 Standby Mode @ Hardware reset esse 1 5), ws i 5) / 2 a WH . Hode word " Internal ? @ software reset~ 5} 4 ah . WE Software reset command Mode word 4) Te Internal standby signal 1 is high, the external clocks to While the internal standby signa the uwPp71051 are ignored. ts written to the uPD71051 in the Note: if data (c/D = 0) should be standby mode, the following operations undefined. 5-2 fe sITable 5-1 Output Pins State in the Standby Mode Pin name State TXRDY TxEMP TXDATA RxXRDY SYNC/BRK Drs RTS Low level High level High level Low level Low level High level High level 5-36. ELECTRICAL CHARACTERISTICS Maximum Ratings (Ta = 25C) Item Symbol Condition Rating Unit Supply voltage Vop =~0.5 to +7.0 Vv Input voltage v5 ~0.5 to Vpp*0-3 Vv Output voltage Yo -0.5 to Vop*?-3 Vv Operating temperature Ts, pt -40 to +85 *c Storage temperature T. tg -65 to +150 *c 6-1va os z oot 0s fqpueqs buyangt | %99, quazing Atddns wu ol oT buy {ezedo buying Taq, o 1011 quaazina wa 1 or- 40 = A I | s6eyvat andano [aaaT #07 ag HO quarIIAS wn ot ot Ans A I | eHeyeaz yndyno asat yh , quazino wa oT- or- AO = q, TT, abeyeay ynduy [easayT #07 . quaiins vn ot OT aq, = Th HIT, ebexyvatT anduy [aseT, ybty A ro O WisZ = 10, 10, a6eq[OA yadjno [aaaT MoT A Txt -0 W4x20 vo oop- = 1; HO, | s6eqT0a yndgno Tansey ybyy A 80 $0- 8o s*o- 1, ebeqroa anduy [aaet 07 ATE 0494, zz c040, 2Z HI, eBeqqTor ynduy [eset YySty xn dL NIN xWW "dab *NIW Fun uo ua oquid: we ' ot-Tsotzaan tsoTzaan Fareuca | Tod's u (soteas = "9, o,ge+ 03 oF- = PL) SOFRSTIeVOeIEYD Oa 6-2Capacitance (Ta = 25C, Vor = ov) item Symbol Condition MIN, | TYP. | MAX. | Unit Input capacitance C, fc = 1 MH 10 pr for other than I/O capacitance Cr6 measured pins, OV 20 pF AC Characteristics (Ta = -40 to +85C, Yop = 5V+10%) Read Cycle Item synbo1 | condition | UPP7052 | wPp72053-20 | unis MIN. MAX. MIN. MAX, Address (C5, C/D) t setting time (for RD +) SAR 0 0 ns Address (CS, C/5) . maintain time Tura 0 0 ns (for RD +) RD pulse width test 150 95 ns wees sh. time orp 120 65 ns C, =150pF Data float time torr 20 80 210 65 ns (for RD +} Port (DSR, CTS) t, t setting time (for RD4} SPR 20 20 CxK 6-3 | -Write Cycle wPD71051 uPD71051-10 Item Symbol Condition Unit MIN. MAX. MIN. MAX. Address (CS, C/D) t setting time SAW 0 0 ne (for WR +) Address (CS, C/D) maintain time Sawa 0 0 ns (for WR.+) WR pulse width tuner, 150 95 ns Data setting time toow 80 BO ns (for WR +) Data maintain time town oO 0 ns {for WR +) Port (DTR, RTS), |. TxEN delay time we 8 8 ox {for WR t+) During mode t specification 6 6 CYR Write recovery In start-stop t time *Rv mode 8 8 CYK in synchron- t cus mode 16 16 CYK 6-4 1 trAKO, x x . DELY wax v9 at yapya TaaeT Yybyy astnd : ty YoTD ynduy 1a3qfusueiL MAD. 3 st ST wax tf WAD. ; t t wa x 9 x OT YIPTA Taaay oy astnd WAD. TL, YyOoTDS ynduy 1949 FusuerL a eT tT Te UE XE sn $0 s*0 / TmiLa, (XTXL 103) aut, AeTap wivaxL a ou wy YyOoTo su oz S 0g s 3 ts TT8F 4 Su oz s oz Ss wi, @Uyy asf1 yOTD su ' @ st Da, YAPTA [asaT Ao, asTad yooTD su SE as nl, WIPTA T2aaaT YBTY esTNd yO0TD su oq 00t oa zt AKI, atoko y20TD XW NIN *XVW IW u uo uO, oquAs we3t awa | ot-tsotzaan TsoTzaan Faypuea | tT HuywyL Teysueiz_, Teyi9s soT4ySpaszoRAeYD OVa 8 UXO, (4 AGUXL) OUT AeTaP xgUxL WAD 3 0z oz daxig, awyy Aelop awaxs sn T T qudSH, (astnd Buy_dues 303) owy2 upequTew yivaxd sn I t q5qas, (as{nd Buy {dues 203) owt 6uz33e8 YLvax" 2hy Oz6T od 9fST od uq x 9 Asuenbarj 2H4 Oz6T ag 9ST og zetty ug x OT YOoTS ynduy zeapaooy 2H4 ooc 2a org od dxt Wad. e MKD ina estnd yooTo ynduy 2zaayao0y 3 st ST uqxt WA, 4 I t ua xX 9 *X OT YIPTA [araT MOT Who THN, as{nd yo Ts 7ynduz zeaTasay ? zt zt ua xT 2H OZ6T oa 9EST 3a ua x 69 . Aauanbaszy ZHY | OZ6I aa SEST aa zs da x OT yoef qnduy 1033 ;uWsue1 ZHy oot 2a Ovz od ud xT *XVH NIW xWH "NIH u uo 0; s wo3I va | ot-tsotzaan Tsotzaan Fatpuog | Toqu ip, 49D) 6-6*sajepdn sn3e38 3OazJe YOTYN SQUsAa JO UOT ZRABUeb BYy 07 eND 442, gz JO Avlep wunwyxew e St e12yL Z *3a802 2 buyanp qnduz you st yOoTS waqsds osyL_ T Syrtewoy WD, geyyp s MH cua x pg xoT wo, OE/T 5 uy; oaks sua x T tWIOKY puw WIOKL JO Asuanbexzzy ayy 09 ATdde suozqoy44992 BupaoT TO} sys 2 azey pneg =T 230N we, 9 9 YIPTA TaaeT ybyy astnd 3esau (uoyzezyzuozyouds [eUura4xXg) a) BT et wuASS, out; Avtep ynduy NAS . (uoyzezyuoryouds [eutezut) WH, | gz 9z asada, aut Aeqap yadyno oNAS su OOT 00z wend, (+ Aquxy) amity Aetep Aquxy a, 9z 92 . uid, (+ Aguxu) awyy AeTep AGuxY su oot 00z uxoad, (+ AGUXL) Ouya AeTOP AguxL XW NIW XUN *NIW u uo uO oquiAs wet vena OI-Tsotzaan TsoTzaan Farpuca | (Pp, 3409)AC Test Input Waveform 2.4V . ; oul ~Heasurenang 2.2V 0.6V points ov G4 Write Data Cycle X XK isan la Ssue fawn hiwr tuwTxnRead Data Cycle tean hans tsen tant, Cea tran ma 6-9 1 JL9 tt wl fee ff " iit) LUv.is \ , Liw vive 1 VIVES) i . r aay Wadesy ati, i i \ nhneS J pewsaiey nd sung aaty WHE nests Mul Leewe pig . . apiy ray . freiey Cee ious wips48 a o ci + x Lia Viva 6 / an Luvis a viv eA asasy stl duyluieg \ (ean | 2c Hy WAS gl \ Ost whotn CHUTE, Tiaaay YVLVOXU pue YOOTD TeaAypaoou"it K VALVOREL cre s Lady LS VS \S VSS \ wee FEL wriady * U anamay * apr) AIL 6-11 K VAIEVOL. Para | WENA, a ty WEL waialy INANE WLVOXL pue YOOTD 19z3 Twsuezay,Flag Timing TsEMP TeRDY SyTma it Gather TrDATA RaRDY High STOP START / a YX \VLXXT RsDATA tonne \ LS XXX X STOP START 60RXDATA and SYNC Timing SYNC output (internal synchronization) fT tonnes FatLR ReDATA x x X YOY Synchronization character -=l pata character SYNC input / {external synchronization) Sans \ Tatrr RaDATA 6-13 XK xX xX >) fh Data characterWrite Recovery Time oN MAIN CLOCK ts tev tan ax \ / LL7. DIMENSIONS 26=-Pin Plastic DIP (600 mil) Dimensions (Unit: mm) 28 15 SON ooo swe. Soo 1 4 38.10 MAX. 2 05.20 = wo! = & Ab 3 gf a aH 12 MIN. SD 254 MAX. 0.2538 0~15 PaaC 100-@00A) 6344-Pin Plastic OFP Dimensions (Unit: mm) 204 Detail of lead end oe, < 2 = oo) o = Pa) S 3 S .0 0.352848 [01560] (0.8 . 1, gt | os ~ 1 os fol.15 0.8+2 PeGb 80-386 6428-Pin Plastic SOP (450 mil) Dimensions (Unit: # oo RA RAR RAR WV Oo PERREEUEEEBEBE 15.05 MAX. mm) 2.55 b.4 36 MAX, ; os = cz 127 MAL s oo BEES Hear 1? P20GM ~ $0- 450A2 6529<Pin PLCC Dimensions (Unit: mm) ~ & 12,45%! 11.30 i oomoo Mf) 7 mm 6 LY / + UU Uo Oooo Uw wy u an 3.4 9.9 MIN, 0.4078" 10.42" P2aL- S8Al