BUK9832-55A
TrenchMOS™ logic level FET
Rev. 01 — 31 January 2001 Product specification
c
c
M3D087
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™1 technology, featuring very low on-state resistance.
Product availability:
BUK9832-55A in SOT223 (SC-73).
2. Features
■TrenchMOS™ technology
■Q101 compliant
■150 °C rated
■Logic level compatible.
3. Applications
■Automotive and general purpose power switching:
◆12 V and 24 V loads
◆Motors, lamps and solenoids.
4. Pinning information
1. TrenchMOS is a trademark of Royal Philips Electronics.
Table 1: Pinning - SOT223 (SC-73), simplified outline and symbol
Pin Description Simplified outline Symbol
1 gate (g)
SOT223 (SC-73)
2 drain (d)
3 source (s)
4 drain (d)
4
123
MSB002 - 1
Top view s
d
g
MBB076
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 2 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
5. Quick reference data
6. Limiting values
Table 2: Quick reference data
Symbol Parameter Conditions Typ Max Unit
VDS drain-source voltage (DC) −55 V
IDdrain current (DC) Tsp =25°C; VGS =5V −12 A
Ptot total power dissipation Tsp =25°C−8W
Tjjunction temperature −150 °C
RDSon drain-source on-state resistance Tj=25°C; VGS =5V; I
D= 8 A 27 32 mΩ
Tj=25°C; VGS = 4.5 V; ID=8A −36 mΩ
Tj=25°C; VGS = 10 V; ID= 8 A 25 29 mΩ
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage (DC) −55 V
VDGR drain-gate voltage (DC) RGS =20kΩ−55 V
VGS gate-source voltage (DC) −±10 V
VGSM non-repetitive gate-source voltage tp≤50 µs−±15 V
IDdrain current (DC) Tsp =25°C; VGS =5V;Figure 2 and 3−12 A
Tsp = 100 °C; VGS =5V;Figure 2 −7A
IDM peak drain current Tsp =25°C; pulsed; tp≤10 µs;
Figure 3 −47 A
Ptot total power dissipation Tsp =25°C; Figure 1 −8W
Tstg storage temperature −55 +150 °C
Tjoperating junction temperature −55 +150 °C
Source-drain diode
IDR reverse drain current (DC) Tsp =25°C−12 A
IDRM pulsed reverse drain current Tsp =25°C; pulsed; tp≤10 µs−47 A
Avalanche ruggedness
WDSS non-repetitive avalanche energy unclamped inductive load; ID=10A;
VDS ≤55 V; VGS =5V; R
GS =50Ω;
starting Tsp =25°C
−100 mJ
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 3 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
VGS ≥4.5 V
Fig 1. Normalized total power dissipation as a
function of solder point temperature. Fig 2. Normalized continuous drain current as a
function of solder point temperature.
Tamb =25°C; IDM is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
03aa17
0
20
40
60
80
100
120
0 25 50 75 100 125 150 175
Pder
Tsp (oC)
(%)
03aa25
0
20
40
60
80
100
120
0 25 50 75 100 125 150 175
Ider
Tsp (oC)
(%)
Pder Ptot
Ptot 25 C
°
()
---------------------- 100%×=
Ider ID
ID25C
°
()
-------------------100%×=
03nc44
10-2
10-1
1
10
102
103
10-1
1 10
102
VDS (V)
ID
(A)
D.C. 100 ms
10 ms
RDSon = VDS/ ID
1 ms
tp = 10 us
100 us
tp
tp
T
P
t
T
δ =
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 4 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
7. Thermal characteristics
7.1 Transient thermal impedance
Table 4: Thermal characteristics
Symbol Parameter Conditions Value Unit
Rth(j-a) thermal resistance from junction to ambient Figure 4 70 K/W
Rth(j-sp) thermal resistance from junction to solder
point 15 K/W
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
03nc45
Single Shot
0.2
0.1
0.05
0.02
10-2
10-1
1
10
102
10-6 10-5 10-4 10-3 10-2 10-1
1 10
102
tp (s)
Zth(j-sp)
(K/W)
δ = 0.5
tp
tp
T
P
t
T
δ =
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 5 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
8. Characteristics
Table 5: Characteristics
T
j
=25
°
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage ID= 0.25 mA; VGS =0V
Tj=25°C55−−V
Tj=−55 °C50−−V
VGS(th) gate-source threshold voltage ID= 1 mA; VDS =V
GS;
Figure 9
Tj=25°C 1 1.5 2 V
Tj= 150 °C 0.6 −−V
Tj=−55 °C−−2.3 V
IDSS drain-source leakage current VDS = 55 V; VGS =0V
Tj=25°C−0.05 10 µA
Tj= 150 °C−−500 µA
IGSS gate-source leakage current VGS =±10 V; VDS =0V −2 100 nA
RDSon drain-source on-state
resistance VGS =5V; I
D=8A;
Figure 7 and 8
Tj=25°C−27 32 mΩ
Tj= 150 °C−−59 mΩ
VGS = 4.5 V; ID=8A −−36 mΩ
VGS =10V; I
D=8A −25 29 mΩ
Dynamic characteristics
Ciss input capacitance VGS =0V; V
DS =25V;
f = 1 MHz; Figure 12 −1195 1594 pF
Coss output capacitance −212 254 pF
Crss reverse transfer capacitance −144 198 pF
td(on) turn-on delay time VDD = 30 V; RL= 1.2 Ω;
VGS =5V; R
G=10Ω−14 −ns
trrise time −125 −ns
td(off) turn-off delay time −64 −ns
tffall time −68 −ns
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 6 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
Source-drain diode
VSD source-drain (diode forward)
voltage IS= 18 A; VGS =0V;
Figure 15 −0.85 1.2 V
trr reverse recovery time IS=20A;dI
S/dt = −100 A/µs
VGS =−10 V; VDS =30V −51 −ns
Qrrecovered charge −80 −nC
Table 5: Characteristics
…continued
T
j
=25
°
C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
Tj=25°CT
j=25°C; ID=15A
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values. Fig 6. Drain-source on-state resistance as a function
of gate-source voltage; typical values.
Tj=25°C
Fig 7. Drain-source on-state resistance as a function
of drain current; typical values. Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature.
03nc41
0
10
20
30
40
50
60
70
80
90
0246810
VDS (V)
ID
(A)
2.2
VGS (V) =10
3
4
5
6
7
03nc40
20
25
30
35
246810
VGS (V)
RDSon
(mΩ)
03nc42
0
10
20
30
40
50
60
70
80
0 20406080
ID (A)
RDSon
(mΩ)VGS (V) = 33.2 3.4 3.63.8 45
03nc24
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
-60 -20 20 60 100 140 180
Tj (oC)
a
aRDSon
RDSon 25 C
°
()
----------------------------
=
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 7 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
ID= 1 mA; VDS =V
GS Tj=25°C; VDS =V
GS
Fig 9. Gate-source threshold voltage as a function of
junction temperature. Fig 10. Sub-threshold drain current as a function of
gate-source voltage.
Tj=25°C; VDS =25V V
GS = 0 V; f = 1 MHz
Fig 11. Forward transconductance as a function of
drain current; typical values. Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values.
03aa33
0
0.5
1
1.5
2
2.5
-60 -20 20 60 100 140 180
max
typ
min
VGS(th)
Tj (oC)
(V)
03aa36
00.5 1 1.5 2 2.5 3
maxtyp
min
ID
VGS (V)
10-6
10-5
10-4
10-3
10-2
10-1
(A)
03nc38
0
5
10
15
20
25
30
0 1020304050
ID (A)
gfs
(S)
03nc43
0
500
1000
1500
2000
2500
3000
3500
10-2 10-1
1 10
102
VDS (V)
C (pF)
Ciss
Coss
Crss
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 8 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
VDS =25V T
j=25°C; ID=15A
Fig 13. Transfer characteristics: drain current as a
function of gate-source voltage; typical values. Fig 14. Gate-source voltage as a function of turn-on
gate charge; typical values.
VGS =0V
Fig 15. Reverse diode current as a function of reverse diode voltage; typical values.
03nc39
0
5
10
15
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VGS (V)
ID
(A)
Tj = 150 oC
Tj = 25 oC
03nc37
0
1
2
3
4
5
0102030
QG (nC)
VGS
(V)
VDD= 44 V
VDD= 14 V
03nc36
0
20
40
60
0.0 0.5 1.0 1.5
VSD (V)
IS
(A)
Tj = 150 oC
Tj = 25 oC
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 9 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
9. Package outline
Fig 16. SOT223 (SC-73).
UNIT A1bpcDEe1HELpQywv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.10
0.01
1.8
1.5 0.80
0.60
b1
3.1
2.9 0.32
0.22 6.7
6.3 3.7
3.3 2.3
e
4.6 7.3
6.7 1.1
0.7 0.95
0.85 0.1 0.10.2
DIMENSIONS (mm are the original dimensions)
SOT223 SC-73 97-02-28
99-09-13
wM
bp
D
b1
e1
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
B
c
y
0 2 4 mm
scale
A
X
132
4
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 10 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
10. Soldering
11. Revision history
Dimensions in mm.
Fig 17. Reflow soldering footprint for SOT223 (SC-73).
MSA443
1.20
(4x)
3.90
5.90
4.80
7.40
4
231
3.85
1.20 (3x)
1.30 (3x)
0.30
3.60
3.50
7.00
6.15
7.65
solder lands
solder resist
occupied area
solder paste
Table 6: Revision history
Rev Date CPCN Description
01 20010131 - Product specification; initial version.
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 11 of 13
9397 750 07734 © Philips Electronics N.V. 2001 All rights reserved.
12. Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
13. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
14. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to
make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve
design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products
are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Datasheet status Product status Definition[1]
Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may
change in any manner without notice.
Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any
time without notice in order to improve design and supply the best possible product.
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
Product specification Rev. 01 — 31 January 2001 12 of 13
9397 750 07734 © Philips Electronics N.V. 2001. All rights reserved.
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(SCA71)
© Philips Electronics N.V. 2001. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
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thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 31 January 2001 Document order number: 9397 750 07734
Contents
Philips Semiconductors BUK9832-55A
TrenchMOS™ logic level FET
1 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
7 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
7.1 Transient thermal impedance. . . . . . . . . . . . . . 4
8 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
12 Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 11
13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
