DS91C176TMA/NOPB - NATIONAL SEMICONDUCTOR

CLK1A (8 KHz)

CLK1B (8 KHz)

CLK2A (19.44 MHz)

CLK2B (19.44 MHz)

CLK3A (User Defined up to 100 MHz)

CLK3B (User Defined up to 100 MHz)

80:RT

ATCA Backplane

Slot Card N Slot Card N+1

MLVDS Transceivers

DS91C176, DS91D176

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SNLS146L –MARCH 2006–REVISED APRIL 2013

DS91D176/DS91C176 100 MHz Single Channel M-LVDS Transceivers

Check for Samples: DS91C176,DS91D176

1FEATURES DESCRIPTION

The DS91C176 and DS91D176 are 100 MHz single

2• DC to 100+ MHz / 200+ Mbps Low Power, Low channel M-LVDS (Multipoint Low Voltage Differential

EMI Operation Signaling) transceivers designed for applications that

• Optimal for ATCA, uTCA Clock Distribution utilize multipoint networks (e.g. clock distribution in

Networks ATCA and uTCA based systems). M-LVDS is a new

bus interface standard (TIA/EIA-899) optimized for

• Meets or Exceeds TIA/EIA-899 M-LVDS multidrop networks. Controlled edge rates, tight input

Standard receiver thresholds and increased drive strength are

• Wide Input Common Mode Voltage for sone of the key enhancements that make M-LVDS

Increased Noise Immunity devices an ideal choice for distributing signals via

• DS91D176 has Type 1 Receiver Input multipoint networks.

• DS91C176 has Type 2 Receiver with Fail-safe The DS91C176/DS91D176 are half-duplex

• Industrial Temperature Range transceivers that accept LVTTL/LVCMOS signals at

the driver inputs and convert them to differential M-

• Space Saving SOIC-8 Package LVDS signals. The receiver inputs accept low voltage

differential signals (LVDS, B-LVDS, M-LVDS, LV-

PECL and CML) and convert them to 3V LVCMOS

signals. The DS91D176 has a M-LVDS type 1

receiver input with no offset. The DS91C176 has an

M-LVDS type 2 receiver which enable failsafe

functionality.

Typical Application in an ATCA Clock Distribution Network

Figure 1. System Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

xxx

High High

Low Low

0 V

2.4 V

-2.4 V

50 mV

-50 mV

150 mV

Transition Region

Type 1 Type 2

VID

DS91C176, DS91D176

SNLS146L –MARCH 2006–REVISED APRIL 2013

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Connection and Logic Diagram

Top View

Figure 2. SOIC Package

See Package Number D0008A

M-LVDS Receiver Types

The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a

conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built

in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short

circuits at the input will always result in the output stage being driven to a low logic state.

Figure 3. M-LVDS Receiver Input Thresholds

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: DS91C176 DS91D176

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SNLS146L –MARCH 2006–REVISED APRIL 2013

Absolute Maximum Ratings (1)(2)

Supply Voltage, VCC −0.3V to +4V

Control Input Voltages −0.3V to (VCC + 0.3V)

Driver Input Voltage −0.3V to (VCC + 0.3V)

Driver Output Voltages −1.8V to +4.1V

Receiver Input Voltages −1.8V to +4.1V

Receiver Output Voltage −0.3V to (VCC + 0.3V)

Maximum Package Power Dissipation at +25°C

SOIC Package 833 mW

Derate SOIC Package 6.67 mW/°C above +25°C

Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)

θJA 150°C/W

θJC 63°C/W

Maximum Junction Temperature 150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 4 seconds) 260°C

ESD Ratings:

(HBM 1.5kΩ, 100pF) ≥8 kV

(EIAJ 0Ω, 200pF) ≥250 V

(CDM 0Ω, 0pF) ≥1000 V

(1) “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be verified. They are not meant to imply that the

device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

Recommended Operating Conditions Min Typ Max Units

Supply Voltage, VCC 3.0 3.3 3.6 V

Voltage at Any Bus Terminal (Separate or Common-Mode) −1.4 +3.8 V

Differential Input Voltage VID 2.4 V

LVTTL Input Voltage High VIH 2.0 VCC V

LVTTL Input Voltage Low VIL 0 0.8 V

Operating Free Air Temperature TA−40 +25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)

Parameter Test Conditions Min Typ Max Units

M-LVDS Driver

|VAB| Differential output voltage magnitude RL= 50Ω, CL= 5pF 480 650 mV

See Figure 4 and Figure 6

ΔVAB Change in differential output voltage magnitude −50 0 +50 mV

between logic states

VOS(SS) Steady-state common-mode output voltage RL= 50Ω, CL= 5pF 0.3 1.8 2.1 V

See Figure 4 and Figure 5

|ΔVOS(SS)| Change in steady-state common-mode output 0 +50 mV

(VOS(PP) @ 500KHz clock)

voltage between logic states

VOS(PP) Peak-to-peak common-mode output voltage 135 mV

VA(OC) Maximum steady-state open-circuit output voltage See Figure 7 0 2.4 V

VB(OC) Maximum steady-state open-circuit output voltage 0 2.4 V

(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless

otherwise specified.

(2) All typicals are given for VCC = 3.3V and TA= 25°C.

(3) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.

(4) CLincludes fixture capacitance and CDincludes probe capacitance.

Product Folder Links: DS91C176 DS91D176

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Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)

Parameter Test Conditions Min Typ Max Units

VP(H) Voltage overshoot, low-to-high level output RL= 50Ω, CL= 5pF,CD= 0.5pF 1.2VSS V

See Figure 9 and Figure 10 (5)

VP(L) Voltage overshoot, high-to-low level output −0.2V V

IIH High-level input current (LVTTL inputs) VIH = 2.0V -15 15 μA

IIL Low-level input current (LVTTL inputs) VIL = 0.8V -15 15 μA

VIKL Input Clamp Voltage (LVTTL inputs) IIN = -18mA -1.5 V

IOS Differential short-circuit output current See Figure 8 -43 43 mA

M-LVDS Receiver

VIT+ Positive-going differential input voltage threshold See FUNCTION TABLES Type 1 20 50 mV

Type 2 94 150 mV

VIT−Negative-going differential input voltage threshold See FUNCTION TABLES Type 1 −50 20 mV

Type 2 50 94 mV

VOH High-level output voltage (LVTTL output) IOH =−8mA 2.4 2.7 V

VOL Low-level output voltage (LVTTL output) IOL = 8mA 0.28 0.4 V

IOZ TRI-STATE output current VO= 0V or 3.6V −10 10 μA

IOSR Short-circuit receiver output current (LVTTL output) VO= 0V -48 -90 mA

M-LVDS Bus (Input and Output) Pins

IATransceiver input/output current VA= 3.8V, VB= 1.2V 32 µA

VA= 0V or 2.4V, VB= 1.2V −20 +20 µA

VA=−1.4V, VB= 1.2V −32 µA

IBTransceiver input/output current VB= 3.8V, VA= 1.2V 32 µA

VB= 0V or 2.4V, VA= 1.2V −20 +20 µA

VB=−1.4V, VA= 1.2V −32 µA

IAB Transceiver input/output differential current (IA−IB) VA= VB,−1.4V ≤V≤3.8V −4 +4 µA

IA(OFF) Transceiver input/output power-off current VA= 3.8V, VB= 1.2V,

DE = VCC 32 µA

0V ≤VCC ≤1.5V

VA= 0V or 2.4V, VB= 1.2V,

DE = VCC −20 +20 µA

0V ≤VCC ≤1.5V

VA=−1.4V, VB= 1.2V,

DE =VCC −32 µA

0V ≤VCC ≤1.5V

IB(OFF) Transceiver input/output power-off current VB= 3.8V, VA= 1.2V,

DE = VCC 32 µA

0V ≤VCC ≤1.5V

VB= 0V or 2.4V, VA= 1.2V,

DE = VCC −20 +20 µA

0V ≤VCC ≤1.5V

VB=−1.4V, VA= 1.2V,

DE = VCC −32 µA

0V ≤VCC ≤1.5V

IAB(OFF) Transceiver input/output power-off differential VA= VB,−1.4V ≤V≤3.8V,

current (IA(OFF) −IB(OFF)) DE = VCC −4 +4 µA

0V ≤VCC ≤1.5V

CATransceiver input/output capacitance VCC = OPEN 9 pF

CBTransceiver input/output capacitance 9 pF

CAB Transceiver input/output differential capacitance 5.7 pF

CA/B Transceiver input/output capacitance balance 1.0

(CA/CB)

(5) Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.

Product Folder Links: DS91C176 DS91D176

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SNLS146L –MARCH 2006–REVISED APRIL 2013

Electrical Characteristics (continued)

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3) (4)

Parameter Test Conditions Min Typ Max Units

SUPPLY CURRENT (VCC)

ICCD Driver Supply Current RL= 50Ω, DE = VCC, RE = VCC 20 29.5 mA

ICCZ TRI-STATE Supply Current DE = GND, RE = VCC 6 9.0 mA

ICCR Receiver Supply Current DE = GND, RE = GND 14 18.5 mA

Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)

Parameter Test Conditions Min Typ Max Units

DRIVER AC SPECIFICATION

tPLH Differential Propagation Delay Low to High RL= 50Ω, CL= 5 pF, 1.3 3.4 5.0 ns

CD= 0.5 pF

tPHL Differential Propagation Delay High to Low 1.3 3.1 5.0 ns

Figure 9 and Figure 10

tSKD1 (tsk(p)) Pulse Skew |tPLHD −tPHLD|(3) (4) 300 420 ps

tSKD3 Part-to-Part Skew (5) (5) 1.3 ns

tTLH (tr) Rise Time (4) 1.0 1.8 3.0 ns

tTHL (tf) Fall Time (4) 1.0 1.8 3.0 ns

tPZH Enable Time (Z to Active High) RL= 50Ω, CL= 5 pF, 8 ns

CD= 0.5 pF

tPZL Enable Time (Z to Active Low ) 8 ns

See Figure 11 and Figure 12

tPLZ Disable Time (Active Low to Z) 8 ns

tPHZ Disable Time (Active High to Z) 8 ns

tJIT Random Jitter, RJ (4) 100 MHz Clock Pattern (6) 2.5 5.5 psrms

fMAX Maximum Data Rate 200 Mbps

RECEIVER AC SPECIFICATION

tPLH Propagation Delay Low to High CL= 15 pF 2.0 4.7 7.5 ns

See Figure 13,Figure 14 and Figure 15

tPHL Propagation Delay High to Low 2.0 5.3 7.5 ns

tSKD1 (tsk(p)) Pulse Skew |tPLHD −tPHLD|(3) (4) 0.6 1.7 ns

tSKD3 Part-to-Part Skew (5) (4) 1.3 ns

tTLH (tr) Rise Time (4) 0.5 1.2 2.5 ns

tTHL (tf) Fall Time (4) 0.5 1.2 2.5 ns

tPZH Enable Time (Z to Active High) RL= 500Ω, CL= 15 pF 10 ns

See Figure 16 and Figure 17

tPZL Enable Time (Z to Active Low) 10 ns

tPLZ Disable Time (Active Low to Z) 10 ns

tPHZ Disable Time (Active High to Z) 10 ns

fMAX Maximum Data Rate 200 Mbps

(1) All typicals are given for VCC = 3.3V and TA= 25°C.

(2) CLincludes fixture capacitance and CDincludes probe capacitance.

(3) tSKD1, |tPLHD −tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative

going edge of the same channel.

(4) Not production tested. Specified by a statistical analysis on a sample basis at the time of characterization.

(5) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This

specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.

(6) Stimulus and fixture Jitter has been subtracted.

Product Folder Links: DS91C176 DS91D176

~ 2.1V

~ 1.5V

'VOS(SS)

VOS(PP)

VOS

DS91C176, DS91D176

SNLS146L –MARCH 2006–REVISED APRIL 2013

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Test Circuits and Waveforms

Figure 4. Differential Driver Test Circuit

Figure 5. Differential Driver Waveforms

Figure 6. Differential Driver Full Load Test Circuit

Figure 7. Differential Driver DC Open Test Circuit

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SNLS146L –MARCH 2006–REVISED APRIL 2013

Figure 8. Differential Driver Short-Circuit Test Circuit

Figure 9. Driver Propagation Delay and Transition Time Test Circuit

Figure 10. Driver Propagation Delays and Transition Time Waveforms

Figure 11. Driver TRI-STATE Delay Test Circuit

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Figure 12. Driver TRI-STATE Delay Waveforms

Figure 13. Receiver Propagation Delay and Transition Time Test Circuit

Figure 14. Type 1 Receiver Propagation Delay and Transition Time Waveforms

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SNLS146L –MARCH 2006–REVISED APRIL 2013

Figure 15. Type 2 Receiver Propagation Delay and Transition Time Waveforms

Figure 16. Receiver TRI-STATE Delay Test Circuit

Figure 17. Receiver TRI-STATE Delay Waveforms

FUNCTION TABLES

Table 1. DS91D176/DS91C176 Transmitting(1)

Inputs Outputs

RE DE D B A

X 2.0V 2.0V L H

X 2.0V 0.8V H L

X 0.8V X Z Z

(1) X — Don't care condition

Z — High impedance state

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Table 2. DS91D176 Receiving(1)

Inputs Output

RE DE A −B R

0.8V 0.8V ≥+0.05V H

0.8V 0.8V ≤ −0.05V L

0.8V 0.8V 0V X

2.0V 0.8V X Z

(1) X — Don't care condition

Z — High impedance state

Table 3. DS91C176 Receiving(1)

Inputs Output

RE DE A −B R

0.8V 0.8V ≥+0.15V H

0.8V 0.8V ≤+0.05V L

0.8V 0.8V 0V L

2.0V 0.8V X Z

(1) X — Don't care condition

Z — High impedance state

Table 4. DS91D176 Receiver Input Threshold Test Voltages(1)

Resulting Differential Resulting Common-Mode

Applied Voltages Receiver Output

Input Voltage Input Voltage

VIA VIB VID VIC R

2.400V 0.000V 2.400V 1.200V H

0.000V 2.400V −2.400V 1.200V L

3.800V 3.750V 0.050V 3.775V H

3.750V 3.800V −0.050V 3.775V L

−1.400V −1.350V −0.050V −1.375V H

−1.350V −1.400V 0.050V −1.375V L

(1) H — High Level

L — Low Level

Output state assumes that the receiver is enabled (RE = L)

Table 5. DS91C176 Receiver Input Threshold Test Voltages(1)

Resulting Differential Resulting Common-Mode

Applied Voltages Receiver Output

Input Voltage Input Voltage

VIA VIB VID VIC R

2.400V 0.000V 2.400V 1.200V H

0.000V 2.400V −2.400V 1.200V L

3.800V 3.650V 0.150V 3.725V H

3.800V 3.750V 0.050V 3.775V L

−1.250V −1.400V 0.150V −1.325V H

−1.350V −1.400V 0.050V −1.375V L

(1) H — High Level

L — Low Level

Output state assumes that the receiver is enabled (RE = L)

Product Folder Links: DS91C176 DS91D176

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SNLS146L –MARCH 2006–REVISED APRIL 2013

PIN DESCRIPTONS

Pin No. Name Description

1 R Receiver output pin

2 RE Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the

receiver is enabled.

3 DE Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.

4 D Driver input pin

5 GND Ground pin

6 A Non-inverting driver output pin/Non-inverting receiver input pin

7 B Inverting driver output pin/Inverting receiver input pin

8 VCC Power supply pin, +3.3V ± 0.3V

Product Folder Links: DS91C176 DS91D176

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Typical Performance Characteristics – DS91D176/DS91C176

Supply Current Output VOD

vs. vs.

Frequency Load Resistance

Supply Current measured using a clock pattern with driver terminated VCC = 3.3V, TA= +25°C

to 50ohms . VCC = 3.3V, TA= +25°C.

Figure 18. Figure 19.

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SNLS146L –MARCH 2006–REVISED APRIL 2013

REVISION HISTORY

Changes from Revision K (April 2013) to Revision L Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12

Product Folder Links: DS91C176 DS91D176

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

DS91C176TMA NRND SOIC D 8 95 Non-RoHS

& Green Call TI Call TI -40 to 85 DS91C

176MA

DS91C176TMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS91C

176MA

DS91C176TMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS91C

176MA

DS91D176TMA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS91D

176MA

DS91D176TMAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 DS91D

176MA

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

PACKAGE OPTION ADDENDUM

www.ti.com 11-Jan-2021

Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

DS91C176TMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

DS91D176TMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 31-May-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS91C176TMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

DS91D176TMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 31-May-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

.228-.244 TYP

[5.80-6.19]

.069 MAX

[1.75]

6X .050

[1.27]

8X .012-.020

[0.31-0.51]

.150

[3.81]

.005-.010 TYP

[0.13-0.25]

0 - 8 .004-.010

[0.11-0.25]

.010

[0.25]

.016-.050

[0.41-1.27]

4X (0 -15 )

.189-.197

[4.81-5.00]

NOTE 3

B .150-.157

[3.81-3.98]

NOTE 4

4X (0 -15 )

(.041)

[1.04]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

.010 [0.25] C A B

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

(.213)

[5.4]

6X (.050 )

[1.27]

8X (.061 )

[1.55]

8X (.024)

[0.6]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

EXPOSED

METAL

OPENING

SOLDER MASK METAL UNDER

SOLDER MASK

DEFINED

EXPOSED

METAL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SYMM

SEE

DETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

8X (.061 )

[1.55]

8X (.024)

[0.6]

6X (.050 )

[1.27] (.213)

[5.4]

(R.002 ) TYP

[0.05]

SOIC - 1.75 mm max heightD0008A

SMALL OUTLINE INTEGRATED CIRCUIT

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

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