Freescale Semiconductor Advance Information Document Number: MC34VR500 Rev. 4.0, 7/2015 Multi-output DC/DC Regulator for QorIQ LS1/T1 Family of Communications Processors 34VR500 Power Management The 34VR500 is a high performance, highly integrated, multi-output, SMARTMOS, DC/DC regulator solution, with integrated power MOSFETs ideally suited for the LS1/T1 family of communication processors. Integrating four switching and five linear regulators, the 34VR500 provides power to the complete system, including the processor, DDR memory, and system peripherals. Features: * Four buck converters: * SW1: 4.5 A * SW2: 2.0 A * SW3: 2.5 A * SW4: 1.0 A, (VTT tracking regulator) * Five general purpose linear regulators * DDR termination reference voltage (DDR3L and DDR4) * Programmable low-power modes * I2C control of all the regulators * Power Control Logic with processor interface and event detection * Auto qualified AEC Q100 grade 2 Applications: * Internet of Things (IoT) gateway * Mobile wireless router * MFP printer * Network attached storage * Automatic teller machine LS102X VR500 SW1 POWER CONTROL LOGIC 3.3 VIN BUS ES SUFFIX (WF-TYPE) 98ASA00589D 56 QFN-EP WF8X8 SW2 LDO2 LDO4 LDO5 SW3 SW4 REFOUT VDD TA_BB_VDD VDDC OVDD1/2 L1VDD OVDD GVDD DDR3 VTT LDO1 HDMI LDO3 Ethernet Figure 1. 34VR500 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2014-2015. All rights reserved. Table of Contents 1 2 3 4 5 6 7 8 9 Orderable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional Block Requirements and Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.2 16 MHz and 32 kHz Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 Bias and References Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Power Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 Control Interface I2C Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.2 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3 34VR500 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.4 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.1 Packaging Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 34VR500 2 Analog Integrated Circuit Device Data Freescale Semiconductor Orderable Parts 1 Orderable Parts This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number Temperature (TA) Package SW4 VTT Mode MC34VR500V1ES Enabled MC34VR500V2ES Disabled Processor LS1020/21/22A MC34VR500V3ES -40 C to 105 C 56 QFN 8x8 mm Reference Design DDR Memory Notes LS1021A IOT Gateway TWR-LS1021A DDR3L (VTT = 0.675 V) N/A (1) (2) Enabled MC34VR500V4ES Enabled MC34VR500V5ES Enabled LS1043/23A T1023/13 LS1043ARDB T1023RDB DDR4 (VTT = 0.6 V) DDR3L (VTT = 0.675 V) Notes 1. For Tape and Reel add an R2 suffix to the part number. 2. Refer Table 8 for the start-up configuration. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 3 Internal Block Diagram 2 Internal Block Diagram VR500 VLDOIN1 LDO1 LDO1 250 mA LDO2 LDO2 100 mA VLDOIN23 LDO3 LDO3 350 mA LDO4 LDO4 100 mA VLDOIN45 LDO5 LDO5 200 mA Buck Regulator Reference Generation LDO Reference Generation SW1 Buck Regulator 4500 mA FB1 SW2 Buck Regulator 2000 mA FB2 SW3 Buck Regulator 2500 mA FB3 SW4 Buck Regulator 1000 mA FB4 PVIN1 LX1 PVIN2 LX2 PVIN3 LX3 PVIN4 LX4 EPAD VDIG I C Interface REFOUT Main State Machine Clocks and Resets REFIN VHALF VDIG Regulator (Internal Use Only) VCC Regulator (Internal Use Only) VIN ICTEST1 EN VCC SGND4 2 ICTEST2 INTB VCCI2C SCL SDA Main and Standby Bandgap STBY PORB VBG VBIAS Figure 2. 34VR500 Simplified Internal Block Diagram 34VR500 4 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections Pinout Diagram SDA VBG VDIG VIN VCC SGND4 ICTEST2 DNC DNC DNC VBIAS Pinout Diagram SCL 3.1 VCCI2C Pin Connections EN 3 56 55 54 53 52 51 50 49 48 47 46 45 44 43 INTB 1 42 DNC DNC 2 41 LDO5 PORB 3 40 VLDOIN45 STBY 4 39 LDO4 ICTEST1 5 38 FB3 DNC 6 37 PVIN3 PVIN1 7 36 LX3 EP 35 LX3 FB1 13 30 REFIN SGND1 14 29 VHALF 15 16 17 18 19 20 21 22 23 24 25 26 27 28 LDO3 31 REFOUT VLDOIN23 12 LDO2 PVIN1 FB2 32 SGND3 PVIN2 11 PVIN2 LX1 LX2 33 DNC LX4 10 PVIN4 PVIN1 FB4 34 PVIN3 LDO1 9 VLDOIN1 LX1 DNC 8 SGND2 LX1 Figure 3. 34VR500 Pinout Diagram 3.2 Pin Definitions Table 2. 34VR500 Pin Definitions Pin Number Pin Name Pin Function Max. Rating Type 1 INTB O 3.6 V Digital 2, 6, 16, 33, 42, 44, 45, 46 DNC -- -- Reserved 3 PORB O 3.6 V Digital Open drain reset output to processor. 4 STBY I 3.6 V Digital Standby input signal from processor 5 ICTEST1 I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. Definition Open drain interrupt signal to processor Leave floating 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 5 Pin Connections Pin Definitions Table 2. 34VR500 Pin Definitions (continued) Pin Number Pin Name Pin Function Max. Rating Type Definition 7, 10, 12 PVIN1 (3) I 4.8 V Analog Input to SW1 regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 8, 9, 11 LX1 (3) O 4.8 V Analog SW1 switching node connection 13 FB1 (3) I 3.6 V Analog Output voltage feedback for SW1. Route this trace separately from the high current path and terminate at the output capacitance. 14 SGND1 GND - GND Signal ground for SW1 regulator. Connect to ground plane directly. 15 SGND2 GND - GND Signal ground for SW2 and SW4 regulators. Connect to ground plane directly. 17 VLDOIN1 I 3.6 V Analog Input supply for LDO1. Bypass with a 1.0 F decoupling capacitor as close to the pin as possible. 18 LDO1 O 2.5 V Analog LDO1 regulator output, Bypass with a 4.7 F ceramic output capacitor. 19 FB4 (3) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high current path and terminate at the output capacitance. 20 PVIN4 (3) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 21 LX4 (3) O 4.8 V Analog Regulator 4 switching node connection 22 (3) O 4.8 V Analog Regulator 2 switching node connection LX2 23, 24 PVIN2 (3) I 4.8 V Analog Input to SW2 regulator. Connect pins 23 and 24 together and bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to these pins as possible. 25 FB2 (3) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high current path and terminate at the output capacitance. 26 LDO2 O 3.6 V Analog LDO2 regulator output. Bypass with a 2.2 F ceramic output capacitor. 27 VLDOIN23 I 3.6 V Analog Input supply for LDO2 and LDO3. Bypass with a 1.0 F decoupling capacitor as close to the pin as possible. 28 LDO3 O 3.6 V Analog LDO3 regulator output, Bypass with a 4.7 F ceramic output capacitor. 29 VHALF I 3.6 V Analog Half supply reference for DDR reference. 30 REFIN I 3.6 V Analog REFOUT regulator input. Bypass with at least 1.0 F decoupling capacitor as close to the pin as possible. 31 REFOUT O 3.6 V Analog REFOUT regulator output 32 SGND3 GND - GND Ground reference for the SW3 regulator. Connect directly to ground plane. 34, 37 PVIN3 (3) I 4.8 V Analog Input to SW3 regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close to the pin as possible. 35, 36 LX3 (3) O 4.8 V Analog Regulator SW3 switching node connection 38 FB3 (3) I 3.6 V Analog Output voltage feedback for SW3. Route this trace separately from the high current path and terminate at the output capacitance. 39 LDO4 O 3.6 V Analog LDO4 regulator output. Bypass with a 2.2 F ceramic output capacitor. 40 VLDOIN45 I 4.8 V Analog Input supply for LDO4 and LDO5. Bypass with a 1.0 F decoupling capacitor as close to the pin as possible. 43 VBIAS I 1.8 V Analog Bypass the pin with a 0.47 F capacitor. 41 LDO5 O 3.6 V Analog LDO5 regulator output. By pass with a 2.2 F ceramic output capacitor. 47 ICTEST2 I 7.5 V Digital/ Analog Reserved pin. Connect to GND in application. 48 SGND4 GND - GND 49 VCC O 3.6 V Analog Ground for the main band gap regulator. Connect directly to ground plane. Analog Core supply 34VR500 6 Analog Integrated Circuit Device Data Freescale Semiconductor Pin Connections Pin Definitions Table 2. 34VR500 Pin Definitions (continued) Pin Number Pin Name Pin Function Max. Rating Type 50 VIN I 4.8 V Analog Main chip supply 51 VDIG O 1.5 V Analog Digital Core supply 52 VBG O 1.5 V Analog Main band gap reference. Bypass with 0.22uF capacitor. 53 SDA I/O 3.6 V Digital I2C data line (Open drain) 54 SCL I 3.6 V Digital I2C clock 55 VCCI2C I 3.6 V Analog Supply for I2C bus. Bypass with 0.1 F ceramic capacitor 56 EN I 3.6 V Digital Enable input. Connect to the processor. Pull-up via an 8.0 k to 100 k to VBIAS if required - EP GND - GND Expose pad. Functions as ground return for buck regulators. Tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. Definition Notes 3. Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be connected to the VIN pin with a 0.1 F bypass capacitor. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 7 General Product Characteristics Absolute Maximum Ratings 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 3. Absolute Maximum Ratings All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section. Symbol Description Value Unit -0.3 to 4.8 V 2000 500 V Notes ELECTRICAL RATINGS VIN VESD Main input supply voltage ESD Ratings Human Body Model Charge Device Model (4) Notes 4. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 34VR500 8 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics Thermal Characteristics 4.2 Thermal Characteristics Table 4. Thermal Ratings Symbol Description (Rating) Min. Max. Unit Notes THERMAL RATINGS TA Ambient Operating Temperature Range -40 105 C TJ Operating Junction Temperature Range -40 125 C Storage Temperature Range -65 150 C - Note 7 C (6) (7) Junction to Ambient Natural Convection Four layer board (2s2p) Eight layer board (2s6p) - - 28 15 C/W (8) (9) (10) Junction to Ambient (at 200 ft/min) Four layer board (2s2p) - 22 C/W (8) (10) Junction to Board - 10 C/W (11) RJCBOTTOM Junction to Case Bottom - 1.2 C/W (12) JT Junction to Package Top Natural Convection - 2.0 C/W (12) TST TPPRT Peak Package Reflow Temperature (5) QFN56 THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS RJA RJMA RJB Notes 5. Do not operate beyond 125 C for extended periods of time. Operation above 150 C may cause permanent damage to the IC. See Table 5 for thermal protection features. 6. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 7. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 8. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 9. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. 10. Per JEDEC JESD51-6 with the board horizontal. 11. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 12. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 13. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD512. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 9 General Product Characteristics Electrical Characteristics 4.2.1 Power Dissipation During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the thermal management and to avoid overheating, the 34VR500 provides thermal protection. An internal comparator monitors the die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register INTSENSE0. In the event of excessive power dissipation, thermal protection circuitry will shut down the 34VR500. This thermal protection will act above the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protection is not tripped under normal conditions. Table 5. Thermal Protection Thresholds Parameter Min. Typ. Max. Units Thermal 110 C Threshold (THERM110) 100 110 120 C Thermal 120 C Threshold (THERM120) 110 120 130 C Thermal 125 C Threshold (THERM125) 115 125 135 C Thermal 130 C Threshold (THERM130) 120 130 140 C Thermal Warning Hysteresis 2.0 - 4.0 C Thermal Protection Threshold 130 140 150 C 4.3 Electrical Characteristics 4.3.1 I/O Specifications Notes Table 6. General PMIC Static Characteristics. TA = -40 to 105 C, VVIN = 2.8 to 4.5 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V 4.0%, typical external component values and full load current range, unless otherwise noted. Pin Name EN PORB SCL SDA INTB STBY Parameter Load Condition Min. Max. Unit VIL - 0.0 0.2 *VVBIAS V VIH - 0.8 *VVBIAS 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VVIN VVIN V VIL - 0.0 0.2 * VVCCI2C V VIH - 0.8 * VVCCI2C 3.6 V VIL - 0.0 0.2 * VVCCI2C V VIH - 0.8 * VVCCI2C 3.6 V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7 * VVCCI2C VVCCI2C V VOL -2.0 mA 0.0 0.4 V VOH Open Drain 0.7* VVIN VVIN V VIL - 0.0 0.2 *VVBIAS V VIH - 0.8 *VVBIAS 3.6 V Notes 34VR500 10 Analog Integrated Circuit Device Data Freescale Semiconductor General Product Characteristics Electrical Characteristics 4.3.2 Current Consumption Table 7. Current Consumption Summary TA = -40 to 105 C, (See Table 3), VVIN = 3.6 V, VVCCI2C = 1.7 to 3.6 V, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VVIN = 3.6 V, VVCCI2C = 3.3 V, and 25 C, unless otherwise noted. Mode Off Sleep Standby 34VR500 Conditions System Conditions Typical Max. Unit Notes Wake-up from EN active 32 k RC on All other blocks off VIN UVDET PMIC able to wake-up 17 25 A (14) (15) Wake-up from EN active Trimmed reference active SW3 PFM Trimmed 16 MHz RC off 32 k RC on REFOUT disabled DDR memories in self refresh 122 250 A (15) SW1 in PFM SW2 in PFM SW3 in PFM SW4 in PFM Trimmed 16 MHz RC enabled Trimmed reference active LDO1 - 5 enabled REFOUT enabled Processor enabled in low power mode. All rails powered on except boost (load = 0 mA) 297 550 A (15) Notes 14. When VIN is below the UVDET threshold, in the range of 1.8 V VIN < 2.65 V, the quiescent current increases by 50 A, typically. 15. For PFM operation (as defined in Table 23). 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 11 General Description Features 5 General Description The 34VR500 is a high performance, highly integrated, multi-output, DC/DC regulator solution, with integrated power MOSFETs ideally suited for the LS1/T1 family of communication processors. 5.1 Features This section summarizes the 34VR500 features. * Input voltage range: 2.8 V to 4.5 V * Buck regulators * Four independent outputs * SW1, 4.5 A; 0.625 V to 1.875 V * SW2, 2.0 A; 0.625 V to 1.975 V * SW3, 2.5 A; 0.625 V to 1.975 V * SW4, 1.0 A; operates in VTT mode for DDR termination at 50% of SW3 for 34VR500V1, 34VR500V3, 34VR500V4, 34VR500V5 and 0.625 V to 1.975 V for 34VR500V2 * Dynamic voltage scaling * Modes: PWM, PFM, APS * Programmable output voltage * Programmable current limit * Programmable soft start * Programmable PWM switching frequency * Programmable OCP with fault interrupt * LDOs * Five general purpose LDOs * LDO1, 0.80 V to 1.55 V, 250 mA * LDO2, 1.8 V to 3.3 V, 100 mA * LDO3, 1.8 V to 3.3 V, 350 mA * LDO4, 1.8 V to 3.3 V, 100 mA * LDO5, 1.8 V to 3.3 V, 200 mA * Soft start * DDR memory reference voltage * REFOUT, 10 mA * 16 MHz internal master clock * I2C interface * User programmable Standby, Sleep, and OFF modes 34VR500 12 Analog Integrated Circuit Device Data Freescale Semiconductor General Description Functional Block Diagram 5.2 Functional Block Diagram MC34VR500 Functional Block Diagram Start-up Configuration (Factory programmable) Power Generation Vo1 Vo4 SW1 (0.625 - 1.875 V) 4.5 A SW2 (0.625-1.975 V) 2.0 A SW4 (0.625 - 1.975 V) 1.0 A VTT option SW3 (0.625-1.975 V) 2.5 A LDO1 (0.8 - 1.55 V) 250 mA LDO2 (1.8 - 3.3 V) 100 mA Vo2 Voltage Phasing and Frequency Selection Sequence and Timing Vo3 Logic and Control Parallel MCU Interface Regulator Control 2 LDO3 (1.8 - 3.3 V) 350 mA LDO4 (1.8 - 3.3 V) 100 mA I C Communication & Registers Fault Detection & Protection LDO5 (1.8 - 3.3 V) 200 mA Thermal Current Limit Short-circuit Figure 4. 34VR500 Functional Block Diagram 5.3 Functional Description 5.3.1 Power Generation The 34VR500 PMIC features four buck regulators, five general purpose LDOs, and a DDR voltage reference to supply voltages for the processor, memory, and peripheral devices. Depending on the system power path configuration, the five general purpose LDO regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific REFOUT voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination 5.3.2 Control Logic The 34VR500 PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including interrupt and reset. Startup voltage and sequence are internally programed. After power up, the regulator voltages can be changed via I2C. The 34VR500 PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 13 General Description Functional Description 5.3.2.1 Interface Signals EN EN is an input signal to the IC that generates a turn-on event. Refer to section Turn ON Events for more details. STBY STBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STBY can be configured as active high or active low using the STBYINV bit. Refer to the section Standby Mode for more details. PORB PORB is an open-drain, active low output. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 8 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. INTB INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is deasserted after the fault interrupt is cleared by software, which requires writing a "1" to the fault interrupt bit. 34VR500 14 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Start-up 6 Functional Block Requirements and Behaviors 6.1 Start-up The 34VR500 starts up from the internal configuration, which is hard-coded into the device. However, the 34VR500 can be controlled through the I2C port after the Start-up sequence. It is also possible to modify the contents of the Internal Registers via the bus I2C to modify the start up parameters (see section Start Sequence Creation). 6.1.1 Device Start-up Configuration Table 8 shows the internal configuration for the 34VR500V1, 34VR500V2, 34VR500V3, 34VR500V4, 34VR500V5. Table 8. Start-up Configuration Registers 34VR500V1 34VR500V2 Default I2C Address 34VR500V3 34VR500V4 34VR500V5 0x08 LDO2_VOLT 1.8 V 1.8 V 1.8 V 2.5 V 2.5 V LDO2_SEQ 1 1 1 2 2 LDO3_VOLT 2.5 V LDO3_SEQ 1 1 3 2 2 LDO4_VOLT 2.5 V 2.5 V 2.5 V 1.8 V 1.8 V LDO4_SEQ 1 1 1 3 3 LDO5_VOLT 1.8 V 1.8 V 1.8 V 3.3 V 3.3 V LDO5_SEQ 1 1 1 3 3 SW1_VOLT 1.0 V 1.0 V 1.0 V 1.5 V 1.5 V SW1_SEQ 2 SW2_VOLT 1.0 V 1.0 V 1.0 V 1.8 V 1.8 V SW2_SEQ 2 2 2 1 1 SW3_VOLT 1.35 V 1.35 V 1.2 V 1.2 V 1.35 V SW3_SEQ 3 3 3 12 12 SW4_VOLT VTT 1.8 V VTT VTT VTT SW4_SEQ 3 3 3 12 12 REFOUT_SEQ 3 3 3 12 12 LDO1_VOLT 1.2 V 1.2 V 1.2 V 1.35 V 1.35 V LDO1_SEQ 4 4 4 1 12 PU CONFIG, SEQ_CLK_SPEED PU CONFIG, SWDVS_CLK 1.0 ms 6.25 mV/s SW1 CONFIG 2.0 MHz SW2 CONFIG 2.0 MHz SW3 CONFIG 2.0 MHz SW4 CONFIG 2.0 MHz 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Functional Block Requirements and Behaviors Start-up UVDET VIN tD1 tR1 EN tD2 tR2 LDO2,3,4,5 tD3 tR2 SW1,2 tD3 tR2 SW3,4 REFOUT TD3 LDO1 tR2 tD4 tR3 PORB Figure 5. Starting Sequence: Example for V1 and V2 Table 9. 34VR500V1 and V2 Start-up Sequence Timing Parameter Typ. Unit Turn-on delay 6.0 ms tR1 Rise time of EN (16) ms tD2 Turn-on delay of first regulator 2.5 ms 0.2 ms tD1 Description (17) tR2 Rise time of regulators tD3 Delay between regulators 1.0 ms tD4 Turn-on delay of PORB 2.0 ms tR3 Rise time of PORB 0.2 ms Notes 16. Depends on the external signal driving EN. 17. Rise time is a function of slew rate of regulators and nominal voltage selected. 34VR500 16 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Start-up 6.1.2 Start Sequence Creation The 34VR500 powers up based on the contents of the internal registers. Depending on certain bit settings, the internal registers are loaded from different sources, as shown in Figure 6. Figure 6. Starting Sequence The contents of the internal registers are initialized to zero when a valid VIN is first applied. The values that are then loaded into the internal registers depend on the value of the TBB_POR (the initial value of TBB_POR is always "0"): * If TBB_POR = 0 the values are loaded from the Default Sequence (this is the case always for first starting) * If TBB_POR = 1 the values are loaded from the internal RAM. VIN must be valid to maintain the contents of the internal RAM. To power on with the contents of the internal RAM, the following conditions must exist: * VIN is valid * TBB_POR = 1 and there is a valid turn-on event via the EN pin To keep a regulator off during a start-up sequence is to set its sequence to 0. This corresponds to the XX_SEQ setting of 0x00. For example, 0x01 corresponds to a sequence of 1, and so on. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 17 Functional Block Requirements and Behaviors 16 MHz and 32 kHz Clocks Figure 7 explains how to start from a new configuration. First VIN Applied 34VR500 regulators will not turn on Keep EN pin in low state Program the new start sequence and set TBB_POR to 1 I2C programming + TBB_POR = 1 Create a Turn On event via the EN pin Turn On event EN pin to high state TBB_POR TBB_POR = 1 Start from the Internal RAM TBB_POR = 0 Start from the Default Sequence Figure 7. Modifying a Starting Sequence Table 95 shows the portion of the register map concerning the programming of a new starting sequence. 6.2 16 MHz and 32 kHz Clocks There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within -8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions: * VIN < UVDET * All regulators are in SLEEP mode * All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions: * During start-up, VIN > UVDET In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 20 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and ENI interrupts, which are referenced to the 32 kHz untrimmed clock. 34VR500 18 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Bias and References Block Description Table 10. 16 MHz Clock Specifications TA = -40 to 105 C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V 4.0%, and typical external component values. Typical values are characterized at VVIN = 3.6 V, and 25 C, unless otherwise noted. Symbol Min. Typ. Max. Units Operating Voltage from the VIN pin 2.8 - 4.5 V f16MHZ 16 MHz Clock Frequency 14.7 16 17.3 MHz f2MHZ 2.0 MHz Clock Frequency 1.84 - 2.16 MHz VIN Parameters Notes (18) Notes 18. 2.0 MHz clock is derived from the 16 MHz clock. 6.2.1 Clock adjustment The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By changing the factory trim values of the 16 MHz clock, the user may add an offset as small as 3.0% of the nominal frequency. Contact a Freescale representative for detailed information on this feature. 6.3 Bias and References Block Description 6.3.1 Internal Core Voltage References All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VBG. The bandgap and the rest of the core circuitry are supplied from VCC. Table 11 shows the main characteristics of the core circuitry. Table 11. Core Voltages Electrical Specifications(20) TA = -40 to 105 C (See Table 3), VVIN = 2.8 to 4.5 V, VVBIAS = 1.0 V 4.0%, and typical external component values. Typical values are characterized at VVIN = 3.6 V, and 25 C, unless otherwise noted. Symbol Parameters Min. Typ. Max. Units Notes - - 1.5 1.3 - - V (19) - - 2.775 0.0 - - V (19) Output Voltage - 1.2 - V (19) VBGACC Absolute Accuracy - 0.5 - % VBGTACC Temperature Drift - 0.25 - % VDIG (digital core supply) VDIG Output Voltage ON mode OFF mode VCC (Analog core supply) VCC Output Voltage ON mode OFF mode VBG (BANDGAP / REGULATOR REFERENCE) VBG Notes 19. 3.0 V < VIN < 4.5 V, no external loading on VDIG, VCC, or VBG. Extended operation down to UVDET, but no system malfunction. 20. For information only. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 19 Functional Block Requirements and Behaviors Bias and References Block Description 6.3.1.1 External Components Table 12. External Components for Core Voltages 6.3.2 Regulator Capacitor Value (F) VDIG 1.0 VCC 1.0 VBG 0.22 REFOUT Voltage Reference REFOUT is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole. This divider then utilizes a voltage follower to drive the load. REFIN REFIN CHALF1 100 nF VHALF _ CHALF2 100 nF + Discharge REFOUT REFOUT CREFDDR 1.0 uf Figure 8. REFOUT Block Diagram 6.3.2.1 REFOUT Control Register The REFOUT voltage reference is controlled by a single bit in REFOUTCTRL register in Table 13. Table 13. Register REFOUTCTRL - ADDR 0x6A Name UNUSED REFOUTEN UNUSED Bit # R/W Default Description 3:0 - 0x00 UNUSED 4 R/W 0x00 Enable or disables REFOUT output voltage 0 = REFOUT Disabled 1 = REFOUT Enabled 7:5 - 0x00 UNUSED 34VR500 20 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Bias and References Block Description External Components Table 14. REFOUT External Components(21) Capacitor (22) REFIN to VHALF Capacitance (F) 0.1 VHALF to GND 0.1 REFOUT 1.0 Notes 21. Use X5R or X7R capacitors. 22. REFIN to GND, 1.0 F minimum capacitance is provided by buck regulator output. REFOUT Specifications Table 15. REFOUT Electrical Characteristics TA = -40 to 105 C (See Table 3), VIN = 3.6 V, IREFDDR = 0.0 mA, VREFIN = 1.5 V, VVBIAS = 1.0 V 4.0%, and typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VREFIN = 1.5 V, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes REFOUT VREFIN Operating Input Voltage Range 1.2 - 1.8 V IREFDDR Operating Load Current Range 0.0 - 10 mA Current Limit, IREFDDR when VREFOUT is forced to VREFIN/4 10.5 15 25 mA Quiescent Current - 8.0 - A VREFOUT Output Voltage 1.2 V < VREFIN < 1.8 V, 0.0 mA < IREFDDR < 10 mA - VREFIN/2 - V VREFOUTTOL Output Voltage Tolerance 1.2 V < VREFIN < 1.8 V, 0.6 mA IREFDDR 10 mA -1.0 - 1.0 % VREFOUTLOR Load Regulation 1.0 mA < IREFDDR < 10 mA, 1.2 V < VREFIN < 1.8 V - 0.40 - mV/mA tONREFDDR Turn-on Time, Enable to 90% of end value VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA - - 100 s tOFFREFDDR Turn-Off Time, Disable to 10% of initial value VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA - - 10 ms VREFOUTOSH Start-up Overshoot VREFIN = 1.2 V, 1.8 V, IREFDDR = 0.0 mA - 1.0 6.0 % VREFOUTTLR Transient Load Response VREFIN = 1.2 V, 1.8 V - 5.0 - mV IREFDDRLIM IREFDDRQ (23) Active Mode - DC Active Mode - AC Notes 23. When REFOUT is off there is a quiescent current of 1.5 A typical. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 21 Functional Block Requirements and Behaviors Power Generation 6.4 Power Generation 6.4.1 Modes of Operation The operation of the 34VR500 can be reduced to four states, or modes: ON, OFF, Sleep, and Standby. Figure 9 shows the state diagram of the 34VR500, along with the conditions to enter and exit from each state. Thermal shutdown OFF Sleep EN = 1 & VIN > UVDET EN = 0 Any SWxOMODE bits=1 EN = 0 All SWxOMODE bits= 0 EN = 0 Any SWxOMODE bits=1 EN = 1 & VIN > UVDET ON Thermal shudown STANDBY asserted STANDBY de-asserted EN = 0 All SWxOMODE bits= 0 Thermal shutdown Standby Figure 9. State Diagram To complement the state diagram in Figure 9, a description of the states is provided in following sections. Note that VIN must exceed the rising UVDET threshold to allow a power up. Refer to Table 22 for the UVDET thresholds. Additionally, the interrupt signal and INTB are only active in Sleep, Standby, and ON states. 6.4.1.1 ON Mode The 34VR500 enters the ON mode after a turn-on event. PORB is de-asserted, high, in this mode of operation. 6.4.1.2 OFF Mode The 34VR500 enters the OFF mode after a turn-off event. A thermal shutdown event also forces the 34VR500 into the OFF mode. Only VDIG is powered in this mode of operation. To exit the OFF mode, a valid turn-on event is required. PORB is asserted, LOW, in this mode. 34VR500 22 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.1.3 Standby Mode * Depending on STBY pin configuration, Standby is entered when the STBY pin is asserted. This is typically used for low-power mode of operation. * When STBY is de-asserted, Standby mode is exited. A product may be designed to go into a Low-power mode after periods of inactivity. The STBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby are pre-programmed through the I2C interface. Note that the STBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarity as shown in Table 16. When the 34VR500 is powered up first, regulator settings for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STBY pin polarity to Active Low, set the STBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STBY will generally be referred to as active high throughout this document. Table 16. STBY Pin and Polarity Control STBY (Pin)(25) STBYINV (I2C bit)(26) STBY Control (24) 0 0 0 0 1 1 1 0 1 1 1 0 Notes 24. STBY = 0: System is not in Standby, STBY = 1: System is in Standby 25. The state of the STBY pin only has influence in On mode. 26. Bit 6 in Power Control Register (ADDR - 0x1B) Since STBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 17, STBYDLY will delay the Standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event. Table 17. STBY Delay - Initiated Response STBYDLY[1:0](27) Function 00 No Delay 01 One 32 k period (default) 10 Two 32 k periods 11 Three 32 k periods Notes 27. Bits [5:4] in Power Control Register (ADDR - 0x1B) 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 23 Functional Block Requirements and Behaviors Power Generation 6.4.1.4 Sleep Mode * Depending on EN pin configuration, Sleep mode is entered when EN is de-asserted and SWxOMODE bit is set. * To exit Sleep mode, assert the EN pin. In the Sleep mode, the regulator will use the set point as programmed by SW1OFF[5:0] for SW1, SW2, SW3, and SW4. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 18 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event. Table 18. Regulator Mode Control SWxOMODE Off Operational Mode (Sleep) (28) 0 Off 1 PFM Notes 28. For sleep mode, an activated switching regulator, should use the off mode set point as programmed by SW1OFF[5:0] for SW1, SW2, SW3, and SW4. 6.4.2 State Machine Flow Summary Table 19 provides a summary matrix of the 34VR500 flow diagram to show the conditions needed to transition from one state to another. Table 19. State Machine Flow Summary Next State Initial State STATE OFF Sleep Standby ON OFF X X X EN = 1 & VIN > UVDET Sleep Thermal Shutdown X X EN = 1 & VIN > UVDET EN = 0, Any SWxOMODE = 1 X Standby de-asserted EN = 0, Any SWxOMODE = 1 Standby asserted X Standby Thermal Shutdown EN = 0, All SWxOMODE = 0 ON Thermal Shutdown EN = 0, All SWxOMODE = 0 6.4.2.1 Turn ON Events From OFF and Sleep modes, the PMIC is powered on by a turn ON event. VIN must be greater than UVDET for the PMIC to turn-on. When VIN is greater than UVDET, a logic high on the EN pin is a turn ON event, when EN is high before VIN is valid, a VIN transition, from 0.0 V to a voltage greater than UVDET, also a Turn ON event. See the State diagram, Figure 9, and the Table 19 for more details. Any regulator enabled in the Sleep mode will remain enabled when transitioning from Sleep to ON, i.e., the regulator will not be turned OFF and then ON again to match the start-up sequence. The following is a more detailed description of the EN configuration: * The EN signal is high and VIN > UVDET, the PMIC will turn ON; the interrupt and sense bits, ENI and ENS respectively, will be set. The sense bit will show the real time status of the EN pin. In this configuration, the EN input can be a mechanical switch debounced through a programmable debouncer, ENDBNC[1:0], to avoid a response to a very short (i.e., unintentional) key press. The interrupt is generated for both the falling and the rising edge of the EN pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with ENDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode. 34VR500 24 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 20. EN Hardware Debounce Bit Settings Bits State ENDBNC[1:0] Turn On Debounce (ms) Falling Edge INT Debounce (ms) Rising Edge INT Debounce (ms) 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 Notes 29. The sense bit, ENS, is not debounced and follows the state of the EN pin. 6.4.2.2 Turn OFF Events EN Pin The EN pin is used to power off the 34VR500. The Off mode is entered when the EN pin is low and SWxOMODE = 0. Thermal Protection If the die temperature surpasses a given threshold, the thermal protection circuit will power off the 34VR500 to avoid damage. A turn-on event will not power on the PMIC while it is in thermal protection. The part will remain in Off mode until the die temperature decreases below a given threshold. There are no specific interrupts related to this other than the warning interrupt. See Power Dissipation section for more detailed information. Undervoltage Detection The state machine will transition to the OFF mode when the voltage at the VIN pin drops below the UVDET undervoltage falling threshold. 6.4.3 Power Tree The 34VR500 features four buck regulators, five general purpose LDOs, and a DDR voltage reference, to supply voltages for the application and peripheral devices. The buck regulators are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they are powered ON or OFF. The five general use LDO regulators are directly supplied from the main input supply or from the switching regulators depending on the application requirements. Since REFOUT is intended to provide DDR memory reference voltage, it should be supplied by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for REFOUT. Refer to Table 21 for a summary of all power supplies provided by the 34VR500. Table 21. Power Tree Summary Supply Output Voltage (V) Step Size (mV) Maximum Load Current (mA) SW1 0.625 - 1.875 25 4500 SW2 0.625 - 1.975 25 2000 SW3 0.625 - 1.975 25 2500 SW4 0.5*SW3_OUT (VTT for V1, V3, V4, V5), 0.625 - 1.975 (for V2) LDO1 0.80 - 1.55 50 250 LDO2 1.8 - 3.3 100 100 LDO3 1.8 - 3.3 100 350 LDO4 1.8 - 3.3 100 100 LDO5 1.8 - 3.3 100 200 REFOUT 0.5*SW3_OUT NA 10 1000 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 25 Functional Block Requirements and Behaviors Power Generation The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 22 summarizes the UVDET thresholds. Table 22. UVDET Threshold UVDET Threshold VIN Rising 3.1 V Falling 2.65 V VR500 LS102x SW1 VDDCORE (0.625 to 1.875 V), 4.5 A SW2 VDDC (0.625 to 1.975 V), 2.0 A VIN 3.3 V VDDCORE VDDC LDO2 (1.8 to 3.3 V), 100 mA OVDD1/2 LDO4 (1.8 to 3.3 V), 100 mA L1VDD LDO5 (1.8 to 3.3 V), 200 mA OVDD SW3 DDR CORE (0.625 to 1.975 V), 2.5 A SW4 System/VTT (0.625 to 1.975 V) (0.5*VDDR) 1.0 A SW3 VIN 3.3 V REFOUT 0.5*VDDR, 10 mA LDO1 (0.80 to 1.55 V), 250 mA DDR3 VTT Peripherals LDO3 (1.8 to 3.3 V), 350 mA Figure 10. 34VR500 Typical Power Map 34VR500 26 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4 Buck Regulators Each buck regulator is capable of operating in PFM, APS, and PWM switching modes. 6.4.4.1 Current Limit Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 6.4.4.2 General Control To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur by any of the following means: I2C programming, exiting/entering the Standby mode, exiting/entering Sleep mode, and load current variation. Available switching modes for buck regulators are presented in Table 23. Table 23. Switching Mode Description Mode Description OFF The regulator is switched off and the output voltage is discharged. PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Table 24 summarizes the Buck regulator programmability for Normal and Standby modes. Table 24. Regulator Mode Control SWxMODE[3:0] Normal Mode Standby Mode SWxMODE[3:0] Normal Mode Standby Mode 0000 Off Off 1000 APS APS 0001 PWM Off 1001 Reserved Reserved 0010 Reserved Reserved 1010 Reserved Reserved 0011 PFM Off 1011 Reserved Reserved 0100 APS Off 1100 APS PFM 0101 PWM PWM 1101 PWM PFM 0110 PWM APS 1110 Reserved Reserved 0111 Reserved Reserved 1111 Reserved Reserved Transitioning between Normal and Standby modes can affect a change in switching modes as well as output voltage. The rate of the output voltage change is controlled by the Dynamic Voltage Scaling (DVS), explained in Dynamic Voltage Scaling. For each regulator, the output voltage options are the same for Normal and Standby modes. When in Standby mode, the regulator outputs the voltage programmed in its standby voltage register and will operate in the mode selected by the SWxMODE[3:0] bits. Upon exiting Standby mode, the regulator will return to its normal switching mode and its output voltage programmed in its voltage register. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 27 Functional Block Requirements and Behaviors Power Generation Any regulators whose SWxOMODE bit is set to "1" will enter Sleep mode if a EN turn-off event occurs, and any regulator whose SWxOMODE bit is set to "0" will be turned off. In Sleep mode, the regulator outputs the voltage programmed in its off (Sleep) voltage register and operates in the PFM mode. The regulator will exit the Sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit is set to "1" will remain on and change to its normal configuration settings when exiting the Sleep state to the ON state. Any regulator whose SWxOMODE bit is set to "0" will be powered up with the same delay in the start-up sequence as when powering On from Off. At this point, the regulator returns to its default ON state output voltage and switch mode settings. Table 18 shows the control bits in Sleep mode. When Sleep mode is activated by the SWxOMODE bit, the regulator will use the set point as programmed by SWxOFF[5:0] for SW1, SW2, SW3, and SW4. 6.4.4.3 Dynamic Voltage Scaling To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor. 1. Normal operation: The output voltage is selected by I2C bits SWx[5:0] for SW1, SW2, SW3, and SW4. A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 26. 2. Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SWxSTBY[5:0] for SW1, SW2, SW3, and SW4. Voltage transitions initiated by a Standby event are governed by the SWxDVSSPEED[1:0] and I2C bits shown in Table 26. 3. Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SWxOFF[5:0] for SW1, SW2, SW3, and SW4. Voltage transitions initiated by a turn-off event are governed by the SWxDVSSPEED[1:0] I2C bits shown in Table 26. Table 25, Table 26, summarize the set point control and DVS time stepping applied to all regulators. Table 25. DVS Control Logic for SW1, SW2, SW3, and SW4 STBY Set Point Selected by 0 SWx[5:0] 1 SWxSTBY[5:0] Table 26. DVS Speed Selection for SW1, SW2, SW3, and SW4 SWxDVSSPEED[1:0] Function 00 25 mV step each 2.0 s 01 (default) 25 mV step each 4.0 s 10 25 mV step each 8.0 s 11 25 mV step each 16 s The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. 34VR500 28 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Requested Set Point Internally Controlled Steps Output Voltage with light Load Example Actual Output Voltage Output Voltage Initial Set Point Actual Output Voltage Internally Controlled Steps Request for Higher Voltage Voltage Change Request Possible Output Voltage Window Request for Lower Voltage Initiated by I2C Programming, Standby Control Figure 11. Voltage Stepping with DVS 6.4.4.4 Regulator Phase Clock The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 27. By default, each regulator is initialized at 90 out of phase with respect to each other. For example, SW1 is set to 0 , SW2 is set to 90 , SW3 is set to 180 , and SW4 is set to 270 by default at power up. Table 27. Regulator Phase Clock Selection SWxPHASE[1:0] Phase of Clock Sent to Regulator (degrees) 00 0 01 90 10 180 11 270 The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 29 shows the selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 and 4.0 MHz, 180 are the same in terms of phasing. Table 28 shows the optimum phasing when using more than one switching frequency. Table 28. Optimum Phasing Frequencies Optimum Phasing 1.0 MHz 2.0 MHz 0 180 1.0 MHz 4.0 MHz 0 180 2.0 MHz 4.0 MHz 0 180 1.0 MHz 2.0 MHz 4.0 MHz 0 90 90 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 29 Functional Block Requirements and Behaviors Power Generation Table 29. Regulator Frequency Configuration 6.4.4.5 SWxFREQ[1:0] Frequency 00 1.0 MHz 01 2.0 MHz 10 4.0 MHz 11 Reserved SW1 Regulator The SW1 is a 4.5 A regulator capable of providing an output from 0.625 to 1.875 V. Figure 12 shows a high level block diagram of the SW1 regulator. PVIN1 PVIN1 SW1MODE ISENSE CINSW1 SW1 Controller LX1 Driver LSW1 COSW1 SW1FAULT EP I2C Internal Compensation FB1 I2C Interface Z2 Z1 VREF EA DAC Figure 12. SW1 Regulator Block Diagram 6.4.4.6 SW1 Setup and Control Registers SW1 output voltage is programmable from 0.625 to 1.875 V in steps of 25 mV. After power up in the default voltage, the output voltage can be changed in the Normal, Standby and Sleep mode by writing to the SW1[5:0], SW1STBY[5:0], and SW1OFF[5:0] respectively. Figure 30 shows the output voltage coding for these registers. Table 30. SW1 Output Voltage Configuration Set Point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 Output (V) Set Point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 Output (V) 13 001101 0.6250 39 100111 1.2750 14 001110 0.6500 40 101000 1.3000 15 001111 0.6750 41 101001 1.3250 16 010000 0.7000 42 101010 1.3500 17 010001 0.7250 43 101011 1.3750 18 010010 0.7500 44 101100 1.4000 19 010011 0.7750 45 101101 1.4250 20 010100 0.8000 46 101110 1.4500 21 010101 0.8250 47 101111 1.4750 34VR500 30 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 30. SW1 Output Voltage Configuration (continued) Set Point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 Output (V) Set Point SW1[5:0] SW1STBY[5:0] SW1OFF[5:0] SW1 Output (V) 22 010110 0.8500 48 110000 1.5000 23 010111 0.8750 49 110001 1.5250 24 011000 0.9000 50 110010 1.5500 25 011001 0.9250 51 110011 1.5750 26 011010 0.9500 52 110100 1.6000 27 011011 0.9750 53 110101 1.6250 28 011100 1.0000 54 110110 1.6500 29 011101 1.0250 55 110111 1.6750 30 011110 1.0500 56 111000 1.7000 31 011111 1.0750 57 111001 1.7250 32 100000 1.1000 58 111010 1.7500 33 100001 1.1250 59 111011 1.7750 34 100010 1.1500 60 111100 1.8000 35 100011 1.1750 61 111101 1.8250 36 100100 1.2000 62 111110 1.8500 37 100101 1.2250 63 111111 1.8750 38 100110 1.2500 Table 31 provides a list of registers used to configure and operate SW1 and a detailed description on each one of these register is provided in Table 31 through Table 36. Table 31. SW1 Register Summary Register Address Output SW1VOLT 0x2E SW1 Output voltage set point in normal operation SW1STBY 0x2F SW1 Output voltage set point in Standby SW1OFF 0x30 SW1 Output voltage set point in Sleep SW1MODE 0x31 SW1 Switching Mode selector register SW1CONF 0x32 SW1 DVS, Phase, Frequency and ILIM configuration Table 32. Register SW1VOLT - ADDR 0x2E Name Bit # R/W Default Description SW1 5:0 R/W 0x00 Sets the SW1 output voltage during normal operation mode. See Table 30 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED Table 33. Register SW1STBY - ADDR 0x2F Name Bit # R/W Default Description SW1STBY 5:0 R/W 0x00 Sets the SW1 output voltage during Standby mode. See Table 30 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 31 Functional Block Requirements and Behaviors Power Generation Table 34. Register SW1OFF - ADDR 0x30 Name Bit # R/W Default Description SW1OFF 5:0 R/W 0x00 Sets the SW1 output voltage during Sleep mode. See Table 30 for all possible configurations. UNUSED 7:6 - 0x00 UNUSED Table 35. Register SW1MODE - ADDR 0x31 Name Bit # R/W Default 3:0 R/W 0x80 Sets the SW1 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW1OMODE 5 R/W 0x00 Set status of SW1 when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW1MODE UNUSED Description Table 36. Register SW1CONF - ADDR 0x32 Name 6.4.4.7 Bit # R/W Default Description SW1ILIM 0 R/W 0x00 SW1 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW1FREQ 3:2 R/W 0x00 SW1 switching frequency selector. See Table 29. SW1PHASE 5:4 R/W 0x00 SW1 Phase clock selection. See Table 27. SW1DVSSPEED 7:6 R/W 0x00 SW1 DVS speed selection. See Table 26. SW1 External Components Table 37. SW1 External Component Recommendations Components Description Component CINSW1 (30) SW1input capacitor 3 x 4.7 F CIN1HF (30) SW1decoupling input capacitor 3 x 0.1 F COSW1(30) SW1 output capacitor 7 x 22 F LSW1 SW1 inductor 0.68 H, DCR = 10 mISAT = 9.0 A Notes 30. Use X5R or X7R capacitors. 34VR500 32 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4.8 SW1 Specifications Table 38. SW1 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch Mode Supply SW1 VPVIN1 Operating Input Voltage 2.8 - 4.5 V VSW1 Nominal Output Voltage - Table 30 - V -25 -3.0 - - 25 3.0 mV % -65 -45 -3.0 - - - 65 45 3.0 mV mV % - - 4500 mA 7.1 5.3 10.5 7.9 13.7 10.3 A Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1 < 4.5 A VSW1ACC ISW1 ISW1LIM 0.625 V VSW1 1.450 V 1.475 V VSW1 1.875 V * PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1 < 150 mA 0.625 V < VSW1 < 0.675 V 0.7 V < VSW1 < 0.85 V 0.875 V < VSW1 < 1.875 V Rated Output Load Current, 2.8 V < VIN < 4.5 V, 0.625 V < VSW1 < 1.875 V Current Limiter Peak Current Detection * Current through Inductor SW1ILIM = 0 SW1ILIM = 1 VSW1 Start-up Overshoot ISW1 = 0 mA DVS clk = 25 mV/4 s, VIN = VPVIN1 = 4.5 V, VSW1 = 1.875 V - - 66 mV tONSW1 Turn-on Time, Enable to 90% of end value ISW1 = 0 mA, DVS clk = 25 mV/4.0 s, VIN = VPVIN1 = 4.5 V, VSW1 = 1.875 V - - 500 s - - - 1.0 2.0 4.0 - - - - - - - - - 77 82 86 84 80 68 - - - - - - Output Ripple - 5.0 - mV VSW1LIR Line Regulation (APS, PWM) - - 20 mV VSW1LOR DC Load Regulation (APS, PWM) - - 20 mV VSW1LOTR Transient Load Regulation * Transient load = 0 to 2.25 A, di/dt = 100 mA/s Overshoot Undershoot - - - - 50 50 fSW1 Switching Frequency SW1FREQ[1:0] = 00 SW1FREQ[1:0] = 01 SW1FREQ[1:0] = 10 MHz Efficiency * VIN = 3.6 V, fSW1 = 2.0 MHz, LSW1 = 1.0 H SW1 VSW1 PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 850 mA APS, PWM, 1.2 V, 1275 mA APS, PWM, 1.2 V, 2125 mA APS, PWM, 1.2 V, 4500 mA % mV 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 33 Functional Block Requirements and Behaviors Power Generation Table 38. SW1 Electrical Characteristics (continued) All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Quiescent Current PFM Mode APS Mode - - 18 145 - - A RSW1DIS Discharge Resistance - 600 - RONSW1P SW1 P-MOSFET RDS(on) VPVIN1 = 3.3 V - 60 77 m RONSW1N SW1 N-MOSFET RDS(on) VPVIN1 = 3.3 V - 80 101 m Notes Switch Mode Supply SW1 (continued) Efficiency (%) ISW1Q 100 90 80 70 60 50 40 30 20 10 0 2MHz, 1.8V, PWM 1MHz, 1.8V, PWM 100 1000 Load Current (mA) 10000 SW1 Efficiency Waveform: VIN = 3.3 V; VOUT = 1.8 V SW1 Efficiency Waveform: VIN = 3.6 V; VOUT = 1.2 V SW1 Efficiency Waveform: VIN = 3.6 V; VOUT = 1.2 V Figure 13. SW1 Efficiency Waveforms 34VR500 34 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Figure 14. Load tRansient Response - SW1 (APS) 6.4.4.9 SW2 SW2 is a 2.0 A rated buck regulator. Table 23 describes the modes, and Table 24 show the options for the SWxMODE[3:0] bits. Figure 15 shows the block diagram and the external component connections for SW2 regulator. PVIN2 PVIN2 SW2 LX2 LSW2 COSW2 SW2MODE ISENSE CINSW2 Controller Driver SW2FAULT EP Internal Compensation FB2 I2C Interface I2C Z2 Z1 EA VREF DAC Figure 15. SW2 Block Diagram 6.4.4.10 SW2 Setup and Control Registers SW2 output voltage is programmable from 0.625 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW2[5:0], SW2STBY[5:0] and SW2OFF[5:0] bits, respectively. Table 39 shows the output voltage coding valid for SW2. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 35 Functional Block Requirements and Behaviors Power Generation Table 39. SW2 Output Voltage Configuration Set Point SW2[5:0] SW2 Output Set Point SW2[5:0] SW2 Output 9 001001 0.6250 37 100101 1.3250 10 001010 0.6500 38 100110 1.3500 11 001011 0.6750 39 100111 1.3750 12 001100 0.7000 40 101000 1.4000 13 001101 0.7250 41 101001 1.4250 14 001110 0.7500 42 101010 1.4500 15 001111 0.7750 43 101011 1.4750 16 010000 0.8000 44 101100 1.5000 17 010001 0.8250 45 101101 1.5250 18 010010 0.8500 46 101110 1.5500 19 010011 0.8750 47 101111 1.5750 20 010100 0.9000 48 110000 1.6000 21 010101 0.9250 49 110001 1.6250 22 010110 0.9500 50 110010 1.6500 23 010111 0.9750 51 110011 1.6750 24 011000 1.0000 52 110100 1.7000 25 011001 1.0250 53 110101 1.7250 26 011010 1.0500 54 110110 1.7500 27 011011 1.0750 55 110111 1.7750 28 011100 1.1000 56 111000 1.8000 29 011101 1.1250 57 111001 1.8250 30 011110 1.1500 58 111010 1.8500 31 011111 1.1750 59 111011 1.8750 32 100000 1.2000 60 111100 1.9000 33 100001 1.2250 61 111101 1.9250 34 100010 1.2500 62 111110 1.9500 35 100011 1.2750 63 111111 1.9750 36 100100 1.3000 Setup and control of SW2 is done through I2C registers listed in Table 40, and a detailed description of each one of the registers is provided in Tables 41 to Table 45. Table 40. SW2 Register Summary Register Address Description SW2VOLT 0x35 Output voltage set point on normal operation SW2STBY 0x36 Output voltage set point on Standby SW2OFF 0x37 Output voltage set point on Sleep SW2MODE 0x38 Switching Mode selector register SW2CONF 0x39 DVS, Phase, Frequency, and ILIM configuration 34VR500 36 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 41. Register SW2VOLT - ADDR 0x35 Name SW2 Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW2 output voltage during normal operation mode. See Table 39 for all possible configurations. Table 42. Register SW2STBY - ADDR 0x36 Name SW2STBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 39 for all possible configurations. Table 43. Register SW2OFF - ADDR 0x37 Name SW2OFF Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW2 output voltage during Sleep mode. See Table 39 for all possible configurations. Table 44. Register SW2MODE - ADDR 0x38 Name Bit # R/W Default 3:0 R/W 0x80 Sets the SW2 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW2OMODE 5 R/W 0x00 Set status of SW2 when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW2MODE UNUSED Description Table 45. Register SW2CONF - ADDR 0x39 Name Bit # R/W Default Description SW2ILIM 0 R/W 0x00 SW2 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. See Table 29. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. See Table 27. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. See Table 28. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 37 Functional Block Requirements and Behaviors Power Generation 6.4.4.11 SW2 External Components Table 46. SW2 External Component Recommendations Components Description Values CINSW2(31) SW2 Input capacitor 4.7 F CIN2HF(31) SW2 Decoupling input capacitor 0.1 F COSW2(31) SW2 Output capacitor LSW2 SW2 Inductor 3 x 22 F 1.5 H DCR = 50 m ISAT = 2.6 A Notes 31. Use X5R or X7R capacitors. 6.4.4.12 SW2 Specifications Table 47. SW2 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch Mode Supply SW2 VPVIN2 Operating Input Voltage 2.8 - 4.5 V VSW2 Nominal Output Voltage - Table 39 - V -45 -3.0 - - 45 3.0 mV % -65 -45 -45 - - - 65 45 45 mV mV mV - - 2000 mA 2.8 2.1 4.0 3.0 5.2 3.9 A Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 1.0 A VSW2ACC ISW2 ISW2LIM 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V * PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 50 mA 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 1.975 V Current Limiter Peak Current Detection * Current through Inductor SW2ILIM = 0 SW2ILIM = 1 VSW2OSH Start-up Overshoot ISW2 = 0.0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN2 = 4.5 V - - 66 mV tONSW2 Turn-ON Time, Enable to 90% of end value ISW2 = 0.0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN2 = 4.5 V - - 500 s - - - 1.0 2.0 4.0 - - - fSW2 Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 MHz 34VR500 38 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 47. SW2 Electrical Characteristics (continued) All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN2 = 3.6 V, ISW2 = 100 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit - 77 - - - - 68 68 76 - - - Output Ripple - 5.0 - mV VSW2LIR Line Regulation (APS, PWM) - - 20 mV VSW2LOR DC Load Regulation (APS, PWM) - - 20 mV VSW2LOTR Transient Load Regulation * Transient load = 0.0 mA to 0.5 A, di/dt = 100 mA/s Overshoot Undershoot - - - - 50 50 Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) - - - 23 145 305 - - - Notes Switch Mode Supply SW2 (Continued) Efficiency * VIN = 2.8V, fSW2 = 2.0 MHz, LSW2 = 1.0 H SW2 VSW2 ISW2Q * APS, PWM, 1.0 V, 1000 mA VIN = 4.5V, fSW2 = 2.0 MHz, LSW2 = 1.0 H PFM, 1.0 V, 50 mA APS, 1.0 V, 1.0 mA APS, 1.0 V, 1000 mA % mV A Switch Mode Supply SW2 (Continued) RONSW2P SW2 P-MOSFET RDS(on) at VIN = VPVIN2 = 3.3 V - 190 209 m RONSW2N SW2 N-MOSFET RDS(on) at VIN = VPVIN2 = 3.3 V - 212 255 m RSW2DIS Discharge Resistance - 600 - SW2 Efficiency Waveform: VIN = 3.6V; VOUT = 3.15V SW2 Efficiency Waveform: VIN = 3.6V; VOUT = 1.8V Figure 16. SW2 Efficiency Waveforms 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 39 Functional Block Requirements and Behaviors Power Generation Figure 17. Load Transient Response - SW2 (PWM) 6.4.4.13 SW3 SW3 is a 2.5 A regulator capable of providing an output from 0.625 V to 1.975 V. Figure 18 shows a high level block diagram of the SW3 regulator. PVIN3 PVIN3 CINSW3 SW3 LX3 LSW3 COSW3 SW3MODE ISENSE Controller Driver SW3FAULT EP Internal Compensation FB3 I2C Interface I2C Z2 Z1 EA VREF DAC Figure 18. SW3 Regulator Block Diagram 34VR500 40 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4.14 SW3 Setup and Control Registers SW3 output voltage is programmable from 0.625 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW3[5:0], SW3STBY[5:0], and SW3OFF[5:0] bits respectively. Table 48 shows the output voltage coding valid for SW3. Table 48. SW3 Output Voltage Configuration Set Point SW3[5:0] SW3 Output Set Point SW3[5:0] SW3 Output 9 001001 0.6250 37 100101 1.3250 10 001010 0.6500 38 100110 1.3500 11 001011 0.6750 39 100111 1.3750 12 001100 0.7000 40 101000 1.4000 13 001101 0.7250 41 101001 1.4250 14 001110 0.7500 42 101010 1.4500 15 001111 0.7750 43 101011 1.4750 16 010000 0.8000 44 101100 1.5000 17 010001 0.8250 45 101101 1.5250 18 010010 0.8500 46 101110 1.5500 19 010011 0.8750 47 101111 1.5750 20 010100 0.9000 48 110000 1.6000 21 010101 0.9250 49 110001 1.6250 22 010110 0.9500 50 110010 1.6500 23 010111 0.9750 51 110011 1.6750 24 011000 1.0000 52 110100 1.7000 25 011001 1.0250 53 110101 1.7250 26 011010 1.0500 54 110110 1.7500 27 011011 1.0750 55 110111 1.7750 28 011100 1.1000 56 111000 1.8000 29 011101 1.1250 57 111001 1.8250 30 011110 1.1500 58 111010 1.8500 31 011111 1.1750 59 111011 1.8750 32 100000 1.2000 60 111100 1.9000 33 100001 1.2250 61 111101 1.9250 34 100010 1.2500 62 111110 1.9500 35 100011 1.2750 63 111111 1.9750 36 100100 1.3000 Table 49 provides a list of registers used to configure and operate SW3. A detailed description on each of these register is provided on Tables 49 through Table 54. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 41 Functional Block Requirements and Behaviors Power Generation Table 49. SW3 Register Summary Register Address Output SW3VOLT 0x3C SW3 Output voltage set point on normal operation SW3STBY 0x3D SW3 Output voltage set point on Standby SW3OFF 0x3E SW3 Output voltage set point on Sleep SW3MODE 0x3F SW3 Switching mode selector register SW3CONF 0x40 SW3 DVS, phase, frequency and ILIM configuration Table 50. Register SW3VOLT - ADDR 0x3C Name SW3 Bit # R/W Default 5:0 R/W 0x00 Description Sets the SW3 output voltage, during normal operation mode. See Table 48 for all possible configurations. Table 51. Register SW3STBY - ADDR 0x3D Name SW3STBY Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW3 output voltage, during Standby mode. See Table 48 for all possible configurations. Table 52. Register SW3OFF - ADDR 0x3E Name SW3OFF Bit # R/W Default 5:0 R/W 0x00 Description Sets the SW3 output voltage during Sleep mode. See Table 48 for all possible configurations. Table 53. Register SW3MODE - ADDR 0x3F Name Bit # R/W Default 3:0 R/W 0x80 Sets the SW3 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW3OMODE 5 R/W 0x00 Set status of SW3 when in Sleep mode. 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW3MODE UNUSED Description Table 54. Register SW3CONF - ADDR 0x40 Name Bit # R/W Default Description SW3ILIM 0 R/W 0x00 SW3 current limit level selection 0 = High level current limit 1 = Low level current limit UNUSED 1 R/W 0x00 Unused SW3FREQ 3:2 R/W 0x00 SW3 switching frequency selector. See Table 29. SW3PHASE 5:4 R/W 0x00 SW3 Phase clock selection. See Table 27. SW3DVSSPEED 7:6 R/W 0x00 SW3 DVS speed selection. See Table 28. 34VR500 42 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.4.15 SW3 External Components Table 55. SW3 External Component Requirements Components CINSW3 (32) Description SW3 SW3 input capacitor 2 x 4.7 F COSW3 (32) SW3 output capacitor 3 x 22 F CIN3HF (32) SW3 decoupling input capacitor 2 x 0.1 F LSW3 1.5 H DCR = 25 m ISAT = 5.0 A SW3 inductor Notes 32. Use X5R or X7R capacitors. 6.4.4.16 SW3 Specifications Table 56. SW3 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit Notes Switch Mode Supply SW3 VPVIN3 Operating Input Voltage 2.8 - 4.5 V VSW3 Nominal Output Voltage - Table 48 - V -25 -3.0 - - 25 3.0 mV % -65 -45 -45 - - - 65 45 45 mV mV mV - - 2500 3.5 2.7 5.0 3.8 6.5 4.9 Start-up Overshoot ISW3 = 0.0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN3 = 4.5 V - - 66 mV Turn-on Time Enable to 90% of end value ISW3 = 0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN3 = 4.5 V - - 500 s - - - 1.0 2.0 4.0 - - - Output Voltage Accuracy * PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3 < 2.5 A VSW3ACC ISW3 ISW3LIM VSW3OSH tONSW3 fSW3 * 0.625 V < VSW3 < 0.85 V 0.875 V < VSW3 < 1.975 V PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3 < 50 mA) 0.625 V < VSW3 < 0.675 V 0.7 V < VSW3 < 0.85 V 0.875 V < VSW3 < 1.975 V Rated Output Load Current * 2.8 V < VIN < 4.5 V, 0.625 V < VSW3 < 1.975 V PWM, APS mode Current Limiter Peak Current Detection * Current through inductor SW3ILIM = 0 SW3ILIM = 1 Switching Frequency SW3FREQ[1:0] = 00 SW3FREQ[1:0] = 01 SW3FREQ[1:0] = 10 mA A MHz 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 43 Functional Block Requirements and Behaviors Power Generation Table 56. SW3 Electrical Characteristics (continued) All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 C, unless otherwise noted. Parameter Symbol Min. Typ. Max. Unit - - - - - - 84 85 85 84 80 74 - - - - - - Output Ripple - 5.0 - mV VSW3LIR Line Regulation (APS, PWM) - - 20 mV VSW3LOR DC Load Regulation (APS, PWM) - - 20 mV VSW3LOTR Transient Load Regulation * Transient Load = 0.0 mA to 1.25 A, di/dt = 100 mA/s Overshoot Undershoot - - - - 50 50 Quiescent Current PFM Mode APS Mode - - 22 300 - - 108 123 129 163 600 - Notes Switch Mode Supply SW3 (Continued) Efficiency * fSW3 = 2.0 MHz, LSW3 1.0 H SW3 VSW3 ISW3Q PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA RONSW3P SW3 P-MOSFET RDSON at VIN = VPVIN3 = 3.3 V - RONSW3N SW3 N-MOSFET RDSON at VIN = VPVIN3 = 3.3 V - RSW3DIS Discharge Resistance - % mV A m m 100 90 80 PFM Vout = 1.5V 20 APS Vout = 1.5V Efficiency (%) 70 ) % ( 60 yc n 50 ie ci ff 40 E 30 10 PWM Vout = 1.5V 0 0.1 1 10 100 1000 Load Current (mA) Figure 19. SW3 Efficiency Waveforms 34VR500 44 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Figure 20. Load Transient Response - SW3 (PWM) 6.4.4.17 SW4 SW4 operates by default in VTT mode (for the 34VR500V1, V3, V4, V5) and it's not possible to change this configuration and modify the output voltage after the Start-up sequence. SW4 operates in non VTT mode for the 34VR500V2, and it is possible to change the output voltage by the I2C bus. SW4 is a 1.0 A rated buck regulator capable of operating in two modes. In Regulator mode, it operates as a normal buck regulator with a programmable output between 0.625 and 1.975 V. It is capable of operating in the three available switching modes: PFM, APS, and PWM, described on Table 23 and configured by the SW4MODE[3:0] bits, as shown in Table 24. If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage will track the output voltage of SW3, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The minimum output voltage for SW4 in VTT mode is 0.6 V Figure 21 shows the block diagram and the external component connections for the SW4 regulator. PVIN4 PVIN4 CINSW4 SW4 LX4 LSW4 COSW4 SW4MODE ISENSE Controller Driver SW4FAULT EP Internal Compensation FB4 I2C Interface I2C Z2 Z1 EA VREF DAC Figure 21. SW4 Block Diagram 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 45 Functional Block Requirements and Behaviors Power Generation 6.4.4.18 SW4 Setup and Control Registers In Regulator mode, the SW4 output voltage is programmable from 0.625 to 1.975 V. The output voltage set point is independently programmed for Normal, Standby, and Sleep mode by setting the SW4[5:0], SW4STBY[5:0], and SW4OFF[5:0] bits, respectively. Table 57 shows the output voltage coding valid for SW4. Table 57. SW4 Output Voltage Configuration Set Point SW4[5:0] SW4 Output Set Point SW4[5:0] SW4 Output 9 001001 0.6250 37 100101 1.3250 10 001010 0.6500 38 100110 1.3500 11 001011 0.6750 39 100111 1.3750 12 001100 0.7000 40 101000 1.4000 13 001101 0.7250 41 101001 1.4250 14 001110 0.7500 42 101010 1.4500 15 001111 0.7750 43 101011 1.4750 16 010000 0.8000 44 101100 1.5000 17 010001 0.8250 45 101101 1.5250 18 010010 0.8500 46 101110 1.5500 19 010011 0.8750 47 101111 1.5750 20 010100 0.9000 48 110000 1.6000 21 010101 0.9250 49 110001 1.6250 22 010110 0.9500 50 110010 1.6500 23 010111 0.9750 51 110011 1.6750 24 011000 1.0000 52 110100 1.7000 25 011001 1.0250 53 110101 1.7250 26 011010 1.0500 54 110110 1.7500 27 011011 1.0750 55 110111 1.7750 28 011100 1.1000 56 111000 1.8000 29 011101 1.1250 57 111001 1.8250 30 011110 1.1500 58 111010 1.8500 31 011111 1.1750 59 111011 1.8750 32 100000 1.2000 60 111100 1.9000 33 100001 1.2250 61 111101 1.9250 34 100010 1.2500 62 111110 1.9500 35 100011 1.2750 63 111111 1.9750 36 100100 1.3000 Full setup and control of SW4 is done through the I2C registers listed on Table 58, and a detailed description of each one of the registers is provided in Tables 59 to Table 63. 34VR500 46 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 58. SW4 Register Summary Register Address Description SW4VOLT 0x4A Output voltage set point on normal operation SW4STBY 0x4B Output voltage set point on Standby SW4OFF 0x4C Output voltage set point on Sleep SW4MODE 0x4D Switching mode selector register SW4CONF 0x4E DVS, phase, frequency and ILIM configuration Table 59. Register SW4VOLT - ADDR 0x4A Name SW4 UNUSED Bit # R/W Default Description 5:0 R/W 0x00 Sets the SW4 output voltage during normal operation mode. See Table 57 for all possible configurations. 7 - 0x00 UNUSED Table 60. Register SW4STBY - ADDR 0x4B Name Bit # R/W Default Description SW4STBY 5:0 R/W 0x00 Sets the SW4 output voltage during Standby mode. See Table 57 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 61. Register SW4OFF - ADDR 0x4C Name Bit # R/W Default Description SW4OFF 5:0 R/W 0x00 Sets the SW4 output voltage during Sleep mode. See Table 57 for all possible configurations. UNUSED 7 - 0x00 UNUSED Table 62. Register SW4MODE - ADDR 0x4D Name Bit # R/W Default 3:0 R/W 0x80 Sets the SW4 switching operation mode. See Table 23 for all possible configurations. UNUSED 4 - 0x00 UNUSED SW4OMODE 5 R/W 0x00 Set status of SW4 when in Sleep mode 0 = OFF 1 = PFM 7:6 - 0x00 UNUSED SW4MODE UNUSED Description 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 47 Functional Block Requirements and Behaviors Power Generation Table 63. Register SW4CONF - ADDR 0x4E Name Bit # R/W Default SW4ILIM 0 R/W 0x00 SW4 current limit level selection 0 = High level Current limit 1 = Low level Current limit UNUSED 1 R/W 0x00 Unused SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 29. SW4PHASE 5:4 R/W 0x00 SW4 Phase clock selection. See Table 27. SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 28. 6.4.4.19 Description SW4 External Components Table 64. SW4 External Component Recommendations Components Description Values CINSW4(33) SW4 Input capacitor 4.7 F CIN4HF(33) SW4 Decoupling input capacitor 0.1 F COSW4(33) SW4 Output capacitor LSW4 SW4 Inductor 3 x 22 F 1.5 H DCR = 50 m ISAT = 2.6 A Notes 33. Use X5R or X7R capacitors. 6.4.4.20 SW4 Specifications Table 65. SW4 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW4 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes Switch Mode Supply SW4 VPVIN4 Operating Input Voltage 2.8 - 4.5 V VSW4 Nominal Output Voltage Normal operation VTT Mode - - Table 57 VSW3/2 - - V -25 -3.0 - - 25 3.0 mV % PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA 0.625 V < VSW4 < 0.675 V 0.7 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V -65 -45 -45 - - - 65 45 45 mV mV mV VTT Mode, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A -40 - 40 mV - - 1000 mA Output Voltage Accuracy * PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A 0.625 V < VSW4 < 0.85 V 0.875 V < VSW4 < 1.975 V VSW4ACC * * ISW4 Rated Output Load Current 2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 1.975 V 34VR500 48 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 65. SW4 Electrical Characteristics (continued) All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, VVBIAS = 1.0 V 4.0%, typical external component values, fSW4 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. 1.4 1.0 2.0 1.5 3.0 2.4 Unit Notes Switch Mode Supply SW4 (CONTINUED) ISW4LIM Current Limiter Peak Current Detection Current through inductor SW4ILIM = 0 SW4ILIM = 1 A VSW4OSH Start-up Overshoot ISW4 = 0.0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN4 = 4.5 V - - 66 mV tONSW4 Turn-on Time Enable to 90% of end value ISW4 = 0.0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN4 = 4.5 V - - 500 s - - - 1.0 2.0 4.0 - - - PFM, 1.8 V, 1.0 mA PFM, 1.8 V, 50 mA APS, PWM 1.8 V, 200 mA APS, PWM 1.8 V, 500 mA APS, PWM 1.8 V, 1000 mA - - - - - 81 78 87 88 83 - - - - - PWM 0.75 V, 200 mA PWM 0.75 V, 500 mA PWM 0.75 V, 1000 mA - - - 78 76 66 - - - Output Ripple - 5.0 - mV VSW4LIR Line Regulation (APS, PWM) - - 20 mV VSW4LOR DC Load Regulation (APS, PWM) - - 20 mV VSW4LOTR Transient Load Regulation * Transient Load = 0.0 mA to 500 mA, di/dt = 100 mA/s Overshoot Undershoot - - - - - - 22 145 - - A fSW4 Switching Frequency SW4FREQ[1:0] = 00 SW4FREQ[1:0] = 01 SW4FREQ[1:0] = 10 MHz Efficiency * fSW4 = 2.0 MHz, LSW4 = 1.0 H SW4 VSW4 ISW4Q Quiescent Current PFM Mode APS Mode 50 50 % mV RONSW4P SW4 P-MOSFET RDSON at VIN = VPVIN4 = 3.3 V - 236 274 m RONSW4N SW4 N-MOSFET RDSON at VIN = VPVIN4 = 3.3 V - 293 378 m RSW4DIS Discharge Resistance - 600 - 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 49 Functional Block Requirements and Behaviors Power Generation 100 90 Efficiency (%) 80 70 ) % ( 60 yc n 50 ie ci ff 40 E 30 PFM Vout = 1.8V APS Vout = 1.8V 20 PWM Vout = 1.8 V 10 PWM Vout = 0.7 5V 0 0.1 1 10 100 1000 Load Current (mA) Figure 22. SW4 Efficiency Waveforms Figure 23. Load Transient Response - SW4 (PWM) 6.4.5 LDO Regulators Description This section describes the LDO regulators provided by the 34VR500. All regulators use the main bandgap as reference. Refer to Bias and References Block Description section for further information on the internal reference voltages. A Low Power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest bias currents may be attained by forcing the part into its Low Power mode by setting the LDOxLPWR bit. The use of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is disabled, the output will be discharged by an internal pull-down. The pull-down is also activated when PORB is low. 34VR500 50 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation VLDOINx VLDOINx VREF _ + LDOx LDOxLPWR LDOx LDOx I2C Interface CLDOx LDOx Discharge Figure 24. General LDO Block Diagram 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 51 Functional Block Requirements and Behaviors Power Generation 6.4.5.1 Transient Response Waveforms Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 25. Note that the transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. IMAX ILOAD IMAX/10 1.0 us 1.0 us Transient Load Stimulus IL = IMAX/10 IL = IMAX Overshoot VOUT Undershoot VOUT Transient Load Response VINx_INITIAL VINx VINx_FINAL 10 us 10 us Transient Line Stimulus VINx_INITIAL VINx_FINAL Overshoot VOUT Undershoot VOUT Transient Line Response Figure 25. Transient Waveforms 34VR500 52 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation 6.4.5.2 Short-circuit Protection All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its LDOxEN bit, while at the same time, an interrupt LDOxFAULTI will be generated to flag the fault to the system processor. The LDOxFAULTI interrupt is maskable through the LDOxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators will not automatically be disabled upon a short-circuit detection. However, the current limiter will continue to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, LDOxFAULTI, will be generated in an overload condition regardless of the state of the REGSCPEN bit. See Table 66 for SCP behavior configuration. Table 66. Short-circuit Behavior 6.4.5.3 REGSCPEN[0] Short-circuit Behavior 0 Current limit 1 Shutdown LDO Regulator Control Each LDO is fully controlled through its respective LDOxCTL register. This register enables the user to set the LDO output voltage according to Table 67 for LDO1 and uses the voltage set point on Table 68 for LDO2 through LDO5. Table 67. LDO1 Output Voltage Configuration Set Point LDO1[3:0] LDO1 Output (V) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 53 Functional Block Requirements and Behaviors Power Generation Table 68. LDO2/3/4/5 Output Voltage Configuration Set Point LDOx[3:0] LDOx Output (V) 0 0000 1.80 1 0001 1.90 2 0010 2.00 3 0011 2.10 4 0100 2.20 5 0101 2.30 6 0110 2.40 7 0111 2.50 8 1000 2.60 9 1001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as programmed to stay "ON" or be disabled when the PMIC enters Standby mode. Each regulator has associated I2C bits for this. Table 69 presents a summary of all valid combinations of the control bits on LDOxCTL register and the expected behavior of the LDO output. Table 69. LDO Control LDOxEN LDOxLPWR LDOxSTBY STANDBY(34) LDOxOUT 0 X X X Off 1 0 0 X On 1 1 0 X Low Power 1 X 1 0 On 1 0 1 1 Off 1 1 1 1 Low Power Notes 34. STANDBY refers to a Standby event as described earlier. For more detail information, Table 70 through Table 74 provide a description of all registers necessary to operate all five general purpose LDO regulators. Table 70. Register LDO1CTL - ADDR 0x6D Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO1 output voltage. See Table 67 for all possible configurations. LDO1EN 4 - 0x00 Enables or Disables LDO1 output 0 = OFF 1 = ON LDO1STBY 5 R/W 0x00 Set LDO1 output state when in Standby. Refer to Table 69. LDO1 Description 34VR500 54 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 70. Register LDO1CTL - ADDR 0x6D Name Bit # R/W Default Description LDO1LPWR 6 R/W 0x00 Enable Low Power Mode for LDO1. Refer to Table 69. UNUSED 7 - 0x00 UNUSED Table 71. Register LDO2CTL - ADDR 0x6E Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO2 output voltage. See Table 68 for all possible configurations. LDO2EN 4 - 0x00 Enables or Disables LDO2 output 0 = OFF 1 = ON LDO2STBY 5 R/W 0x00 Set LDO2 output state when in Standby. Refer to Table 69. LDO2LPWR 6 R/W 0x00 Enable Low Power Mode for LDO2. Refer to Table 69. UNUSED 7 - 0x00 UNUSED LDO2 Description Table 72. Register LDO3CTL - ADDR 0x6F Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO3 output voltage. See Table 68 for all possible configurations. LDO3EN 4 - 0x00 Enables or Disables LDO3 output 0 = OFF 1 = ON LDO3STBY 5 R/W 0x00 Set LDO3 output state when in Standby. Refer to Table 69. LDO3LPWR 6 R/W 0x00 Enable Low Power Mode for LDO3. Refer to Table 69. UNUSED 7 - 0x00 UNUSED LDO3 Description Table 73. Register LDO4CTL - ADDR 0x70 Name Bit # R/W Default 3:0 R/W 0x80 Sets LDO4 output voltage. See Table 68 for all possible configurations. LDO4EN 4 - 0x00 Enables or Disables LDO4 output 0 = OFF 1 = ON LDO4STBY 5 R/W 0x00 Set LDO4 output state when in Standby. Refer to Table 69. LDO4LPWR 6 R/W 0x00 Enable Low Power Mode for LDO4. Refer to Table 69. UNUSED 7 - 0x00 UNUSED LDO4 Description Table 74. Register LDO5CTL - ADDR 0x71 Name Bit # R/W Default Description 3:0 R/W 0x80 Sets LDO5 output voltage. See Table 68 for all possible configurations. LDO5EN 4 - 0x00 Enables or Disables LDO5 output 0 = OFF 1 = ON LDO5STBY 5 R/W 0x00 Set LDO5 output state when in Standby. Refer to Table 69. LDO5LPWR 6 R/W 0x00 Enable Low Power Mode for LDO5. Refer to Table 69. UNUSED 7 - 0x00 UNUSED LDO5 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 55 Functional Block Requirements and Behaviors Power Generation 6.4.5.4 External Components Table 75 lists the typical component values for the general purpose LDO regulators. Table 75. LDO External Components Regulator Output Capacitor (F)(35) LDO1 4.7 LDO2 2.2 LDO3 4.7 LDO4 2.2 LDO5 2.2 Notes 35. Use X5R/X7R ceramic capacitors. 6.4.5.5 6.4.5.5.1 LDO Specifications LDO1 Table 76. LDO1 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN1 = 3.0 V, VLDO1[3:0] = 1111, ILDO1 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN1 = 3.0 V, LDO1[3:0] = 1111, ILDO1 = 10 mA and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes LDO1 VLDOIN1 Operating Input Voltage 1.75 - 3.40 V LDO1NOM Nominal Output Voltage - Table 67 - V ILDO1 Operating Load Current 0.0 - 250 mA -3.0 - 3.0 % LDO1 Active Mode - DC VLDO1TOL Output Voltage Tolerance 1.75 V <VLDOIN1 < 3.4 V, 0.0 mA < ILDO1 < 250 mA LDO1[3:0] = 0000 to 1111 VLDO1LOR Load Regulation (VLDO1 at ILDO1 = 250 mA) - (VLDO1 at ILDO2 = 0.0 mA) For any 1.75 V <VLDOIN1 < 3.4 V - 0.05 - mV/mA VLDO1LIR Line Regulation (VLDO1 at VLDOIN1 = 3.4 V) - (VLDO1 at VLDOIN1 = 1.75 V) For any 0.0 mA < ILDO1 < 250 mA - 0.50 - mV/V ILDO1LIM Current Limit ILDO1 when LDO1 is forced to LDO1NOM/2 305 417 510 ILDO1OCP Overcurrent Protection Threshold ILDO1 required to cause the SCP function to disable LDO when REGSCPEN = 1 290 - 500 - 16 - ILDO1Q Quiescent Current No load, Change in IVIN and IVLDOIN1 When LDO1 enabled mA mA A 34VR500 56 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 76. LDO1 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN1 = 3.0 V, VLDO1[3:0] = 1111, ILDO1 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN1 = 3.0 V, LDO1[3:0] = 1111, ILDO1 = 10 mA and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. 50 37 60 45 - - - - - -108 -118 -124 -100 -108 -112 - - - - 12.5 16.5 Unit Notes dB (36) LDO1 AC AND tRANSIENT PSRRLDO1 PSRR * ILDO1 = 187.5 mA, 20 Hz to 20 kHz LDO1[3:0] = 0000 - 1101 LDO1[3:0] = 1110, 1111 Output Noise Density * VLDOIN1 = 1.75 V, ILDO1 = 187.5 mA NOISELDO1 SLWRLDO1 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-On Slew Rate * 10% to 90% of end value * 1.75 V VLDOIN1 3.4 V, ILDO1 = 0.0 mA LDO1[3:0] = 0000 to 0111 LDO1[3:0] = 1000 to 1111 dBV/Hz mVs tONLDO1 Turn-On Time Enable to 90% of end value, VLDOIN1 = 1.75 V, 3.4 V ILDO1 = 0.0 mA 60 - 500 s tOFFLDO1 Turn-Off Time Disable to 10% of initial value, VLDOIN1 = 1.75 V ILDO1 = 0.0 mA - - 10 ms LDO1OSHT Start-up Overshoot VLDOIN1 = 1.75 V, 3.4 V, ILDO1 = 0.0 mA - 1.0 2.0 % VLDO1LOTR Transient Load Response VLDOIN1 = 1.75 V, 3.4 V ILDO1 = 25 to 250 mA in 1.0 s Peak of overshoot or undershoot of LDO1 with respect to final value Refer to Figure 25 - - 3.0 % VLDO1LITR Transient Line Response ILDO1 = 187.5 mA VLDOIN1INITIAL = 1.75 V to VLDOIN1 = 2.25 V for LDO1[3:0] = 0000 to 1101 VLDOIN1INITIAL = VLDO1+0.3 V to VLDOIN1FINAL = VLDO1+0.8 V for LDO1[3:0] = 1110, 1111 Refer to Figure 25 - 5.0 8.0 mV Notes 36. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 57 Functional Block Requirements and Behaviors Power Generation 6.4.5.5.2 LDO2 Table 77. LDO2 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN23 = 3.6 V, VLDO2[3:0] = 1111, ILDO2 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN23 = 3.6 V, LDO2[3:0] = 1111, ILDO2 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes 2.8 LDO2NOM+ 0.250 - - 3.6 3.6 V (37) LDO2 VLDOIN23 Operating Input Voltage 1.8 V LDO2NOM 2.5 V 2.6 V LDO2NOM 3.3 V LDO2NOM Nominal Output Voltage - Table 68 - V ILDO2 Operating Load Current 0.0 - 100 mA VLDO2TOL Output Voltage Tolerance VLDOIN23MIN < VLDOIN23 < 3.6 V 0.0 mA < ILDO2 < 100 mA LDO2[3:0] = 0000 to 1111 -3.0 - 3.0 % VLDO2LOR Load Regulation (VLDO2 at ILDO2 = 100 mA) - (VLDO2 at ILDO2 = 0.0 mA) For any VLDOIN23MIN < VLDOIN23 < 3.6 V - 0.07 - mV/mA VLDO2LIR Line Regulation (VLDO2 at VLDOIN23 = 3.6 V) - (VLDO2 at VLDOIN23MIN) For any 0.0 mA < ILDO2 < 100 mA - 0.8 - mV/V ILDO2LIM Current Limit ILDO2 when LDO2 is forced to LDO2NOM/2 127 167 200 mA ILDO2OCP Overcurrent Protection Threshold ILDO2 required to cause the SCP function to disable LDO when REGSCPEN = 1 120 - 200 mA - 13 - A 35 55 40 60 - - - - - -114 -129 -135 -102 -123 -130 dBV/Hz - - - - - - - - 22.0 26.5 30.5 34.5 mVs LDO2 DC ILDO2Q Quiescent Current No load, Change in IVIN and IVLDOIN23 When LDO2 enabled LDO2 AC AND tRANSIENT PSRRLDO2 PSRR * ILDO2 = 75 mA, 20 Hz to 20 kHz LDO2[3:0] = 0000 - 1110, VLDOIN23 = VLDOIN23MIN + 100 mV LDO2[3:0] = 0000 - 1000, VLDOIN23 = LDO2NOM + 1.0 V dB (38) Output Noise Density * VLDOIN23 = VLDOIN23MIN, ILDO2 = 75 mA NOISELDO2 SLWRLDO2 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-On Slew Rate * 10% to 90% of end value * VLDOIN23MINVLDOIN23 3.6 V, ILDO2 = 0.0 mA LDO2[3:0] = 0000 to 0011 LDO2[3:0] = 0100 to 0111 LDO2[3:0] = 1000 to 1011 LDO2[3:0] = 1100 to 1111 34VR500 58 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 77. LDO2 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN23 = 3.6 V, VLDO2[3:0] = 1111, ILDO2 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN23 = 3.6 V, LDO2[3:0] = 1111, ILDO2 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes LDO2 AC AND tRANSIENT (Continued) tONLDO2 Turn-On Time Enable to 90% of end value, VLDOIN23 = VLDOIN23MIN, 3.6 V ILDO2 = 0.0 mA 60 - 500 s tOFFLDO2 Turn-Off Time Disable to 10% of initial value, VLDOIN23 = VLDOIN23MIN ILDO2 = 0.0 mA - - 10 ms LDO2OSHT Start-up Overshoot VLDOIN23 = VLDOIN23MIN, 3.6 V, ILDO2 = 0.0 mA - 1.0 2.0 % VLDO2LOTR Transient Load Response VLDOIN23 = VLDOIN23MIN, 3.6 V ILDO2 = 10 to 100 mA in 1.0s Peak of overshoot or undershoot of LDO2 with respect to final value. Refer to Figure 25 - - 3.0 % VLDO2LITR Transient Line Response ILDO2 = 75 mA VLDOIN23INITIAL = 2.8 V to VLDOIN23FINAL = 3.3 V for LDO2[3:0] = 0000 to 0111 VLDOIN23INITIAL = VLDO2+0.3 V to VLDOIN23FINAL = VLDO2+0.8 V for LDO2[3:0] = 1000 to 1010 VLDOIN23INITIAL = VLDO2+0.25 V to VLDOIN23FINAL = 3.6 V for LDO2[3:0] = 1011 to 1111 Refer to Figure 25 - 5.0 8.0 mV Notes 37. When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper regulation due to the dropout voltage generated through the internal LDO transistor. 38. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VLDOIN23MIN refers to the minimum allowed input voltage for a particular output voltage. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 59 Functional Block Requirements and Behaviors Power Generation 6.4.5.5.3 LDO3 Table 78. LDO3 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN23 = 3.6 V, LDO3[3:0] = 1111, ILDO3 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN23 = 3.6 V, LDO3[3:0] = 1111, ILDO3 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes 2.8 LDO3NOM + 0.250 - - 3.6 3.6 V (39) LDO3 VLDOIN23 Operating Input Voltage 1.8 V LDO3NOM 2.5 V 2.6 V LDO3NOM 3.3 V LDO3NOM Nominal Output Voltage - Table 68 - V ILDO3 Operating Load Current 0.0 - 350 mA VLDO3TOL Output Voltage Tolerance VLDOIN23MIN < VLDOIN23 < 3.6 V 0.0 mA < ILDO3 < 350 mA LDO3[3:0] = 0000 to 1111 -3.0 - 3.0 % VLDO3LOR Load Regulation (VLDO3 at ILDO3 = 350 mA) - (VLDO3 at ILDO3 = 0.0 mA) For any VLDOIN23MIN < VLDOIN23 < 3.6 V - 0.07 - mV/mA VLDO3LIR Line Regulation (VLDO3 at 3.6 V) - (VLDO3 at VLDOIN23MIN) For any 0.0 mA < ILDO3 < 350 mA - 0.80 - mV/V ILDO3LIM Current Limit ILDO3 when LDO3 is forced to LDO3NOM/2 435 584.5 700 mA ILDO3OCP Overcurrent Protection Threshold ILDO3 required to cause the SCP function to disable LDO when REGSCPEN = 1 420 - 700 mA - 13 - A 35 55 40 60 - - - - - -114 -129 -135 -102 -123 -130 dBV/Hz - - - - - - - - 22.0 26.5 30.5 34.5 mVs LDO3 DC ILDO3Q Quiescent Current No load, Change in IVIN and IVLDOIN23 When LDO3 enabled LDO3 AC AND tRANSIENT PSRRLDO3 PSRR * ILDO3 = 262.5 mA, 20 Hz to 20 kHz LDO3[3:0] = 0000 - 1110, VLDOIN23 = VLDOIN23MIN + 100 mV LDO3[3:0] = 0000 - 1000, VLDOIN23 = LDO3NOM + 1.0 V dB (40) Output Noise Density * VLDOIN23 = VLDOIN23MIN, ILDO3 = 262.5 mA NOISELDO3 SLWRLDO3 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-On Slew Rate * 10% to 90% of end value * VLDOIN23MIN VLDOIN23 3.6 V, ILDO3 = 0.0 mA LDO3[3:0] = 0000 to 0011 LDO3[3:0] = 0100 to 0111 LDO3[3:0] = 1000 to 1011 LDO3[3:0] = 1100 to 1111 34VR500 60 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 78. LDO3 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN23 = 3.6 V, LDO3[3:0] = 1111, ILDO3 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN23 = 3.6 V, LDO3[3:0] = 1111, ILDO3 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit tONLDO3 Turn-On Time Enable to 90% of end value, VLDOIN23 = VLDOIN23MIN, 3.6 V ILDO3 = 0.0 mA 60 - 500 s tOFFLDO3 Turn-Off Time Disable to 10% of initial value, VLDOIN23 = VLDOIN23MIN ILDO3 = 0.0 mA - - 10 ms LDO3OSHT Start-up Overshoot VLDOIN23 = VLDOIN23MIN, 3.6 V, ILDO3 = 0.0 mA - 1.0 2.0 % VLDO3LOTR Transient Load Response VLDOIN23 = VLDOIN23MIN, 3.6 V ILDO3 = 35 to 350 mA in 1.0 s Peak of overshoot or undershoot of LDO3 with respect to final value. Refer to Figure 25 - - 3.0 % VLDO3LITR Transient Line Response ILDO3 = 262.5 mA VLDOIN23INITIAL = 2.8 V to VLDOIN23FINAL = 3.3 V for LDO3[3:0] = 0000 to 0111 VLDOIN23INITIAL = VLDO3+0.3 V to VLDOIN23FINAL = VLDO3+0.8 V for LDO3[3:0] = 1000 to 1010 VLDOIN23INITIAL = VLDO3+0.25 V to VLDOIN23FINAL = 3.6 V for LDO3[3:0] = 1011 to 1111 Refer to Figure 25 - 5.0 8.0 mV Notes LDO3 AC AND tRANSIENT (Continued) Notes 39. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 40. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VLDOIN23MIN refers to the minimum allowed input voltage for a particular output voltage. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 61 Functional Block Requirements and Behaviors Power Generation 6.4.5.5.4 LDO4 Table 79. LDO4 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO4[3:0] = 1111, ILDO4 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO4[3:0] = 1111, ILDO4 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes 2.8 LDO4NOM + 0.250 - - 4.5 4.5 V (41) LDO4 VLDOIN45 Operating Input Voltage 1.8 V LDO4NOM 2.5 V 2.6 V LDO4NOM 3.3 V LDO4NOM Nominal Output Voltage - Table 68 - V ILDO4 Operating Load Current 0.0 - 100 mA -3.0 - 3.0 % LDO4 Active Mode - DC VLDO4TOL Output Voltage Tolerance VLDOIN45MIN < VLDOIN45 < 4.5 V 0.0 mA < ILDO4 < 100 mA, LDO4[3:0] = 0000 to 1111 VLDO4LOR Load Regulation (VLDO4 at ILDO4 = 100 mA) - (VLDO4 at ILDO4 = 0.0 mA) For any VLDOIN45MIN < VLDOIN45 < 4.5 mV - 0.10 - mV/mA VLDO4LIR Line Regulation (VLDO4 at VLDOIN45 = 4.5 V) - (VLDO4 at VLDOIN45MIN) For any 0.0 mA < ILDO4 < 100 mA - 0.50 - mV/V ILDO4LIM Current Limit ILDO4 when LDO4 is forced to LDO4NOM/2 122 167 200 mA ILDO4OCP Overcurrent Protection threshold ILDO4 required to cause the SCP function to disable LDO when REGSCPEN = 1 120 - 200 mA - 13 - A 35 52 40 60 - - - - - -114 -129 -135 -102 -123 -130 dBV/Hz - - - - - - - - 22.0 26.5 30.5 34.5 mVs ILDO4Q Quiescent Current No load, Change in IVIN and IVLDOIN45 When LDO4 enabled LDO4 AC AND tRANSIENT PSRRLDO4 PSRR * ILDO4 = 75 mA, 20 Hz to 20 kHz LDO4[3:0] = 0000 - 1111, VLDOIN45 = VLDOIN45MIN + 100 mV LDO4[3:0] = 0000 - 1111, VLDOIN45 = LDO4NOM + 1.0 V dB (42) Output Noise Density * VLDOIN45 = VLDOIN45MIN, ILDO4 = 75 mA NOISELDO4 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-On Slew Rate * 10% to 90% of end value * VLDOIN45MIN VLDOIN45 4.5 mV, ILDO4 = 0.0 mA SLWRLDO4 LDO4[3:0] = 0000 to 0011 LDO4[3:0] = 0100 to 0111 LDO4[3:0] = 1000 to 1011 LDO4[3:0] = 1100 to 1111 34VR500 62 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Power Generation Table 79. LDO4 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO4[3:0] = 1111, ILDO4 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO4[3:0] = 1111, ILDO4 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit tONLDO4 Turn-On Time Enable to 90% of end value, VLDOIN45 = VLDOIN45MIN, 4.5 V ILDO4 = 0.0 mA 60 - 500 s tOFFLDO4 Turn-Off Time Disable to 10% of initial value, VLDOIN45 = VLDOIN45MIN ILDO4 = 0.0 mA - - 10 ms LDO4OSHT Start-Up Overshoot VLDOIN45 = VLDOIN45MIN, 4.5 V, ILDO4 = 0.0 mA - 1.0 2.0 % VLDO4LOTR Transient Load Response VLDOIN45 = VLDOIN45MIN, 4.5 V ILDO4 = 10 to 100 mA in 1.0 s Peak of overshoot or undershoot of LDO4 with respect to final value. Refer to Figure 25 - - 3.0 % VLDO4LITR Transient Line Response ILDO4 = 75 mA VLDOIN45INITIAL = 2.8 V to VLDOIN45FINAL = 3.3 V for LDO4[3:0] = 0000 to 0111 VLDOIN45INITIAL = VLDO4+0.3 V to VLDOIN45FINAL = VLDO4+0.8 V for LDO4[3:0] = 1000 to 1111 Refer to Figure 25 - 5.0 8.0 mV Notes LDO4 Active Mode - DC (Continued) Notes 41. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 42. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VLDOIN45MIN refers to the minimum allowed input voltage for a particular output voltage. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 63 Functional Block Requirements and Behaviors Power Generation 6.4.5.5.5 LDO5 Table 80. LDO5 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO5[3:0] = 1111, ILDO5 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO5[3:0] = 1111, ILDO5 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes 2.8 LDO5NOM+ 0.250 - - 4.5 4.5 V (43) LDO5 VLDOIN45 Operating Input Voltage 1.8 V LDO5NOM 2.5 V 2.6 V LDO5NOM 3.3 V LDO5NOM Nominal Output Voltage - Table 68 - V ILDO5 Operating Load Current 0.0 - 200 mA VLDO5TOL Output Voltage Tolerance VLDOIN45MIN < VLDOIN45 < 4.5 V, 0.0 mA < ILDO5 < 200 mA LDO5[3:0] = 0000 to 1111 -3.0 - 3.0 % VLDO5LOR Load Regulation (VLDO5 at ILDO5 = 200 mA) - (VLDO5 at ILDO5 = 0.0 mA) For any VLDOIN45MIN < VLDOIN45 < 4.5 V - 0.10 - mV/mA VLDO5LIR Line Regulation (VLDO5 at VLDOIN45 = 4.5 V) - (VLDO5 at VLDOIN45MIN) For any 0.0 mA < ILDO5 < 200 mA - 0.50 - mV/V ILDO5LIM Current Limit ILDO5 when LDO5 is forced to LDO5NOM/2 232 333 475 ILDO5OCP Over Current Protection Threshold ILDO5 required to cause the SCP function to disable LDO when REGSCPEN = 1 220 - 475 - 13 - 35 52 40 60 - - - - - -114 -129 -135 -102 -123 -130 dBV/Hz - - - - - - - - 22.0 26.5 30.5 34.5 mVs LDO5 DC ILDO5Q Quiescent Current No load, Change in IVIN and IVLDOIN45, When LDO5 enabled mA mA A LDO5 AC AND tRANSIENT PSRRLDO5 PSRR * ILDO5 = 150 mA, 20 Hz to 20 kHz LDO5[3:0] = 0000 - 1111, VLDOIN45 = VLDOIN45MIN + 100 mV LDO5[3:0] = 0000 - 1111, VLDOIN45 = LDO5NOM + 1.0 V dB (44) Output Noise Density * VLDOIN45 = VLDOIN45MIN, ILDO5 = 150 mA NOISELDO5 100 Hz - <1.0 kHz 1.0 kHz - <10 kHz 10 kHz - 1.0 MHz Turn-On Slew Rate * 10% to 90% of end value * VLDOIN45MIN VLDOIN45 4.5 V. ILDO5 = 0.0 mA SLWRLDO5 LDO5[3:0] = 0000 to 0011 LDO5[3:0] = 0100 to 0111 LDO5[3:0] = 1000 to 1011 LDO5[3:0] = 1100 to 1111 34VR500 64 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 80. LDO5 Electrical Characteristics All parameters are specified at TA = -40 to 105 C (See Table 3), VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO5[3:0] = 1111, ILDO5 = 10 mA, VVBIAS = 1.0 V 4.0%, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN45 = 3.6 V, LDO5[3:0] = 1111, ILDO5 = 10 mA, and 25 C, unless otherwise noted. Symbol Parameter Min. Typ. Max. Unit Notes LDO5 AC AND tRANSIENT (Continued) tONLDO5 Turn-On Time Enable to 90% of end value, VLDOIN45 = VLDOIN45MIN, 4.5 V ILDO5 = 0.0 mA 60 - 500 s tOFFLDO5 Turn-Off Time Disable to 10% of initial value, VLDOIN45 = VLDOIN45MIN ILDO5 = 0.0 mA - - 10 ms LDO5OSHT Start-Up Overshoot VLDOIN45 = VLDOIN45MIN, 4.5 V, ILDO5 = 0 mA - 1.0 2.0 % VLDO5LOTR Transient Load Response VLDOIN45 = VLDOIN45MIN, 4.5 V ILDO5 = 20 to 200 mA in 1.0 s Peak of overshoot or undershoot of LDO5 with respect to final value. Refer to Figure 25 - - 3.0 % VLDO5LITR Transient Line Response ILDO5 = 150 mA VLDOIN45INITIAL = 2.8 V to VLDOIN45FINAL = 3.3 V for LDO5[3:0] = 0000 to 0111 VLDOIN45INITIAL = VLDO5+0.3 V to VLDOIN45FINAL = VLDO5+0.8 V for LDO5[3:0] = 1000 to 1111 Refer to Figure 25 - 5.0 8.0 mV Notes 43. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper regulation due to the dropout voltage generated through the internal LDO transistor. 44. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test. VLDOIN45 refers to the minimum allowed input voltage for a particular output voltage. 6.5 Control Interface I2C Block Description The 34VR500 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers, the resources of the IC can be controlled. The registers also provide status information about how the IC is operating. The SCL and SDA lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL and SDA traces from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be accomplished by reducing the drive strength of the I2C master via software. It is recommended to use a drive strength of 80 or higher to increase the edge times. Alternatively, this can be accomplished by using small capacitors from SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 k. 6.5.1 I2C Device ID I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. The I2C address is set to 0x08. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 65 Functional Block Requirements and Behaviors Control Interface I2C Block Description 6.5.2 I2C Operation The I2C mode of the interface is implemented generally following the Fast mode definition which supports up to 400 kbits/s operation (exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) The I2C interface is configured as "Slave". Timing diagrams, electrical specifications, and further details can be found in the I2C specification, which is available for download at: http://www.nxp.com/documents/user_manual/UM10204.pdf I2C read operations are performed in byte increments separated by an ACK. Read operations begin with the MSB and each byte is sent out unless a STOP command or NACK is received prior to completion. The 34VR500 only supports single-byte I2C transactions for read and write. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device responds to the host if the master command packet contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction. The 34VR500 uses the "repeated start" operation for reads, as shown in Figure 27. Figure 26. Data Transfer on the I2C Bus Figure 27. Read Operation 6.5.3 Interrupt Handling The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving the INTB pin low. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each interrupt can be cleared by writing a "1" to the appropriate bit in the Interrupt Status register; this will also cause the INTB pin to go high. If there are multiple interrupt bits set the INTB pin will remain low until all are either masked or cleared. If a new interrupt occurs while the processor clears an existing interrupt bit, the INTB pin will remain low. Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB pin will not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the INTB pin will go low after unmasking. 34VR500 66 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 81. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly. 6.5.4 Interrupt Bit Summary Table 81 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer to the related chapters. Table 81. Interrupt, Mask and Sense Bits Interrupt Mask Sense Purpose Trigger Debounce Time (ms) Low Input Voltage Detect Sense is 1 if below 2.80 V threshold H to L 3.9(45) Enable on button event H to L 31.25(45) Sense is 1 if EN is high L to H 31.25 LOWVINI LOWVINM LOWVINS ENI ENM ENS THERM110 THERM110M THERM110S Thermal 110 C threshold Sense is 1 if above threshold Dual 3.9 THERM120 THERM120M THERM120S Thermal 120 C threshold Sense is 1 if above threshold Dual 3.9 THERM125 THERM125M THERM125S Thermal 125 C threshold Sense is 1 if above threshold Dual 3.9 THERM130 THERM130M THERM130S Thermal 130 C threshold Sense is 1 if above threshold Dual 3.9 SW1FAULTI SW1FAULTM SW1FAULTS Regulator 1 overcurrent limit Sense is 1 if above current limit L to H 8.0 SW2FAULTI SW2FAULTM SW2FAULTS Regulator 2 overcurrent limit Sense is 1 if above current limit L to H 8.0 SW3FAULTI SW3FAULTM SW3FAULTS Regulator 3 overcurrent limit Sense is 1 if above current limit L to H 8.0 SW4FAULTI SW4FAULTM SW4FAULTS Regulator 4 overcurrent limit Sense is 1 if above current limit L to H 8.0 LDO1FAULTI LDO1FAULTM LDO1FAULTS LDO1 overcurrent limit Sense is 1 if above current limit L to H 8.0 LDO2FAULTI LDO2FAULTM LDO2FAULTS LDO2 overcurrent limit Sense is 1 if above current limit L to H 8.0 LDO3FAULTI LDO3FAULTM LDO3FAULTS LDO3 overcurrent limit Sense is 1 if above current limit L to H 8.0 LDO4FAULTI LDO4FAULTM LDO4FAULTS LDO4 overcurrent limit Sense is 1 if above current limit L to H 8.0 LDO5FAULTI LDO5FAULTM LDO5FAULTS LDO5 overcurrent limit Sense is 1 if above current limit L to H 8.0 Notes 45. Debounce timing for the falling edge can be extended with ENDBNC[1:0]. A full description of all interrupt, mask, and sense registers is provided in Tables 82 to 90. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 67 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 82. Register INTSTAT0 - ADDR 0x05 Name Bit # R/W Default Description ENI 0 R/W1C 0 Power on interrupt bit LOWVINI 1 R/W1C 0 Low-voltage interrupt bit THERM110I 2 R/W1C 0 110 C Thermal interrupt bit THERM120I 3 R/W1C 0 120 C Thermal interrupt bit THERM125I 4 R/W1C 0 125 C Thermal interrupt bit THERM130I 5 R/W1C 0 130 C Thermal interrupt bit Table 83. Register INTMASK0 - ADDR 0x06 Name Bit # R/W Default Description ENM 0 R/W1C 1 Power on interrupt mask bit LOWVINM 1 R/W1C 1 Low-voltage interrupt mask bit THERM110M 2 R/W1C 1 110 C Thermal interrupt mask bit THERM120M 3 R/W1C 1 120 C Thermal interrupt mask bit THERM125M 4 R/W1C 1 125 C Thermal interrupt mask bit THERM130M 5 R/W1C 1 130 C Thermal interrupt mask bit Table 84. Register INTSENSE0 - ADDR 0x07 Name Bit # R/W Default Description ENS 0 R 0 Enable on sense bit 0 = EN low 1 = EN high LOWVINS 1 R 0 Low voltage sense bit 0 = VIN > 2.8 V 1 = VIN 2.8 V THERM110S 2 R 0 110 C Thermal sense bit 0 = Below threshold 1 = Above threshold THERM120S 3 R 0 120 C Thermal sense bit 0 = Below threshold 1 = Above threshold THERM125S 4 R 0 125 C Thermal sense bit 0 = Below threshold 1 = Above threshold THERM130S 5 R 0 130 C Thermal sense bit 0 = Below threshold 1 = Above threshold Table 85. Register INTSTAT1 - ADDR 0x08 Name Bit # R/W Default Description SW1FAULTI 2:0 R/W1C 0 SW1 Overcurrent interrupt bit SW2FAULTI 3 R/W1C 0 SW2 Overcurrent interrupt bit 34VR500 68 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 85. Register INTSTAT1 - ADDR 0x08 (continued) Name Bit # R/W Default Description SW3FAULTI 5:4 R/W1C 0 SW3 Overcurrent interrupt bit SW4FAULTI 6 R/W1C 0 SW4 Overcurrent interrupt bit Table 86. Register INTMASK1 - ADDR 0x09 Name Bit # R/W Default 2:0 R/W 1 SW1 Overcurrent interrupt mask bit SW2FAULTM 3 R/W 1 SW2 Overcurrent interrupt mask bit SW3FAULTM 5:4 R/W 1 SW3 Overcurrent interrupt mask bit SW4FAULTM 6 R/W 1 SW4 Overcurrent interrupt mask bit SW1FAULTM Description Table 87. Register INTSENSE1 - ADDR 0x0A Name Bit # R/W Default Description SW1FAULTS 2:0 R 0 SW1 Overcurrent sense bit 0 = Normal operation 1 = Above current limit SW2FAULTS 3 R 0 SW2 Overcurrent sense bit 0 = Normal operation 1 = Above current limit SW3FAULTS 5:4 R 0 SW3 Overcurrent sense bit 0 = Normal operation 1 = Above current limit SW4FAULTS 6 R 0 SW4 Overcurrent sense bit 0 = Normal operation 1 = Above current limit Table 88. Register INTSTAT4 - ADDR 0x11 Name Bit # R/W Default Description LDO1FAULTI 1 R/W1C 0 LDO1 Overcurrent interrupt bit LDO2FAULTI 2 R/W1C 0 LDO2 Overcurrent interrupt bit LDO3FAULTI 3 R/W1C 0 LDO3 Overcurrent interrupt bit LDO4FAULTI 4 R/W1C 0 LDO4 Overcurrent interrupt bit LDO5FAULTI 5 R/W1C 0 LDO5 Overcurrent interrupt bit Table 89. Register INTMASK4 - ADDR 0x12 Name Bit # R/W Default Description LDO1FAULTM 1 R/W 1 LDO1 Overcurrent interrupt mask bit LDO2FAULTM 2 R/W 1 LDO2 Overcurrent interrupt mask bit LDO3FAULTM 3 R/W 1 LDO3 Overcurrent interrupt mask bit LDO4FAULTM 4 R/W 1 LDO4 Overcurrent interrupt mask bit LDO5FAULTM 5 R/W 1 LDO5 Overcurrent interrupt mask bit 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 69 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 90. Register INTSENSE4 - ADDR 0x13 Name 6.5.5 6.5.5.1 Bit # R/W Default Description LDO1FAULTS 1 R 0 LDO1 Overcurrent sense bit 0 = Normal operation 1 = Above current limit LDO2FAULTS 2 R 0 LDO2 Overcurrent sense bit 0 = Normal operation 1 = Above current limit LDO3FAULTS 3 R 0 LDO3 Overcurrent sense bit 0 = Normal operation 1 = Above current limit LDO4FAULTS 4 R 0 LDO4 Overcurrent sense bit 0 = Normal operation 1 = Above current limit LDO5FAULTS 5 R 0 LDO5 Overcurrent sense bit 0 = Normal operation 1 = Above current limit Specific Registers IC and Version Identification The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 91 to 93. Table 91. Register DEVICEID - ADDR 0x00 Name DEVICEID Bit # R/W Default 3:0 R 0x00 Description Die version. 0100 = 34VR500 Table 92. Register SILICON REV- ADDR 0x03 Name METAL_LAYER_REV FULL_LAYER_REV Bit # 3:0 7:4 R/W R R Default Description 0x00 Represents the metal mask revision Pass 0.0 = 0000 . . Pass 0.15 = 1111 0x01 Represents the full mask revision Pass 1.0 = 0001 . . Pass 15.0 = 1111 Table 93. Register FABID - ADDR 0x04 Name Bit # R/W Default Description FIN 1:0 R 0x00 Allows for characterizing different options within the same reticule FAB 3:2 R 0x00 Represents the wafer manufacturing facility 34VR500 70 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description 6.5.6 Register Bitmap The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page, the functional registers are the same, but the extended registers are different. To access the Functional Page from one of the extended pages, no write to the page register is necessary. Registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will have no effect. The contents of all registers are given in the tables defined in this chapter; each table is structure as follows: Name: Name of the bit. Bit #: The bit location in the register (7-0) R/W: Read / Write access and control * R is read-only access * R/W is read and write access * RW1C is read and write access with write 1 to clear Reset: Reset signals are color coded based on the following legend. Bits reset by VCOREDIG_PORB Bits reset by EN or loaded default Bits reset by DIGRESETB Bits reset by PORB Bits reset by VCOREDIG_PORB Bits reset by POR or OFFB Default: The value after reset, as noted in the Default column of the memory map. * Fixed defaults are explicitly declared as 0 or 1. * "X" corresponds to Read / Write bits that are initialized at start-up. Bits are subsequently I2C modifiable, when their reset has been released. "X" may also refer to bits that may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts. 6.5.6.1 Register map Table 94. Functional Page BITS[7:0] Add Register Name R/W Default 00 DeviceID R 8'b0001_0000 7 6 5 4 - - - - 0 0 0 1 3 2 04 05 06 07 SILICONREVID FABID INTSTAT0 INTMASK0 INTSENSE0 R R RW1C R/W R 0 DEVICE ID [3:0] 0 1 FULL_LAYER_REV[3:0] 03 1 0 0 METAL_LAYER_REV[3:0] 8'b0001_0000 0 0 0 1 0 0 0 - - - - 0 0 0 0 0 0 0 0 - - THERM130I THERM125I THERM120I THERM110I LOWVINI ENI 0 0 0 0 0 0 0 0 - - THERM130M THERM125M THERM120M THERM110M LOWVINM ENM 0 0 1 1 1 1 1 1 RSVD RSVD THERM130S THERM125S THERM120S THERM110S LOWVINS ENS 0 0 x x x x x x FAB[1:0] 0 FIN[1:0] 8'b0000_0000 8'b0000_0000 8'b0011_1111 8'b00xx_xxxx 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 71 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 94. Functional Page (continued) BITS[7:0] Add Register Name R/W Default 08 INTSTAT1 RW1C 8'b0000_0000 09 0A 11 12 13 1B 2E 2F 30 31 INTMASK1 INTSENSE1 INTSTAT4 INTMASK4 INTSENSE4 PWRCTL SW1VOLT SW1STBY SW1OFF SW1MODE R/W R RW1C R/W R R/W R/W R/W R/W R/W 7 6 5 - SW4FAULTI 0 0 - SW4FAULTM 0 1 - SW4FAULTS 0 x x x x x x - - LDO5FAULTI LDO4FAULTI LDO3FAULTI LDO2FAULTI LDO1FAULTI - 0 0 0 0 0 0 0 0 - - LDO5 FAULTM LDO4 FAULTM LDO3 FAULTM LDO2 FAULTM LDO1 FAULTM - 0 0 1 1 1 1 1 1 - - LDO5 FAULTS LDO4 FAULTS LDO3 FAULTS LDO2 FAULTS LDO1 FAULTS - 0 0 x x x x x x REGSCPEN STANDBYINV ENRSTEN RESTARTEN 0 0 0 0 0 - - 0 0 x x x - - 0 0 x x x - - 0 0 x x x x - - SW1OMODE - 0 0 0 0 SW3FAULTI 0 35 36 37 38 SW1CONF SW2VOLT SW2STBY SW2OFF SW2MODE R/W R/W R/W R/W R/W SW2CONF R/W 2 1 SW2FAULTI 0 SW3FAULTM 0 SW1FAULTI 0 0 0 SW2FAULTM 0 SW1FAULTM 1 1 SW3FAULTS 1 1 1 SW2FAULTS 1 SW1FAULTS 8'b0xxx_xxxx x 8'b0000_0000 8'b0011_1111 8'b00xx_xxxx STBYDLY[1:0] ENDBNC[1:0] 8'b0001_0000 0 1 0 SW1[5:0] 8'b00xx_xxxx x x x SW1STBY[5:0] 8'b00xx_xxxx x x x SW1OFF[5:0] 8'b00xx_xxxx x x SW1MODE[3:0] 8'b0000_1000 1 SW1PHASE[1:0] 0 0 0 - SW1ILIM x 0 0 x x x x x x x x x SW1FREQ[1:0] 8'bxx00_xx00 x x - - 0 0 - - 0 0 0 0 x SW2[5:0] 8'b0xxx_xxxx x x x SW2STBY[5:0] 8'b0xxx_xxxx x x x x - - 0 0 x x SW2OFF[5:0] - - SW2OMODE - 0 0 0 0 8'b0xxx_xxxx SW2MODE[3:0] 8'b0000_1000 SW2DVSSPEED[1:0] 39 3 8'b0111_1111 SW1DVSSPEED[1:0] 32 4 1 SW2PHASE[1:0] 0 SW2FREQ[1:0] 0 0 - SW2ILIM 0 0 8'bxx01_xx00 x x 0 1 x x 34VR500 72 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 94. Functional Page (continued) BITS[7:0] Add Register Name R/W Default 3C SW3VOLT R/W 8'b0xxx_xxxx 3D 3E 3F SW3STBY SW3OFF SW3MODE R/W R/W R/W 7 6 - - 0 0 - - 0 0 - - 0 0 0 0 5 4A 4B 4C 4D SW3CONF SW4VOLT SW4STBY SW4OFF SW4MODE R/W R/W R/W R/W R/W 6A 6D 6E 6F 70 71 7F SW4CONF REFOUTCRTRL LDO1CTL LDO2CTL LDO3CTL LDO4CTL LDO5CTL Page Register R/W R/W R/W R/W R/W R/W R/W R/W 2 1 0 x x x x x x x x x x x x 1 0 x SW3STBY[5:0] 8'b0xxx_xxxx x x x SW3OFF[5:0] 8'b0xxx_xxxx x x SW3OMODE - 0 0 SW3MODE[3:0] 8'b0000_1000 SW3PHASE[1:0] 0 0 - SW3ILIM x 0 0 x x x x x x x x SW3FREQ[1:0] 8'bxx10_xx00 x x 1 0 - - 0 0 - - 0 0 - - 0 0 x x - - SW4OMODE - 0 0 0 0 x SW4[5:0] 8'b0xxx_xxxx x x x SW4STBY[5:0] 8'b0xxx_xxxx x x x SW4OFF[5:0] 8'b0xxx_xxxx x x SW4MODE[3:0] 8'b0000_1000 SW4DVSSPEED[1:0] 4E 3 SW3[5:0] SW3DVSSPEED[1:0] 40 4 1 SW4PHASE[1:0] 0 SW4FREQ[1:0] 0 0 - SW4ILIM 8'bxx11_xx00 x x 1 1 x x 0 0 - - - REFOUTEN - - - - 0 0 0 x 0 0 0 0 - LDO1LPWR LDO1STBY LDO1EN 0 0 0 x x x - LDO2LPWR LDO2STBY LDO2EN 0 0 0 x x x - LDO3LPWR LDO3STBY LDO3EN 0 0 0 x x x - LDO4LPWR LDO4STBY LDO4EN 0 0 0 x x x - LDO5LPWR LDO5STBY LDO5EN 0 0 0 x x x - - - 0 0 0 x x 8'b000x_0000 LDO1[3:0] 8'b000x_xxxx x x x x LDO2[3:0] 8'b000x_xxxx LDO3[3:0] 8'b000x_xxxx x x LDO4[3:0] 8'b000x_xxxx x x LDO5[3:0] 8'b000x_xxxx x x PAGE[4:0] 8'b0000_0000 x x x 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 73 Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 95. Extended Page 1: Internal RAM BITS[7:0] Address A8 Register Name SW1 VOLT TYPE R/W Default 7 6 - - 0 0 5 4 3 AA AC AD AE B0 B1 B2 B8 B9 BA C4 CC CD D0 SW1 SEQ SW1 CONFIG SW2 VOLT SW2 SEQ SW2 CONFIG SW3 VOLT SW3 SEQ SW3 CONFIG SW4 VOLT SW4 SEQ SW4 CONFIG REFOUT SEQ LDO1 VOLT LDO1 SEQ LDO2 VOLT R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 1 0 x x x x SW1_VOLT[5:0] 8'b00xx_xxxx x x x - A9 2 SW1_SEQ[4:0] 8'b000x_xxxx 0 0 0 x x x x - - - - - - SW1_FREQ[1:0] 0 0 0 0 0 0 x x x x x x x x 8'b0000_00xx - - 0 0 SW2_VOLT[5:0] - - 0 0 0 x x x x - - - - - - SW2_FREQ[1:0] 0 0 0 0 0 0 x x - - 0 0 x x x - - 0 0 0 x x x x - - - - SW3_CONFIG[1:0] SW3_FREQ[1:0] 0 0 0 0 x x x x - - 0 0 x x x x - - - 0 0 0 x x x x x - - - VTT - - SW4_FREQ[1:0] 0 0 0 x x x x x - - - 0 0 0 x x x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 8'b0xxx_xxxx x SW2_SEQ[4:0] 8'b000x_xxxx 8'b0000_00xx SW3_VOLT[5:0] 8'b0xxx_xxxx x x x SW3_SEQ[4:0] 8'b000x_xxxx x 8'b0000_xxxx SW4_VOLT[5:0] 8'b00xx_xxxx x x SW4_SEQ[4:0] 8'b000x_xxxx 8'b000x_xxxx REFOUT_SEQ[4:0] 8'b000x_x0xx x 0 LDO1_VOLT[3:0] 8'b0000_xxxx x x x x x x LDO1_SEQ[4:0] 8'b000x_xxxx x x LDO2_VOLT[3:0] 8'b0000_xxxx x x x x 34VR500 74 Analog Integrated Circuit Device Data Freescale Semiconductor Functional Block Requirements and Behaviors Control Interface I2C Block Description Table 95. Extended Page 1: Internal RAM (continued) BITS[7:0] Address D1 D4 D5 D8 D9 DC DD E0 E4 E8 Register Name LDO2 SEQ LDO3 VOLT LDO3 SEQ LDO4 VOLT LDO4 SEQ LDO5 VOLT LDO5 SEQ PU CONFIG1 TBB_POR PWRGD EN TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W/M Default 7 6 5 4 3 2 1 0 - - - 0 0 0 x x x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 x - - - - 0 0 0 0 - - - 0 0 0 x - - - PWRON_ CFG1 0 0 0 x x x x x TBB_POR RSVD - - - - RSVD - 0 RSVD RSVD RSVD RSVD RSVD RSVD RSVD - - - - - - - PG_EN 0 0 0 0 0 0 x 0 LDO2_SEQ[4:0] 8'b000x_xxxx x x LDO3_VOLT[3:0] 8'b0000_xxxx x x x x x x LDO3_SEQ[4:0] 8'b000x_xxxx x x LDO4_VOLT[3:0] 8'b0000_xxxx x x x x x x LDO4_SEQ[4:0] 8'b000x_xxxx x x LDO5_VOLT[3:0] 8'b0000_xxxx x x x x x x LDO5_SEQ[4:0] 8'b000x_xxxx 8'b000x_xxxx x x SWDVS_CLK1[1:0] SEQ_CLK_SPEED1[1:0] 8'b0000_00x0 8'b0000_000x 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 75 Typical Applications Introduction 7 Typical Applications 7.1 Introduction Figure 28 provides a typical application diagram of the 34VR500 PMIC together with its functional components. For details on component references and additional components such as filters, refer to the individual sections. 7.1.1 Application Diagram VLDOIN1 VR500 1.0uF 4.7uF LDO1 FB1 SW1 Output Vin PVIN1 SW1 4500 mA Buck LDO1 250mA O/P Drive 3 x 4.7 uF +3 x 0.1 uF 0.68uH LX1 7 x22 uF VLDOIN23 1.0uF LDO2 2.2uF 4.7uF LDO3 LDO2 100mA SW2 Output SW2 2000 mA Buck VLDOIN45 1.0uF 1.5uH LX2 LDO3 350mA O/P Drive Core Control logic PVIN2 FB2 Vin 3 x 22 uF 4.7 uF +0.1 uF LDO4 100mA 2.2uF LDO4 2.2uF LDO5 Initialization State Machine FB3 LDO5 200mA SW3 2500 mA Buck Supplies Control VCCI2C CONTROL I2C Interface 4.7k 4.7k VCCI2C PVIN3 1.5uH LX3 Vin SDA SW3 Output Vin 2 x 4.7 uF +2 x 0.1 uF 3 x 22 uF FB4 SW4 1000 mA Buck SCL To MCU O/P Drive PVIN4 O/P Drive LX4 SW4 Output 4.7 uF +0.1 uF 1.5uH 3 x 22 uF DVS CONTROL DVS Control 1uF I2C Register map VDIG 220nF VBG 1uF VCC Trim-In-Package Reference Generation Clocks and resets SGND4 0.47uF VBIAS 1uF Clocks REFOUT 32kHz and 16MHz VSW3 REFIN Package Pin Legend Output Pin 100nF Input Pin VHALF Bi-directional Pin 100k VSW2 INTB ICTEST2 PORTB VSW2 100k EN STBY VSW2 100k ICTEST1 100nF To/From AP Figure 28. Typical Application Schematic 34VR500 76 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications Bill of Materials 7.1.2 Application Instructions Table 96 provides a complete list of the recommended components on a full featured system using the 34VR500 device. Critical components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may be used. 7.2 Bill of Materials Table 96. Bill of Materials (46) Item Qty Schematic Label Value Description Part Number Manufacturer Component/Pin Assy Opt Freescale Components 1 1 Power management IC 34VR500 Freescale BUCK, SW1 - (0.625-1.875 V), 4.5 A 2 1 0.60 H 4 x 4 x 2.1 ISAT = 10.4 A for 30% drop, DCRMAX = 10.45 m XAL4020-601ME Coilcraft Output Inductor 3 6 22 F 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance 4 3 4.7 F 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance 5 3 0.1 F 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance BUCK, SW2 - (0.625-1.975 V), 2.0 A 6 1 1.5 H 3.9 x 3.9 x 1.1 ISAT = 2.6 A for 10% drop, DCRMAX = 70 m LPS4012-152MR Coilcraft Output Inductor 7 2 22 F 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance 8 1 4.7 F 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance 9 1 0.1 F 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance BUCK, SW3 - (0.625-1.975 V), 2.5 A 10 1 1.5 H 4 x 4 x 2.1 ISAT = 7.0 A for 10% drop, DCRMAX = 21.45 m XFL4020-152ME Coilcraft Output Inductor 11 - 1.5 H 4.3 x 4.3 x 1.4 ISAT = 2.9 A for 10% drop, DCRMAX = 78 m LPS4014_152ML Coilcraft Output Inductor (Alternate) 12 - 1.0 H 4 x 4 x 1.2 ISAT = 6.2 A, DCR = 37 m FDSD0412-H-1R0M Toko Output inductor (Alternate) 13 4 22 F 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance 14 2 4.7 F 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance 15 1 0.1 F 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 77 Typical Applications Bill of Materials Table 96. Bill of Materials (46) (continued) Item Qty Schematic Label Value Description Part Number Manufacturer Component/Pin Assy Opt BUCK, SW4 - (0.625-1.975 V), 1.0 A 16 1 1.5 H 3.9 x 3.9 x 1.1 ISAT = 2.6 A for 10% drop, DCRMAX = 70 m LPS4012-152MR Coilcraft Output Inductor 17 2 22 F 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance 18 1 4.7 F 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance 19 1 0.1 F 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance 6.3 V X5R 0402 C0402X5R6R3- Venkel Output capacitance 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance 6.3 V X5R 0402 C0402X5R6R3- Venkel Output capacitance 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance LDO, LDO1 - (0.80-1.55), 250 mA 20 1 4.7 F LDO, LDO2 - (1.80-3.30), 100 mA 21 1 2.2 F LDO, LDO3 - (1.80-3.30), 350 mA 22 1 4.7 F LDO, LDO4 - (1.80-3.30), 100 mA 23 1 2.2 F LDO, LDO5 - (1.80-3.30), 200 mA 24 1 2.2 F Reference, REFOUT - (0.60-0.90V), 10 mA 25 1 1.0 F 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America Output capacitance 26 2 0.1 F 10 V X5R 0402 C0402C104K8PAC VHALF, REFIN Kemet Internal References, VDIG, VBG, VCC 27 1 1.0 F 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VDIG 28 1 1.0 F 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VCC 29 1 0.22 F 10 V X5R 0402 GRM155R61A224KE1 Murata VBG Kemet VCCI2C Miscellaneous 30 1 0.1 F 10 V X5R 0402 CD402C104K8PAC 31 1 1.0 F 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VIN 32 1 100 k 1/16 W 0402 RK73H1ETTP1003F KOA SPEER EN 33 1 100 k 1/16 W 0402 RK73H1ETTP1003F KOA SPEER PORB 34 1 100 k 1/16 W 0402 RK73H1ETTP1003F KOA SPEER STBY 35 1 100 k 1/16 W 0402 RK73H1ETTP1003F KOA SPEER INTB Notes 46. Freescale does not assume liability, endorse, or warrant components from external manufacturers are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application. 47. Do not populate 48. Critical components. For critical components, it is vital to use the manufacturer listed. 34VR500 78 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications 34VR500 Layout Guidelines 7.3 34VR500 Layout Guidelines 7.3.1 General Board Recommendations 1. It is recommended to use an eight layer board stack-up arranged as follows: * High current signal * GND * Signal * Power * Power * Signal * GND * High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing. 7.3.2 Component Placement It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output capacitors. 7.3.3 1. * * * * 2. General Routing Requirements Some recommended things to keep in mind for manufacturability: Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper Minimum allowed spacing between line and hole pad is 3.5 mils Minimum allowed spacing between line and line is 3.0 mils Care must be taken with FBx pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the PVINx, SWx, and LXx pins. They could be also shielded. 3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Avoid coupling traces between important signal/low noise supplies (like VBG, VCC, VDIG) from any switching node (i.e. LX1, LX2, LX3, and LX4). 5. Make sure that all components related to a specific block are referenced to the corresponding ground. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 79 Typical Applications 34VR500 Layout Guidelines 7.3.4 1. * * Parallel Routing Requirements I2C signal routing CLK is the fastest signal of the system, so it must be given special care. To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length. Figure 29. Recommended Shielding for Critical Signals * These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane. * Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals. 7.3.5 Switching Regulator Layout Recommendations 1. Per design, the switching regulators in 34VR500 are designed to operate with only one input bulk capacitor. However, it is recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins. 2. Make high-current ripple traces low-inductance (short, high W/L ratio). 3. Make high-current traces wide or copper islands. 34VR500 80 Analog Integrated Circuit Device Data Freescale Semiconductor Typical Applications Thermal Information VIN PVINx CIN_HF Driver Controller CIN SWx LXx L COUT Compensation FBx Figure 30. Generic Buck Regulator Architecture Figure 31. Layout Example for Buck Regulators 7.4 Thermal Information 7.4.1 Rating Data The thermal rating data of the packages has been simulated with the results listed in Table 4. Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RJA or JA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RJMA or JMA (Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org. 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 81 Typical Applications Thermal Information 7.4.2 Estimation of Junction Temperature An estimation of the chip junction temperature TJ can be obtained from the equation: TJ = TA + (RJA x PD) with: TA = Ambient temperature for the package in C RJA = Junction to ambient thermal resistance in C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RJA and the value obtained on a four layer board RJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RJB x PD) with TB = Board temperature at the package perimeter in C RJB = Junction to board thermal resistance in C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Functional Block Requirements and Behaviors for more details on thermal management. 34VR500 82 Analog Integrated Circuit Device Data Freescale Semiconductor Packaging Packaging Dimensions 8 Packaging 8.1 Packaging Dimensions Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing's document number. See the Thermal Characteristics section for specific thermal characteristics for each package. Table 97. Package Drawing Information Package Suffix 56 QFN 8x8 mm - 0.5 mm pitch. WF-Type (wettable flank) ES Package Outline Drawing Number 98ASA00589D 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 83 Packaging Packaging Dimensions 34VR500 84 Analog Integrated Circuit Device Data Freescale Semiconductor Packaging Packaging Dimensions 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 85 Packaging Packaging Dimensions 34VR500 86 Analog Integrated Circuit Device Data Freescale Semiconductor Revision History Packaging Dimensions 9 Revision History Revision Date 1.0 5/2014 * Initial release 8/2014 * * * * * * SW2, SW3, and SW4 voltage range modification Table 6.1.2 added to explain how to change the start sequence. Table 95 added Added PC34VR500V2ES to the Orderable part Table 1 Update the 98A number Added Bill of Materials * * Updated Table 1 (corrected a typo) Updated values for VSW2ACC in Table 47 * * Updated values for VSW3ACC in Table 56 Updated values for VSW4ACC in Table 65 * * Updated package outline (changed 98ASA00379D to 98ASA00589D) Added optimized value for the buck regulator external components * Added MC34VR500V3ES, MC34VR500V4ES, MC34VR500V5ES to the Orderable Part Variations Table Added SW1, SW2, SW3, SW4 transient load plots Added SW1, SW2 efficiency plots Updated Control Interface I2C Block Description, I2C Device ID, and I2C Operation sections Updated SW2 rated current to 2.0 A 2.0 3.0 4.0 1/2015 7/2015 Description of Changes * * * * 34VR500 Analog Integrated Circuit Device Data Freescale Semiconductor 87 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. Home Page: freescale.com There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no on the information in this document. warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by customer's technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) 2015 Freescale Semiconductor, Inc. Document Number: MC34VR500 Rev. 4.0 7/2015 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Freescale Semiconductor: MC34VR500V2ES MC34VR500V1ES MC34VR500V1ESR2 MC34VR500V2ESR2 MC34VR500V4ES MC34VR500V4ESR2 MC34VR500V5ESR2 MC34VR500V5ES MC34VR500V6ESR2 MC34VR500V6ES