
Analog Integrated Circuit Device Data
6Freescale Semiconductor
34VR500
Pin Connections
Pin Definitions
7, 10, 12 PVIN1 (3) I 4.8 V Analog Input to SW1 regulator. Bypass with at least a 4.7 F ceramic capacitor and
a 0.1 F decoupling capacitor as close to the pin as possible.
8, 9, 11 LX1 (3) O 4.8 V Analog SW1 switching node connection
13 FB1 (3) I 3.6 V Analog Output voltage feedback for SW1. Route this trace separately from the high
current path and terminate at the output capacitance.
14 SGND1 GND - GND Signal ground for SW1 regulator. Connect to ground plane directly.
15 SGND2 GND - GND Signal ground for SW2 and SW4 regulators. Connect to ground plane
directly.
17 VLDOIN1 I 3.6 V Analog Input supply for LDO1. Bypass with a 1.0 F decoupling capacitor as close
to the pin as possible.
18 LDO1 O 2.5 V Analog LDO1 regulator output, Bypass with a 4.7 F ceramic output capacitor.
19 FB4 (3) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high
current path and terminate at the output capacitance.
20 PVIN4 (3) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7F ceramic capacitor and
a 0.1 F decoupling capacitor as close to the pin as possible.
21 LX4 (3) O 4.8 V Analog Regulator 4 switching node connection
22 LX2 (3) O 4.8 V Analog Regulator 2 switching node connection
23, 24 PVIN2 (3) I 4.8 V Analog
Input to SW2 regulator. Connect pins 23 and 24 together and bypass with at
least a 4.7 F ceramic capacitor and a 0.1 F decoupling capacitor as close
to these pins as possible.
25 FB2 (3) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high
current path and terminate at the output capacitance.
26 LDO2 O 3.6 V Analog LDO2 regulator output. Bypass with a 2.2 F ceramic output capacitor.
27 VLDOIN23 I 3.6 V Analog Input supply for LDO2 and LDO3. Bypass with a 1.0 F decoupling capacitor
as close to the pin as possible.
28 LDO3 O 3.6 V Analog LDO3 regulator output, Bypass with a 4.7 F ceramic output capacitor.
29 VHALF I 3.6 V Analog Half supply reference for DDR reference.
30 REFIN I 3.6 V Analog REFOUT regulator input. Bypass with at least 1.0 F decoupling capacitor
as close to the pin as possible.
31 REFOUT O 3.6 V Analog REFOUT regulator output
32 SGND3 GND - GND Ground reference for the SW3 regulator. Connect directly to ground plane.
34, 37 PVIN3 (3) I 4.8 V Analog Input to SW3 regulator. Bypass with at least a 4.7 F ceramic capacitor and
a 0.1 F decoupling capacitor as close to the pin as possible.
35, 36 LX3 (3) O 4.8 V Analog Regulator SW3 switching node connection
38 FB3 (3) I 3.6 V Analog Output voltage feedback for SW3. Route this trace separately from the high
current path and terminate at the output capacitance.
39 LDO4 O 3.6 V Analog LDO4 regulator output. Bypass with a 2.2 F ceramic output capacitor.
40 VLDOIN45 I 4.8 V Analog Input supply for LDO4 and LDO5. Bypass with a 1.0 F decoupling capacitor
as close to the pin as possible.
43 VBIAS I 1.8 V Analog Bypass the pin with a 0.47 F capacitor.
41 LDO5 O 3.6 V Analog LDO5 regulator output. By pass with a 2.2 F ceramic output capacitor.
47 ICTEST2 I 7.5 V Digital/
Analog Reserved pin. Connect to GND in application.
48 SGND4 GND - GND Ground for the main band gap regulator. Connect directly to ground plane.
49 VCC O 3.6 V Analog Analog Core supply
Table 2. 34VR500 Pin Definitions (continued)
Pin Number Pin Name Pin
Function Max. Rating Type Definition